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Commit 71c48d9d authored by Ben Avison's avatar Ben Avison
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Added definitions for the ARMv6 extensions to the CP15 cache type register 

Detail:
  This allows the cache properties of CPUs like the ARM1176JZF-S (as featured
  in the Raspberry Pi) to be correctly determined
Admin:
  Tested in a Raspberry Pi build

Version 2.07. Tagged as 'HdrSrc-2_07'
parent f5da1136
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Showing with 31 additions and 14 deletions
VersionNum
View file @ 71c48d9d
/* (2.06)
/* (2.07)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 2.06
#define Module_MajorVersion_CMHG 2.07
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 13 Apr 2012
#define Module_Date_CMHG 14 May 2012
#define Module_MajorVersion "2.06"
#define Module_Version 206
#define Module_MajorVersion "2.07"
#define Module_Version 207
#define Module_MinorVersion ""
#define Module_Date "13 Apr 2012"
#define Module_Date "14 May 2012"
#define Module_ApplicationDate "13-Apr-12"
#define Module_ApplicationDate "14-May-12"
#define Module_ComponentName "HdrSrc"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/HdrSrc"
#define Module_FullVersion "2.06"
#define Module_HelpVersion "2.06 (13 Apr 2012)"
#define Module_LibraryVersionInfo "2:6"
#define Module_FullVersion "2.07"
#define Module_HelpVersion "2.07 (14 May 2012)"
#define Module_LibraryVersionInfo "2:7"
hdr/MEMM/ARM600
View file @ 71c48d9d
......@@ -109,6 +109,7 @@ CR_TLBPurge CN 6 ; write
CR_IDCFlush CN 7 ; write-only
; Cache type register fields
; NOTE - need to be kept in sync with hdr.MEMM.VMSAv6!
CT_ctype_pos * 25
CT_ctype_mask * &F:SHL:CT_ctype_pos
......@@ -122,11 +123,15 @@ CT_Isize_mask * &FFF:SHL:CT_Isize_pos
CT_ctype_WT * 0 ; write-through cache
CT_ctype_WB_Crd * 1 ; write-back, clean by reading data
CT_ctype_WB_CR7 * 2 ; write-back, clean with register 7
CT_ctype_WB_Cal_LD * 5 ; write-back, clean by allocating data, lockdown (?)
CT_ctype_WB_Cal_LD * 5 ; write-back, clean by allocating data, lockdown (?)
CT_ctype_WB_CR7_LDd * 5 ; write-back, clean with register 7, lockdown (format D)
CT_ctype_WB_CR7_LDa * 6 ; write-back, clean with register 7, lockdown (format A)
CT_ctype_WB_CR7_LDb * 7 ; write-back, clean with register 7, lockdown (format B)
CT_ctype_WB_CR7_Lx * 8 ; write-back, clean with register 7, multiple cache levels
CT_ctype_WB_CR7_Lx * 8 ; write-back, clean with register 7, multiple cache levels
CT_ctype_WB_CR7_LDc * 14 ; write-back, clean with register 7, lockdown (format C)
CT_P_pos * 11
CT_P * 1:SHL:CT_P_pos
CT_size_pos * 6
CT_size_mask * 7:SHL:CT_size_pos
CT_assoc_pos * 3
......@@ -144,6 +149,7 @@ CT_size_8K * 4
CT_size_16K * 5
CT_size_32K * 6
CT_size_64K * 7
CT_size_128K * 8
CT_size_768 * 0
CT_size_1536 * 1
CT_size_3K * 2
......@@ -152,6 +158,7 @@ CT_size_12K * 4
CT_size_24K * 5
CT_size_48K * 6
CT_size_96K * 7
CT_size_192K * 8
CT_assoc_1 * 0
CT_assoc_2 * 1
......@@ -183,6 +190,7 @@ CT_M_8K * 0
CT_M_16K * 0
CT_M_32K * 0
CT_M_64K * 0
CT_M_128K * 0
CT_M_768 * 1
CT_M_1536 * 1
CT_M_3K * 1
......@@ -191,6 +199,7 @@ CT_M_12K * 1
CT_M_24K * 1
CT_M_48K * 1
CT_M_96K * 1
CT_M_192K * 1
......
hdr/MEMM/VMSAv6
View file @ 71c48d9d
......@@ -135,11 +135,15 @@ CT_Isize_mask * &FFF:SHL:CT_Isize_pos
CT_ctype_WT * 0 ; write-through cache
CT_ctype_WB_Crd * 1 ; write-back, clean by reading data
CT_ctype_WB_CR7 * 2 ; write-back, clean with register 7
CT_ctype_WB_Cal_LD * 5 ; write-back, clean by allocating data, lockdown (?)
CT_ctype_WB_Cal_LD * 5 ; write-back, clean by allocating data, lockdown (?)
CT_ctype_WB_CR7_LDd * 5 ; write-back, clean with register 7, lockdown (format D)
CT_ctype_WB_CR7_LDa * 6 ; write-back, clean with register 7, lockdown (format A)
CT_ctype_WB_CR7_LDb * 7 ; write-back, clean with register 7, lockdown (format B)
CT_ctype_WB_CR7_Lx * 8 ; write-back, clean with register 7, multiple cache levels
CT_ctype_WB_CR7_Lx * 8 ; write-back, clean with register 7, multiple cache levels
CT_ctype_WB_CR7_LDc * 14 ; write-back, clean with register 7, lockdown (format C)
CT_P_pos * 11
CT_P * 1:SHL:CT_P_pos
CT_size_pos * 6
CT_size_mask * 7:SHL:CT_size_pos
CT_assoc_pos * 3
......@@ -157,6 +161,7 @@ CT_size_8K * 4
CT_size_16K * 5
CT_size_32K * 6
CT_size_64K * 7
CT_size_128K * 8
CT_size_768 * 0
CT_size_1536 * 1
CT_size_3K * 2
......@@ -165,6 +170,7 @@ CT_size_12K * 4
CT_size_24K * 5
CT_size_48K * 6
CT_size_96K * 7
CT_size_192K * 8
CT_assoc_1 * 0
CT_assoc_2 * 1
......@@ -196,6 +202,7 @@ CT_M_8K * 0
CT_M_16K * 0
CT_M_32K * 0
CT_M_64K * 0
CT_M_128K * 0
CT_M_768 * 1
CT_M_1536 * 1
CT_M_3K * 1
......@@ -204,6 +211,7 @@ CT_M_12K * 1
CT_M_24K * 1
CT_M_48K * 1
CT_M_96K * 1
CT_M_192K * 1
......
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