Commit 6dfb8d83 authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Add protection against StrongARM conditional MSR CPSR_c bug

Detail:
  hdr/Machine/Machine - Add new StrongARM_MSR_bug global that's TRUE when we're targeting a StrongARM-compatible machine type.
  Corrected No26bitCode and No32bitCode comments to say that it's all about whether we're supporting 26/32bit processor modes, not about whether we're targetting 26/32bit only processors
  hdr/CPU/Generic32 - Modify macros to protect against StrongARM MSR bug where appropriate.
Admin:
  Tested with IOMD softload on StrongARM RiscPC.
  Fixes issue with Maestro crashing due to MSR bug creating a stack imbalance in SoundScheduler.


Version 1.96. Tagged as 'HdrSrc-1_96'
parent 8522d964
/* (1.95)
/* (1.96)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 1.95
#define Module_MajorVersion_CMHG 1.96
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 27 Jan 2012
#define Module_Date_CMHG 16 Feb 2012
#define Module_MajorVersion "1.95"
#define Module_Version 195
#define Module_MajorVersion "1.96"
#define Module_Version 196
#define Module_MinorVersion ""
#define Module_Date "27 Jan 2012"
#define Module_Date "16 Feb 2012"
#define Module_ApplicationDate "27-Jan-12"
#define Module_ApplicationDate "16-Feb-12"
#define Module_ComponentName "HdrSrc"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/HdrSrc"
#define Module_FullVersion "1.95"
#define Module_HelpVersion "1.95 (27 Jan 2012)"
#define Module_LibraryVersionInfo "1:95"
#define Module_FullVersion "1.96"
#define Module_HelpVersion "1.96 (16 Feb 2012)"
#define Module_LibraryVersionInfo "1:96"
......@@ -30,6 +30,10 @@ Included_Hdr_CPU_Generic32 SETL {TRUE}
; 05-Nov-99 KBracey Moved from ARM600.
; 32-bit versions of Generic26 macros created.
[ :LNOT: :DEF: Included_Hdr_Machine_Machine
GET Hdr:Machine.<Machine>
]
; 32-bit PSR transfer macros
; New positions of bits in 32-bit PSR
......@@ -137,7 +141,7 @@ CPU32_bits PSRto32 $bits
|
BIC$cond $regtmp, $srcreg, #CPU32_bits
]
somemsr $cond, CPSR, $regtmp, CPU32_bits
somemsr $cond, CPSR, $regtmp, CPU32_bits, unsafe
MEND
; **************************************************
......@@ -156,11 +160,11 @@ $label mymsr $cond, CPSR_f, #C_bit
MACRO
$label PHPSEI $register=R14, $regtmp
[ "$register" = ""
[ "$regtmp" = ""
[ "$regtmp" = "" :LOR: StrongARM_MSR_bug
$label mymrs AL, R14, CPSR
TST R14, #I32_bit ; is I32_bit set?
ORREQ R14, R14, #I32_bit ; no, then set it
mymsr EQ, CPSR_c, R14
mymsr EQ, CPSR_c, R14, , safe
BICEQ R14, R14, #I32_bit ; $reg contains original PSR
|
$label mymrs AL, R14, CPSR
......@@ -169,11 +173,11 @@ $label mymrs AL, R14, CPSR
mymsr EQ, CPSR_c, $regtmp ; $reg contains original PSR
]
|
[ "$regtmp" = ""
[ "$regtmp" = "" :LOR: StrongARM_MSR_bug
$label mymrs AL, $register, CPSR
TST $register, #I32_bit ; is I32_bit set?
ORREQ $register, $register, #I32_bit ; no, then set it
mymsr EQ, CPSR_c, $register
mymsr EQ, CPSR_c, $register, , safe
BICEQ $register, $register, #I32_bit ; $reg contains original PSR
|
$label mymrs AL, $register, CPSR
......@@ -221,7 +225,7 @@ $label
]
[ . - %BT01 = 0
; branch over on opposite condition
DCD &1A000001 :EOR: Cond_$cond
DCI &1A000001 :EOR: Cond_$cond
mymsr ,CPSR_f, #0
MOV pc, lr
]
......@@ -299,7 +303,7 @@ srcreg SETS "$regtmp"
srcreg SETS "$regtmp"
]
]
somemsr $cond, CPSR,$srcreg, CPU32_set:OR:CPU32_clr
somemsr $cond, CPSR,$srcreg, CPU32_set:OR:CPU32_clr, unsafe
MEND
; ****************************************************
......@@ -335,7 +339,7 @@ field SETS "f"
field SETS "$fields"
]
]
$label mymsr $cond, CPSR_$field, $reg
$label mymsr $cond, CPSR_$field, $reg, , unsafe
MEND
; **********************************************
......@@ -366,7 +370,7 @@ CPU32_bits PSRto32 $bits
|
ORR$cond $regtmp, $srcreg, #CPU32_bits
]
somemsr $cond, CPSR, $regtmp, CPU32_bits
somemsr $cond, CPSR, $regtmp, CPU32_bits, unsafe
MEND
; **************************************************
......@@ -392,7 +396,7 @@ srcreg SETS "$oldpsr"
$label mymrs $cond, $srcreg, CPSR
CPU32_bits PSRto32 $bits
EOR$cond $regtmp, $srcreg, #CPU32_bits
somemsr $cond, CPSR, $regtmp, CPU32_bits
somemsr $cond, CPSR, $regtmp, CPU32_bits, unsafe
MEND
; ***********************************************
......@@ -415,7 +419,7 @@ srcreg SETS "$oldpsr"
]
$label mymrs $cond, $srcreg, CPSR
EOR$cond $regtmp, $srcreg, $regtog
mymsr $cond, CPSR_$field, $regtmp
mymsr $cond, CPSR_$field, $regtmp, , unsafe
MEND
; *************************************************
......@@ -458,7 +462,7 @@ $label mymsr $cond, $psrl, $op2a, $op2b
; *** saving 2 cycles on some processors. ***
; ***************************************************
MACRO
$label somemsr $cond, $psr, $op, $mask
$label somemsr $cond, $psr, $op, $mask, $sabug
LCLS s
s SETS "$psr._"
[ (($mask) :AND: &FF) <> 0
......@@ -473,7 +477,7 @@ s SETS s:CC:"s"
[ (($mask) :AND: &FF000000) <> 0
s SETS s:CC:"f"
]
$label mymsr $cond, $s, $op
$label mymsr $cond, $s, $op, , $sabug
MEND
; Funny names for ObjAsm compatibility
......@@ -493,11 +497,25 @@ psrtype SETA 1 :SHL: 22
]
ASSERT psrtype <> -1
ASSERT $rd <> 15
& Cond_$cond :OR: 2_00000001000011110000000000000000 :OR: psrtype :OR: ($rd :SHL: 12)
DCI Cond_$cond :OR: 2_00000001000011110000000000000000 :OR: psrtype :OR: ($rd :SHL: 12)
MEND
; ****************************************************
; *** mymsr - Perform an MSR operation. ***
; *** If $sabug is set to "safe", it's assumed the ***
; *** code around this operation is sufficiently ***
; *** protected against the StrongARM conditional ***
; *** MSR CPSR_c bug. ***
; *** If $sabug is set to "unsafe", a NOP will ***
; *** automatically be inserted when generating an ***
; *** MSR that could trigger the bug (and we're ***
; *** targeting a StrongARM machine type). ***
; *** If $sabug is left unset, a warning and a NOP ***
; *** will be produced whenever a dangerous MSR is ***
; *** requested (if we're targeting StrongARM) ***
; ****************************************************
MACRO
$label mymsr $cond, $psrl, $op2a, $op2b
$label mymsr $cond, $psrl, $op2a, $op2b, $sabug
$label
LCLA psrtype
LCLS op2as
......@@ -573,7 +591,13 @@ op SETA ($op2a) :OR: (0:SHL:25)
! 1, "Shifted register not yet implemented in this macro!"
]
]
& Cond_$cond :OR: 2_00000001001000001111000000000000 :OR: op :OR: psrtype
DCI Cond_$cond :OR: 2_00000001001000001111000000000000 :OR: op :OR: psrtype
[ StrongARM_MSR_bug :LAND: "$sabug" <> "safe" :LAND: "$cond" <> "AL" :LAND: "$cond" <> "" :LAND: ((psrtype :AND: &410000) = &10000)
[ "$sabug" <> "unsafe"
! 0, "mymsr inserting NOP for StrongARM MSR CPSR_c bug"
]
NOP
]
MEND
; SetMode newmode, reg1, regoldpsr
......@@ -606,7 +630,7 @@ $lbl BKPT $val
[ $val < 0 :LOR: $val > &FFFF
! 0, "immediate value out of range"
]
DCD &E1200070 + ((($val) :SHR: 4) :SHL: 8) + (($val) :AND: &F)
DCI &E1200070 + ((($val) :SHR: 4) :SHL: 8) + (($val) :AND: &F)
MEND
] ; :LNOT: :DEF: Included_Hdr_CPU_Generic32
......
......@@ -139,13 +139,13 @@ HiResTTX SETL M_Lazarus :LOR: M_STB400 :LOR: M_STB5 :LOR: M_Tungsten
TTX256 SETL M_Tungsten :LOR: M_STB5
] ; :LNOT: M_All
; Do we support 26-bit only processors? (ARM2, ARM3)
; Are we only supporting 26bit processor modes?
; If true, we mustn't rely on MSR, MRS etc, and we should be
; RISC OS 3.1 compatible.
GBLL No32bitCode
No32bitCode SETL M_Archimedes :LOR: M_Morris :LOR: M_Phoebe :LOR: M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400
; Do we support 32-bit only processors? (ARM9, ARM10...)
; Are we only supporting 32bit processor modes?
GBLL No26bitCode
No26bitCode SETL M_32 :LOR: M_Lazarus :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_CortexA8 :LOR: M_CortexA9
......@@ -166,6 +166,10 @@ HAL26 SETL HAL :LAND: :LNOT: No26bitCode
GBLL NoUnaligned
NoUnaligned SETL M_CortexA8 :LOR: M_ARM11ZF :LOR: M_CortexA9
; Do we need to deal with the StrongARM conditional MSR CPSR_c bug?
GBLL StrongARM_MSR_bug
StrongARM_MSR_bug SETL M_All :LOR: M_32 :LOR: M_Phoebe
[ :LNOT: M_All
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; System build options added for STB/NCD
......
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