Commit 6b136a69 authored by Ben Avison's avatar Ben Avison Committed by ROOL
Browse files

Support Machine=CortexA53

Version 2.97. Tagged as 'HdrSrc-2_97'
parent b732bf72
/* (2.96)
/* (2.97)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
#define Module_MajorVersion_CMHG 2.96
#define Module_MajorVersion_CMHG 2.97
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 27 Nov 2021
#define Module_Date_CMHG 28 Jan 2022
#define Module_MajorVersion "2.96"
#define Module_Version 296
#define Module_MajorVersion "2.97"
#define Module_Version 297
#define Module_MinorVersion ""
#define Module_Date "27 Nov 2021"
#define Module_Date "28 Jan 2022"
#define Module_ApplicationDate "27-Nov-21"
#define Module_ApplicationDate "28-Jan-22"
#define Module_ComponentName "HdrSrc"
#define Module_FullVersion "2.96"
#define Module_HelpVersion "2.96 (27 Nov 2021)"
#define Module_LibraryVersionInfo "2:96"
#define Module_FullVersion "2.97"
#define Module_HelpVersion "2.97 (28 Jan 2022)"
#define Module_LibraryVersionInfo "2:97"
......@@ -329,6 +329,8 @@ MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_VE :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH :OR: MchFlg_Vv4 :OR: MchFlg_A
ELIF "$arch" = "v8"
MchFlgs SETA MchFlgs_v8
ELIF "$arch" = "v8_crypto"
MchFlgs SETA MchFlgs_v8 :OR: MchFlg_C
|
! 1, "Unrecognised architecture: $arch"
]
......@@ -370,6 +372,8 @@ MchFlgs_CumulativeNOT SETA MchFlgs_CumulativeNOT :OR: :NOT: MchFlgs
ArchitectureOption v7_VFP3D32_SIMD
ELIF "$Machine" = "CortexA9" ; Cortex A9, e.g. TI OMAP44xx, Freescale i.MX6
ArchitectureOption v7_VFP3D32H_SIMD
ELIF "$Machine" = "CortexA53" ; Cortex A53, A57, A35, A72 or A73, e.g. Allwinner A64, Broadcom BCM2837, Rockchip RK3399
ArchitectureOption v8_crypto
ELIF "$Machine" = "All" ; if the target code is required to run on
; any RISC OS machine
ArchitectureOption v2
......
; Copyright 2015 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
SUBT Cortex-A53/-A57/-A53/-A72/-A73 machine: Armv8.0-A + NEON + crypto
GBLS Machine
Machine SETS "CortexA53"
GET Hdr:Machine.Machine
END
......@@ -59,6 +59,7 @@ M_STB400 SETL Machine="STB400"
GBLL M_CortexA8
GBLL M_CortexA9
GBLL M_CortexA7
GBLL M_CortexA53
GBLL M_IOMD
GBLL M_STB5
GBLL M_Tungsten
......@@ -72,12 +73,16 @@ M_RPi SETL Machine="RPi"
M_CortexA8 SETL Machine="CortexA8"
M_CortexA9 SETL Machine="CortexA9"
M_CortexA7 SETL Machine="CortexA7"
M_CortexA53 SETL Machine="CortexA53"
M_IOMD SETL Machine="IOMD"
M_STB5 SETL Machine="STB5"
M_Tungsten SETL Machine="Tungsten"
[ Machine="CortexA15" :LOR: Machine="CortexA17"
! 1, "You probably wanted to use Machine=CortexA7"
]
[ Machine="CortexA35" :LOR: Machine="CortexA57" :LOR: Machine="CortexA72" :LOR: Machine="CortexA73"
! 1, "You probably wanted to use Machine=CortexA53"
]
; Are we only supporting 26bit processor modes?
; If true, we mustn't rely on MSR, MRS etc, and we should be
......@@ -87,7 +92,7 @@ No32bitCode SETL M_26 :LOR: M_Archimedes :LOR: M_Morris :LOR: M_Falcon :L
; Are we only supporting 32bit processor modes?
GBLL No26bitCode
No26bitCode SETL M_32 :LOR: M_Lazarus :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9 :LOR: M_CortexA7
No26bitCode SETL M_32 :LOR: M_Lazarus :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9 :LOR: M_CortexA7 :LOR: M_CortexA53
; If this makes your head hurt, the other way of looking at it is
; 26/32 neutral => No32bitCode FALSE No26bitCode FALSE
......@@ -98,7 +103,7 @@ No26bitCode SETL M_32 :LOR: M_Lazarus :LOR: M_IOMD :LOR: M_Tungsten :LOR:
; Override optimisation settings to avoid using unaligned LDR(H)/STR(H) on ARMv6+
; This switch should only be enabled for debugging purposes
GBLL NoUnaligned
NoUnaligned SETL M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9 :LOR: M_CortexA7
NoUnaligned SETL M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9 :LOR: M_CortexA7 :LOR: M_CortexA53
; Do we need to deal with the StrongARM conditional MSR CPSR_c bug?
GBLL StrongARM_MSR_bug
......@@ -136,7 +141,7 @@ MEMC_Type SETS "IOMD"
GetMEMC SETS "GET Hdr:IO." :CC: MEMC_Type
GBLS MEMM_Type
[ M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9 :LOR: M_CortexA7
[ M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9 :LOR: M_CortexA7 :LOR: M_CortexA53
MEMM_Type SETS "VMSAv6"
|
MEMM_Type SETS "ARM600"
......@@ -180,7 +185,7 @@ DontUseVCO SETL M_Lazarus :LOR: M_STB400
; Are we using a HAL?
GBLL HAL
HAL SETL M_32 :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9 :LOR: M_CortexA7
HAL SETL M_32 :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9 :LOR: M_CortexA7 :LOR: M_CortexA53
; General flag for STB/NCD-type products
GBLL STB
......@@ -209,7 +214,7 @@ MaxI2Cspeed SETA 100
; E2ROM is supported at i2c addresses >= A8 in addition to normal CMOS RAM
; Note that this also controls HAL NVRAM support, and RTCSupport.
GBLL E2ROMSupport
E2ROMSupport SETL M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400 :LOR: M_STB5 :LOR: M_Lazarus :LOR: M_32 :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9 :LOR: M_CortexA7
E2ROMSupport SETL M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400 :LOR: M_STB5 :LOR: M_Lazarus :LOR: M_32 :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9 :LOR: M_CortexA7 :LOR: M_CortexA53
; Support for network 'podule' cards
GBLL NetPodSupport
......
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