Commit 559a684e authored by Stewart Brodie's avatar Stewart Brodie
Browse files

Merge of 32-bit capable macros to trunk.

Detail:
  The 26-bit and 32-bit capable macros have been added.
  Header files choose which set of macros to use based on <Machine>.
  If you want the new macros, include "Hdr:APCS.<APCS>" in addition
    to the usual inclusions at the top of assembler files.
  Choices are based on the settings of macros No32bitCode and
    No26bitCode.  By default, all existing machines define these
    as {TRUE} and {FALSE} respectively.  This yields the same macros
    as before (tested in Customer F 5 build) and should yield code which
    functions on RISC OS 3.1.  Any other combination of settings is
    untested at this time.
  New assembler code should use the macros FunctionEntry, Return et al
    to ensure that they build correctly.
  New assembler code should be written to not require flag preservation
    across internal function calls and to not assume it on external
    function calls where it is possible to do so.  DO NOT simply replace
    "MOVS pc, lr" with "MOV pc, lr" as this doesn't work properly.
    Replace "MOVS pc, lr" with "Return ,LinkNotStacked"
  Do not write code which simply masks out &FC000003 from pc or some kind
    or pc originated value (eg. on r14 to attempt to remove the PSR flags
    from it.  Use the RemovePSRFromReg macro instead.
Admin:
  Tested with Customer F 5 build.
  Requires FPEmulator 4.11
  Requires Portable 0.65 (or Portable75 0.04)
  Required by any new or modified assembler code in future, pretty much.
    Such components may not necessarily specify a dependency on this
    or any other later version of HdrSrc.

Version 0.63. Tagged as 'HdrSrc-0_63'
parent ae7fb614
......@@ -34,7 +34,8 @@
#
# Paths
#
HDRDIR = <hdr$dir>.Global
TOPDIR = <hdr$dir>
HDRDIR = ${TOPDIR}.Global
HDIR = <CExport$dir>
LIBDIR = <Lib$Dir>
......@@ -62,11 +63,14 @@ TOKENS = Hdr:Tokens
COMPONENT = HdrSrc
EXPORTS = \
${HDRDIR}.APCS.<APCS> \
${HDRDIR}.APCS.Common \
${HDRDIR}.AUN \
${HDRDIR}.CMOS \
${HDRDIR}.Countries \
${HDRDIR}.CPU.ARM600 \
${HDRDIR}.CPU.Generic26 \
${HDRDIR}.CPU.Generic32 \
${HDRDIR}.DDVMacros \
${HDRDIR}.Debug \
${HDRDIR}.Devices \
......@@ -154,8 +158,9 @@ export: ${OPTIONS} ${EXPORTS} Dirs
Dirs:
${MKDIR} ${HDRDIR}
${MKDIR} ${HDRDIR}.^.Interface
${MKDIR} ${HDRDIR}.^.Interface2
${MKDIR} ${TOPDIR}.Interface
${MKDIR} ${TOPDIR}.Interface2
${MKDIR} ${HDRDIR}.APCS
${MKDIR} ${HDRDIR}.CPU
${MKDIR} ${HDRDIR}.FDC
${MKDIR} ${HDRDIR}.IO
......@@ -181,9 +186,10 @@ clean:
# Special rule for exporting all ImageSize and Machine files.
# Trigger by invoking the export with OPTIONS=ALL.
#
ALL: ${HDRDIR}.Machine.Machine ${HDRDIR}.ImageSize.<ImageSize>
ALL: ${HDRDIR}.Machine.Machine ${HDRDIR}.ImageSize.<ImageSize> ${HDRDIR}.APCS.<APCS>
${CP} hdr.Machine ${HDRDIR}.Machine ${CPFLAGS}
${CP} hdr.ImageSize ${HDRDIR}.ImageSize ${CPFLAGS}
${CP} hdr.APCS ${HDRDIR}.APCS ${CPFLAGS}
#
# Rules for deriving headers:
......@@ -278,8 +284,11 @@ ${HDIR}.Global.h.IOCtl: h.IOCtl; ${CP} h.IOCtl
${HDRDIR}.Machine.<Machine>: hdr.Machine.<Machine>; ${CP} hdr.Machine.<Machine> $@ ${CPFLAGS}
${HDRDIR}.Machine.Machine: hdr.Machine.Machine; ${CP} hdr.Machine.Machine $@ ${CPFLAGS}
${HDRDIR}.ImageSize.<ImageSize>: hdr.ImageSize.<ImageSize>; ${CP} hdr.ImageSize.<ImageSize> $@ ${CPFLAGS}
${HDRDIR}.APCS.<APCS>: hdr.APCS.<APCS>; ${CP} hdr.APCS.<APCS> $@ ${CPFLAGS}
${HDRDIR}.APCS.Common: hdr.APCS.Common; ${CP} hdr.APCS.Common $@ ${CPFLAGS}
${HDRDIR}.CPU.ARM600: hdr.CPU.ARM600; ${CP} hdr.CPU.ARM600 $@ ${CPFLAGS}
${HDRDIR}.CPU.Generic26: hdr.CPU.Generic26; ${CP} hdr.CPU.Generic26 $@ ${CPFLAGS}
${HDRDIR}.CPU.Generic32: hdr.CPU.Generic32; ${CP} hdr.CPU.Generic32 $@ ${CPFLAGS}
${HDRDIR}.FDC.FDC711: hdr.FDC.FDC711; ${CP} hdr.FDC.FDC711 $@ ${CPFLAGS}
${HDRDIR}.IO.GenericIO: hdr.IO.GenericIO; ${CP} hdr.IO.GenericIO $@ ${CPFLAGS}
${HDRDIR}.IO.IOC: hdr.IO.IOC; ${CP} hdr.IO.IOC $@ ${CPFLAGS}
......
/* (0.62)
/* (0.63)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
#define Module_MajorVersion_CMHG 0.62
#define Module_MajorVersion_CMHG 0.63
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 19 Nov 1999
#define Module_Date_CMHG 26 Nov 1999
#define Module_MajorVersion "0.62"
#define Module_Version 62
#define Module_MajorVersion "0.63"
#define Module_Version 63
#define Module_MinorVersion ""
#define Module_Date "19 Nov 1999"
#define Module_Date "26 Nov 1999"
#define Module_FullVersion "0.62"
#define Module_FullVersion "0.63"
; Copyright 1999 Pace Micro Technology plc
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; > Hdr:APCS.APCS-32
GBLS APCS_Type
APCS_Type SETS "APCS-32"
GET Hdr:APCS.Common
END
; Copyright 1999 Pace Micro Technology plc
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; > Hdr:APCS.APCS-R
GBLS APCS_Type
APCS_Type SETS "APCS-R"
[ No26bitCode
! 1, "You can't use APCS-R with No26bitCode"
]
GET Hdr:APCS.Common
END
; Copyright 1999 Pace Micro Technology plc
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; > Hdr:APCS.Common
OldOpt SETA {OPT}
OPT OptNoList+OptNoP1List
[ :LNOT: :DEF: Included_Hdr_APCS
GBLL Included_Hdr_APCS
Included_Hdr_APCS SETL {TRUE}
; All the following macros use {CONFIG} to determine the APCS in force.
; This means they are NOT directly affected by the APCS variable.
; This allows them to work when the APCS has been overridden - for example
; the SharedCLibrary will build using APCS-R to keep 26-bit compatibility
; where possible.
; This also means that these macros are not AAsm compatible.
; *****************************************
; *** Pull registers given in reglist ***
; *****************************************
MACRO
$label PullAPCS $reglist, $cond
[ "$reglist" :RIGHT: 2 <> "pc" :LAND: "$reglist" :RIGHT: 2 <> "PC"
! 1, "PullAPCS must pull PC at the end. Use Pull instead"
]
[ {CONFIG}=26
$label LDM$cond.FD sp!, {$reglist}^
|
$label LDM$cond.FD sp!, {$reglist}
]
MEND
; *****************************
; *** APCS function entry ***
; *****************************
MACRO
FunctionEntry $SaveList, $MakeFrame
LCLS Temps
LCLS TempsC
Temps SETS "$SaveList"
TempsC SETS ""
[ Temps <> ""
TempsC SETS Temps :CC: ","
]
[ "$MakeFrame" = ""
Push "$TempsC.lr"
|
MOV ip, sp
Push "$TempsC.fp,ip,lr,pc"
SUB fp, ip, #4
]
MEND
; ******************************
; *** APCS function return ***
; ******************************
MACRO
Return $ReloadList, $Base, $CC, $linkreg
LCLS Temps
LCLS Tempr
Temps SETS "$ReloadList"
Tempr SETS "$linkreg"
[ "$Base"<>"LinkNotStacked" :LAND: "$Base"<>"" :LAND: "$Base"<>"fpbased"
! 1, "Unrecognised value for $Base"
]
[ "$Base"="LinkNotStacked" :LAND: "$ReloadList"=""
[ "$Tempr" = ""
Tempr SETS "lr"
]
|
[ "$Tempr" <> ""
! 1, "Return address cannot be held in register when LR is stacked"
]
]
[ {CONFIG} = 26
[ "$Base" = "LinkNotStacked" :LAND: "$ReloadList"=""
MOV$CC.S pc, $Tempr
|
[ Temps <> ""
Temps SETS Temps :CC: ","
]
[ "$Base" = "fpbased"
LDM$CC.DB fp, {$Temps.fp,sp,pc}^
|
LDM$CC.FD sp!, {$Temps.pc}^
]
]
|
[ "$Base" = "LinkNotStacked" :LAND: "$ReloadList"=""
MOV$CC pc, $Tempr
|
[ Temps <> ""
Temps SETS Temps :CC: ","
]
[ "$Base" = "fpbased"
LDM$CC.DB fp, {$Temps.fp,sp,pc}
|
LDM$CC.FD sp!, {$Temps.pc}
]
]
]
MEND
; This function goes with those in Hdr:Proc
; *****************************************************************************
; *** Exit procedure, restore stack and saved registers to values on entry. ***
; *** Restore PSR if APCS-R in force. ***
; *****************************************************************************
MACRO
$label EXITAPCS $cond
$label
[ Proc_SavedCPSR
! 1, "Don't use EntryS with EXITAPCS"
]
[ Proc_LocalStack <> 0
ADD$cond sp, sp, #Proc_LocalStack
]
[ APCS = "APCS-R"
[ "$Proc_RegList" = ""
Pull "pc",$cond,^
|
Pull "$Proc_RegList, pc",$cond,^
]
|
[ "$Proc_RegList" = ""
LDR$cond pc, [sp], #4
|
Pull "$Proc_RegList, pc",$cond
]
]
MEND
] ; :LNOT::DEF:Included_Hdr_APCS
OPT OldOpt
END
......@@ -27,160 +27,10 @@ OldOpt SETA {OPT}
; 04-Jan-93 BCockburn Moved processor specific macros from Hdr:Macros
; 04-Jan-93 BCockburn Made ARM3 specific
; 13-Jul-93 JRoach Strip out generic stuff
; 04-Nov-99 KBracey Moved all to Hdr:CPU.Generic26
;
; ARM600 CPU model related things
; ARM6 PSR transfer macros
; Condition code symbols
Cond_EQ * 0 :SHL: 28
Cond_NE * 1 :SHL: 28
Cond_CS * 2 :SHL: 28
Cond_HS * Cond_CS
Cond_CC * 3 :SHL: 28
Cond_LO * Cond_CC
Cond_MI * 4 :SHL: 28
Cond_PL * 5 :SHL: 28
Cond_VS * 6 :SHL: 28
Cond_VC * 7 :SHL: 28
Cond_HI * 8 :SHL: 28
Cond_LS * 9 :SHL: 28
Cond_GE * 10 :SHL: 28
Cond_LT * 11 :SHL: 28
Cond_GT * 12 :SHL: 28
Cond_LE * 13 :SHL: 28
Cond_AL * 14 :SHL: 28
Cond_ * Cond_AL
Cond_NV * 15 :SHL: 28
; New positions of I and F bits in 32-bit PSR
I32_bit * 1 :SHL: 7
F32_bit * 1 :SHL: 6
IF32_26Shift * 26-6
; Processor mode numbers
USR26_mode * 2_00000
FIQ26_mode * 2_00001
IRQ26_mode * 2_00010
SVC26_mode * 2_00011
USR32_mode * 2_10000
FIQ32_mode * 2_10001
IRQ32_mode * 2_10010
SVC32_mode * 2_10011
ABT32_mode * 2_10111
UND32_mode * 2_11011
; New register names
r13_abort RN 13
r14_abort RN 14
lr_abort RN 14
r13_undef RN 13
r14_undef RN 14
lr_undef RN 14
MACRO
mrs $cond, $rd, $psrs
LCLA psrtype
psrtype SETA -1
[ "$psrs" = "CPSR" :LOR: "$psrs" = "CPSR_all"
psrtype SETA 0 :SHL: 22
]
[ "$psrs" = "SPSR" :LOR: "$psrs" = "SPSR_all"
psrtype SETA 1 :SHL: 22
]
ASSERT psrtype <> -1
ASSERT $rd <> 15
& Cond_$cond :OR: 2_00000001000011110000000000000000 :OR: psrtype :OR: ($rd :SHL: 12)
MEND
MACRO
msr $cond, $psrl, $op2a, $op2b
LCLA psrtype
LCLS op2as
LCLA op
LCLA shift
psrtype SETA -1
[ "$psrl" = "CPSR" :LOR: "$psrl" = "CPSR_all"
psrtype SETA (0:SHL:22) :OR: (1:SHL:19) :OR: (1:SHL:16)
]
[ "$psrl" = "CPSR_flg"
psrtype SETA (0:SHL:22) :OR: (1:SHL:19) :OR: (0:SHL:16)
]
[ "$psrl" = "CPSR_ctl"
psrtype SETA (0:SHL:22) :OR: (0:SHL:19) :OR: (1:SHL:16)
]
[ "$psrl" = "SPSR" :LOR: "$psrl" = "SPSR_all"
psrtype SETA (1:SHL:22) :OR: (1:SHL:19) :OR: (1:SHL:16)
]
[ "$psrl" = "SPSR_flg"
psrtype SETA (1:SHL:22) :OR: (1:SHL:19) :OR: (0:SHL:16)
]
[ "$psrl" = "SPSR_ctl"
psrtype SETA (1:SHL:22) :OR: (0:SHL:19) :OR: (1:SHL:16)
]
ASSERT psrtype <> -1
[ ("$op2a" :LEFT: 1) = "#"
; Immediate operand
op2as SETS "$op2a" :RIGHT: ((:LEN: "$op2a")-1)
op SETA $op2as
[ "$op2b" = ""
; Rotate not specified in immediate operand
shift SETA 0
WHILE (op :AND: &FFFFFF00)<>0 :LAND: shift<16
op SETA ((op:SHR:30):AND:3):OR:(op:SHL:2)
shift SETA shift + 1
WEND
ASSERT (op :AND: &FFFFFF00)=0
|
; Rotate of immediate operand specified explicitly
ASSERT (($op2b):AND:&FFFFFFE1)=0
shift SETA ($opt2b):SHR:1
]
op SETA (shift :SHL: 8) :OR: op :OR: (1:SHL:25)
|
; Not an immediate operand
[ "$op2b" = ""
; Unshifted register
op SETA ($op2a) :OR: (0:SHL:25)
|
! 1, "Shifted register not yet implemented in this macro!"
]
]
& Cond_$cond :OR: 2_00000001001000001111000000000000 :OR: op :OR: psrtype
MEND
; SetMode newmode, reg1, regoldpsr
;
; Sets processor mode to constant value newmode
; using register reg1 as a temporary.
; If regoldpsr is specified, then this register
; on exit holds the old PSR before the mode change
; reg1 on exit always holds the new PSR after the mode change
MACRO
SetMode $newmode, $reg1, $regoldpsr
[ "$regoldpsr"=""
mrs AL, $reg1, CPSR_all
BIC $reg1, $reg1, #&1F
ORR $reg1, $reg1, #$newmode
msr AL, CPSR_all, $reg1
|
mrs AL, $regoldpsr, CPSR_all
BIC $reg1, $regoldpsr, #&1F
ORR $reg1, $reg1, #$newmode
msr AL, CPSR_all, $reg1
]
MEND
OPT OldOpt
END
......@@ -25,6 +25,19 @@ OldOpt SETA {OPT}
; ---- ---- -----------
; 13-Jul-93 JRoach Created
; 30-Jun-94 AMcC Restore OPT
; 05-Nov-99 KBracey Keep an eye on No26bitCode flag
GBLS CPU26_GetMachine
[ :LNOT: :DEF: Included_Hdr_Machine_Machine
CPU26_GetMachine SETS "GET Hdr:Machine.<Machine>"
|
CPU26_GetMachine SETS ""
]
$CPU26_GetMachine
[ :LNOT: :DEF: Included_Hdr_CPU_Generic26
GBLL Included_Hdr_CPU_Generic26
Included_Hdr_CPU_Generic26 SETL {TRUE}
; Standard register names
......@@ -94,8 +107,10 @@ LINK RN r14
pc RN r15 ; Program Counter
PC RN r15
[ :LNOT: No26bitCode
psr RN r15 ; Processor Status Register
PSR RN r15
]
; Registers for the ARM Procedure Calling Standard
......@@ -108,6 +123,28 @@ IP RN 12
ip RN 12
; Condition code symbols
Cond_EQ * 0 :SHL: 28
Cond_NE * 1 :SHL: 28
Cond_CS * 2 :SHL: 28
Cond_HS * Cond_CS
Cond_CC * 3 :SHL: 28
Cond_LO * Cond_CC
Cond_MI * 4 :SHL: 28
Cond_PL * 5 :SHL: 28
Cond_VS * 6 :SHL: 28
Cond_VC * 7 :SHL: 28
Cond_HI * 8 :SHL: 28
Cond_LS * 9 :SHL: 28
Cond_GE * 10 :SHL: 28
Cond_LT * 11 :SHL: 28
Cond_GT * 12 :SHL: 28
Cond_LE * 13 :SHL: 28
Cond_AL * 14 :SHL: 28
Cond_ * Cond_AL
Cond_NV * 15 :SHL: 28
; Flag position specifiers for the PSR
N_bit_number * 31
......@@ -126,6 +163,7 @@ C_bit * 1 :SHL: C_bit_number
V_bit * 1 :SHL: V_bit_number
I_bit * 1 :SHL: I_bit_number
F_bit * 1 :SHL: F_bit_number
M_bits * 2_11
; Processor mode values for the PSR
......@@ -171,6 +209,7 @@ $label Push R14
Pull R14
MEND
[ No32bitCode
; ************************************************
; *** CLC - Clear carry flag - will set nzcv ***
; ************************************************
......@@ -202,7 +241,7 @@ $label CMP$cond pc, #0
; *** register, default R14. Note that this code preserves the C and V flags. ***
; **********************************************************************************
MACRO
$label PHPSEI $register
$label PHPSEI $register, $regtmp ; (we don't use regtmp, 32-bit one does)
[ "$register" = ""
$label MOV R14, #I_bit
TST R14, PC ; is I_bit set ?
......@@ -221,13 +260,14 @@ $label MOV $register, #I_bit
; *** by PHPSEI). Note that this code preserves the C and V flags. ***
; **************************************************************************
MACRO
$label PLP $register
$label PLP $register=R14
[ "$register" = ""
$label TEQP R14, PC
|
$label TEQP $register, PC
]
MEND
]
; ****************
; *** RETURN ***
......@@ -237,6 +277,7 @@ $label RETURN $cond
$label MOV$cond pc, lr
MEND
[ :LNOT: No26bitCode
; *****************
; *** RETURNS ***
; *****************
......@@ -244,6 +285,42 @@ $label MOV$cond pc, lr
$label RETURNS $cond
$label MOV$cond.S pc, lr
MEND
]
[ No32bitCode
; ******************
; *** RETURNVC ***
; ******************
MACRO
$label RETURNVC $cond
$label BIC$cond.S pc, lr, #V_bit
MEND
; ******************
; *** RETURNVS ***
; ******************
MACRO
$label RETURNVS $cond
$label ORR$cond.S pc, lr, #V_bit
MEND
; ****************************************************
; *** SavePSR - Save the PSR in a register, to be ***
; *** restored later using RestorePSR ***
; ****************************************************
MACRO
$label SavePSR $reg, $cond
$label MOV$cond $reg, pc
MEND
; ****************************************************
; *** RestPSR - Restore the PSR from a register ***
; *** set up by SavePSR ***
; ****************************************************
MACRO
$label RestPSR $reg, $cond, $fields
$label TEQ$cond.P pc, $reg
MEND
; ****************************************************
; *** SCPSR - Set and clear bits in PSR from the ***
......@@ -251,6 +328,9 @@ $label MOV$cond.S pc, lr
; ****************************************************
MACRO
$label SCPSR $set, $clr, $regtmp, $cond
[ ($set :AND: $clr) <> 0
! 0, "Attempt to simultaneously set and clear a bit in SCPSR"
]
$label MOV$cond $regtmp, pc
ORR$cond $regtmp, $regtmp, #($set) :OR: ($clr)
TEQ$cond.P $regtmp, #$clr
......@@ -293,5 +373,59 @@ $label MOV$cond $regtmp, pc
TEQ$cond.P $regtmp, #$bits
MEND
; *************************************************
; *** WritePSRc - Set the PSR control bits to ***
; *** an absolute value. ***
; *** Sets I,F,M[0:1], corrupts NZVC. ***
; *** Preserves 32-bitness. ***
; *** Only use in IRQ26/32,FIQ26/32,SVC26/32 ***
; *** Ignored in USR modes, illegal in others ***
; *** Use instead of TEQP PC,#$value ***
; *************************************************
MACRO
$label WritePSRc $value, $regtmp
$label TEQP PC, #$value
MEND
]
MACRO
$label RemovePSRFromReg $pcr, $tmp, $dest
; This macro masks out the PSR bits from a pc (or register holding a pc -
; eg. lr). It does so only in 26-bit modes, and is required to not affect
; any PSR flags. If $dest is supplied, it denotes an alternative target
; register from $pcr. $dest and $tmp may be the same register.
;
; MRS is safe as it is a NOP if the processor doesn't understand it. The code
; takes bit 4 of the CPSR (always set in 32-bit modes, always clear in 26-bit
; modes), shifts it to the bottom bit and inverts it, then shifts it to the
; top bit so it can use ASR to duplicate it into 8 bits, and then ROR#30 to