Commit 4f610204 authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Bring trunk HdrSrc.hdr.Macros in line with Cortex version

Detail:
  * LD macro updated to know about LDRH and LDRD instructions
  * LDW macro updated: safe to use on last word of a page; no longer enforces
    relative order of temporary registers; uses unaligned loads when possible;
    uses 1 fewer instructions if ARMv6 compatibility is not required;
    scheduled for XScale and Cortex-A8
Admin:
  Tested with BASIC softload on RISC OS 5.12 Iyonix.
  Fixes bug #220


Version 1.72. Tagged as 'HdrSrc-1_72'
parent c522f63f
/* (1.71)
/* (1.72)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 1.71
#define Module_MajorVersion_CMHG 1.72
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 03 Jul 2009
#define Module_Date_CMHG 25 Oct 2009
#define Module_MajorVersion "1.71"
#define Module_Version 171
#define Module_MajorVersion "1.72"
#define Module_Version 172
#define Module_MinorVersion ""
#define Module_Date "03 Jul 2009"
#define Module_Date "25 Oct 2009"
#define Module_ApplicationDate "03-Jul-09"
#define Module_ApplicationDate "25-Oct-09"
#define Module_ComponentName "HdrSrc"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/HdrSrc"
#define Module_FullVersion "1.71"
#define Module_HelpVersion "1.71 (03 Jul 2009)"
#define Module_LibraryVersionInfo "1:71"
#define Module_FullVersion "1.72"
#define Module_HelpVersion "1.72 (25 Oct 2009)"
#define Module_LibraryVersionInfo "1:72"
......@@ -1031,16 +1031,26 @@ $label
; ***********************************************
MACRO
$label LD $reg,$var,$cc
[ ( ?$var = 1 ) :LOR: ( ?$var = 4 )
[ ?$var = 1
$label LDR$cc.B $reg, $var
|
[ ?$var = 2
ASSERT :LNOT: NoARMv4
$label LDR$cc.H $reg, $var
|
[ ?$var = 4
$label LDR$cc $reg, $var
]
|
! 0, "What do you think your doing??"
[ ?$var = 8
ASSERT :LNOT: NoARMP
$label LDR$cc.D $reg, $var
|
! 0, "What do you think you're doing??"
! 0, "Size of " :CC: "$var" :CC: " is " :CC: :STR: ?$var
]
]
]
]
MEND
; ***************************************
......@@ -1052,19 +1062,45 @@ $label MOV$cond $reg, #0
LDR$cond.B $reg, [$reg, #OsbyteVars+$var-OSBYTEFirstVar]
MEND
; ************************************************
; *** LDW - Load word from unknown alignment ***
; ************************************************
; ****************************************************
; *** LDW - Load word from unknown alignment ***
; *** $dest and $addr are allowed to match, ***
; *** otherwise all registers must differ. ***
; *** Now safe to use where $addr+4 would abort. ***
; *** No longer restricts register numbers. ***
; ****************************************************
MACRO
$label LDW $dest, $addr, $temp1, $temp2
ASSERT $dest < $temp2
$label BIC $temp1, $addr, #3
LDMIA $temp1, {$dest, $temp2}
AND $temp1, $addr, #3
MOVS $temp1, $temp1, LSL #3
$label
[ NoARMv6 :LOR: NoUnaligned
; Mustn't use v6-only features. May or may not need to run on v6 processors.
; Optimised for Cortex-A8 if SupportARMv6, or for XScale if not
ANDS $temp1, $addr, #3
[ SupportARMv6
BIC $temp2, $addr, #3
LDREQ $dest, [$addr]
LDMNEIA $temp2, {$dest, $temp2}
MOVNE $temp1, $temp1, LSL #3
|
LDMNEIA $addr, {$dest, $temp2}
MOVNE $temp1, $temp1, LSL #3
LDREQ $dest, [$addr]
]
[ $dest < $temp2
MOVNE $dest, $dest, LSR $temp1
|
MOVNE $temp2, $temp2, LSR $temp1
]
RSBNE $temp1, $temp1, #32
[ $dest < $temp2
ORRNE $dest, $dest, $temp2, LSL $temp1
|
ORRNE $dest, $temp2, $dest, LSL $temp1
]
|
; OK to use v6-only features
LDR $dest, [$addr]
]
MEND
; *******************************************
......
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