Commit 41952da2 authored by Ben Avison's avatar Ben Avison
Browse files

Fresh commit of Machine and UserIF headers to lose the revision history

(which contains sensitive customer data).
parent dc267498
; Copyright 2008 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
SUBT Definition of the machine
OldOpt SETA {OPT}
OPT OptNoList+OptNoP1List
[ :LNOT: :DEF: Included_Hdr_Machine_Machine
GBLL Included_Hdr_Machine_Machine
Included_Hdr_Machine_Machine SETL {TRUE}
; ***********************************
; *** C h a n g e L i s t ***
; ***********************************
;
; Date Name Description
; ---- ---- -----------
; 21-Apr-97 SMC Now only one header file.
; Define Machine variable and set it by including appropriate header.
;
; Define boolean variables for each machine to avoid possibility of typos in
; strings. NEVER use these outside this header file. Use feature tests
; instead.
GBLL M_Falcon
GBLL M_Morris
GBLL M_Omega
GBLL M_Lazarus
GBLL M_Peregrine
GBLL M_STB3
GBLL M_STB400
GBLL M_STB5
GBLL M_Phoebe
GBLL M_Tungsten
GBLL M_32
M_Falcon SETL Machine="Falcon"
M_Morris SETL Machine="Morris"
M_Omega SETL Machine="Omega"
M_Lazarus SETL Machine="Lazarus"
M_Peregrine SETL Machine="Peregrine"
M_STB3 SETL Machine="STB3"
M_STB400 SETL Machine="STB400"
M_STB5 SETL Machine="STB5"
M_Phoebe SETL Machine="Phoebe"
M_Tungsten SETL Machine="Tungsten"
M_32 SETL Machine="32"
GBLS SystemName
[ M_Omega :LOR: M_Lazarus
SystemName SETS "NC OS"
|
SystemName SETS "RISC OS"
]
; CPU type (processor model, excluding cache and memory management)
GBLS CPU_Type
CPU_Type SETS "ARM600"
GBLS GetCPU
GetCPU SETS ("GET Hdr:CPU." :CC: "$CPU_Type")
; IO type (non generic interrupt masks, some IO locations)
GBLS IO_Type
IO_Type SETS "IOMD"
GBLS GetIO
GetIO SETS ("GET Hdr:IO." :CC: "$IO_Type")
; Video controller - does the sound too
GBLS VIDC_Type
VIDC_Type SETS "VIDC20"
GBLS GetVIDC
GetVIDC SETS "GET Hdr:VIDC." :CC: VIDC_Type
; Memory controller, excluding memory management stuff. This
; one deals with memory speeds and DMA
GBLS MEMC_Type
MEMC_Type SETS "IOMD"
GBLS GetMEMC
GetMEMC SETS "GET Hdr:IO." :CC: MEMC_Type
GBLS MEMM_Type
MEMM_Type SETS "ARM600"
GBLS GetMEMM
GetMEMM SETS "GET Hdr:MEMM.ARM600"
; floppy controller
GBLS FDC_Type
FDC_Type SETS "FDC711"
GBLS GetFDC
GetFDC SETS "GET Hdr:FDC." :CC: FDC_Type
GBLL NewClockChip
NewClockChip SETL {TRUE}
GBLS Keyboard_Type
[ M_Lazarus
Keyboard_Type SETS "RCMM"
|
Keyboard_Type SETS "PC"
]
GBLL MorrisSupport
MorrisSupport SETL {TRUE}
GBLL StorkPowerSave
StorkPowerSave SETL {TRUE}
GBLL HiResTTX
HiResTTX SETL M_Lazarus :LOR: M_STB400 :LOR: M_STB5 :LOR: M_Tungsten
GBLL TTX256
TTX256 SETL M_Tungsten :LOR: M_STB5
; Do we support 26-bit only processors? (ARM2, ARM3)
; If true, we mustn't rely on MSR, MRS etc, and we should be
; RISC OS 3.1 compatible.
GBLL No32bitCode
No32bitCode SETL M_Morris :LOR: M_Phoebe :LOR: M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400
; Do we support 32-bit only processors? (ARM9, ARM10...)
GBLL No26bitCode
No26bitCode SETL M_32 :LOR: M_Lazarus :LOR: M_Tungsten :LOR: M_STB5
; Are we using a HAL?
GBLL HAL
HAL SETL M_32 :LOR: M_Tungsten :LOR: M_STB5
; HAL32 indicates the new 32-bit memory map in use.
GBLL HAL26
GBLL HAL32
HAL32 SETL HAL :LAND: No26bitCode
HAL26 SETL HAL :LAND: :LNOT: No26bitCode
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; System build options added for STB/NCD
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; General flag for STB/NCD-type products
GBLL STB
STB SETL M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400 :LOR: M_Lazarus
; Support for battery manager hardware
GBLL BatManSupport
BatManSupport SETL {FALSE} :LAND: StorkPowerSave
; Podule type of hardware in podule 0 address space
; number taken from Hdr:PoduleReg, or 0 if podule0 slot is a real slot.
GBLA FakePodule0
[ M_Falcon
FakePodule0 SETA &10E
|
[ M_Peregrine :LOR: M_STB3
FakePodule0 SETA &121
|
FakePodule0 SETA 0
]
]
; Traditional podule IRQ (8 & 13) behaviour for OS_ClaimDeviceVector
GBLL CDVPoduleIRQs
CDVPoduleIRQs SETL (:LNOT: HAL) :LOR: M_Tungsten
; Support for network 'podule' cards
GBLL NetPodSupport
NetPodSupport SETL :LNOT: (M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400 :LOR: M_Lazarus :LOR: M_Tungsten)
; Number of podules to look at.
GBLA NumberOfPodules
[ M_STB400
NumberOfPodules SETA 1
|
[ M_STB3 :LOR: M_Tungsten
NumberOfPodules SETA 4
|
NumberOfPodules SETA 8
]
]
; Support for extension ROMs in 2nd bank
GBLL ExtROMSupport
ExtROMSupport SETL M_Falcon :LOR: M_Peregrine :LOR: M_STB3 :LOR: ((M_Omega :LOR: M_Lazarus :LOR: M_STB400) :LAND: {FALSE})
; Support for OS images in 2nd ROM bank
GBLL ROMCardSupport
ROMCardSupport SETL M_Omega
; Support for being an OS image in 2nd ROM bank
GBLL CanLiveOnROMCard
CanLiveOnROMCard SETL ROMCardSupport :LAND: {TRUE}
; 2nd ROM bank is 16bit wide
GBLL ExtROMis16bit
ExtROMis16bit SETL M_Falcon :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400
; E2ROM is supported at i2c addresses >= A8 in addition to normal CMOS RAM
GBLL E2ROMSupport
E2ROMSupport SETL M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400 :LOR: M_STB5 :LOR: M_Lazarus :LOR: M_32 :LOR: M_Tungsten
; RTC is supported at IIC &A0 or &D0 (should really be HAL, but defer until
; there's a full HAL RTC API).
GBLL RTCSupport
RTCSupport SETL {TRUE}
; Support for 82C710 and 82C711 combo chips in addition to 665
GBLL OldComboSupport
OldComboSupport SETL {FALSE}
; Whether combo chip should be configured for active high interrupts
GBLL ComboIRQsActiveHigh
ComboIRQsActiveHigh SETL M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB400 :LOR: M_Lazarus
; The combo chip is clocked at 14.318MHz, instead of 24MHz
GBLL ComboClock14MHz
ComboClock14MHz SETL {FALSE}
; Some IOMD interrupts have been reassigned, to cope with the combo chip
; now having active-high interrupts.
; Printer, serial, expansion card 0 move; floppy, IDE, NIC go; gain 2 MPEG interrupts
GBLL ReassignedIOMDInterrupts
ReassignedIOMDInterrupts SETL ComboIRQsActiveHigh :LAND: :LNOT: NetPodSupport :LAND: M_STB400
; Address of NTSC/not PAL flag, if on MPEG podule rather than CLINES, else 0
GBLA MPEGPoduleNTSCNotPALAddress
[ M_Falcon
MPEGPoduleNTSCNotPALAddress SETA &88200000
|
[ M_Peregrine
MPEGPoduleNTSCNotPALAddress SETA &88400000
|
MPEGPoduleNTSCNotPALAddress SETA 0
]
]
; Bit mask for above (0 if not applicable)
GBLA MPEGPoduleNTSCNotPALMask
[ M_Falcon
MPEGPoduleNTSCNotPALMask SETA 1 :SHL: 7
|
[ M_Peregrine
MPEGPoduleNTSCNotPALMask SETA 1 :SHL: 5
|
MPEGPoduleNTSCNotPALMask SETA 0
]
]
; Name of the the header file which defines the MPEG podule
GBLS MPEGPoduleType
[ M_Falcon
MPEGPoduleType SETS "MPEGCard"
|
[ M_Peregrine
MPEGPoduleType SETS "MPEG2Card"
|
[ M_STB3
MPEGPoduleType SETS "MPEG2bCard"
|
[ M_STB400
MPEGPoduleType SETS "MPEG2cCard"
|
MPEGPoduleType SETS "Unknown..." ; Unknown MPEG Podule type
]
]
]
]
; VIDC Clock sources
GBLS VIDCClockSource
[ M_Falcon :LOR: M_Morris :LOR: M_Phoebe :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3
VIDCClockSource SETS "VCO"
|
[ M_STB400
VIDCClockSource SETS "HCLK"
|
[ M_Lazarus
VIDCClockSource SETS "RCLK"
|
VIDCClockSource SETS "VCLK"
]
]
]
; TV modes are produced by Chrontel device
GBLL ChrontelSupport
ChrontelSupport SETL M_32
; ROM speed is normal, not divide by 2
GBLL ROMSpeedNormal
ROMSpeedNormal SETL M_Falcon :LOR: M_Morris :LOR: M_Phoebe
; Safe area when doing TV modes
; Expressed as percentage of screen not to use - left, bottom, right, top
GBLS PALSafeArea
GBLS NTSCSafeArea
[ M_Lazarus
PALSafeArea SETS "6, 6, 6, 6"
|
[ M_STB400
PALSafeArea SETS "8, 6, 8, 6"
|
PALSafeArea SETS "8, 8, 8, 8"
]
]
[ M_Lazarus
NTSCSafeArea SETS "3, 6, 3, 6" ; This is what the original Model 1 had
|
NTSCSafeArea SETS "5, 6, 5, 6"
]
; VCO not fitted, so don't attempt to use VCLK.
GBLL DontUseVCO
DontUseVCO SETL M_Lazarus :LOR: M_STB400
; Only 13.5MHz pixel clock available for TV monitor types
GBLL Only13500kHzTV
Only13500kHzTV SETL M_STB5
; Hardware interlace available from HAL
GBLL HWInterlace
HWInterlace SETL M_STB5
; Number of columns to use for default PAL mode - some systems
; don't use the standard 768.
GBLA PAL_Columns
[ M_Lazarus
PAL_Columns SETA 800
|
[ M_STB5 :LOR: M_STB400 :LOR: M_STB3
PAL_Columns SETA 720
|
PAL_Columns SETA 768
]
]
; Define the number of cycles required to access the ROMs. These only work in 7500/7500FE based systems at the moment.
GBLS ROMSpeedNSTicks
GBLS ROMSpeedBurstTicks
[ M_STB3 :LOR: M_Lazarus
ROMSpeedNSTicks SETS "4"
ROMSpeedBurstTicks SETS "0"
; Ultimately STB400 should be 7+4 (109ns+62ns). For development, 10+8 (156ns+125ns)
|
ROMSpeedNSTicks SETS "5"
ROMSpeedBurstTicks SETS "4"
]
[ M_Phoebe
SystemROMspeed * 156 ;ROM speed in nS
BurstROMspeed * 93 ;ROM burst speed in nS. 0 = no burst mode
]
GBLL FECPUSpeedNormal
FECPUSpeedNormal SETL M_STB3 :LOR: M_STB400 :LOR: M_Lazarus
GBLL FEIOSpeedHalf
FEIOSpeedHalf SETL M_Lazarus
; Modems as found in STB Roadsters, NC (Model 1) and NC
[ M_Falcon :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_Omega :LOR: M_Lazarus
GBLA Modem_DefaultPodule
GBLA Modem_RegisterSetOffset ; offset within EASI
GBLA Modem_InterruptStatusOffset ; offset within EASI
[ M_Falcon :LOR: M_Peregrine :LOR: M_STB3
Modem_DefaultPodule SETA 1 ; default podule is 1 on an STB
|
Modem_DefaultPodule SETA 0 ; have real podules on the rest
]
[ M_Lazarus
Modem_RegisterSetOffset SETA &800000 ; Kerner modem card
Modem_InterruptStatusOffset SETA -1 ; no status...
|
[ M_Falcon :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_Omega
Modem_RegisterSetOffset SETA &803000 ; CME modem card
Modem_InterruptStatusOffset SETA &802000 ; CME modem card
|
Modem_RegisterSetOffset SETA &000be0 ; NC modem
Modem_InterruptStatusOffset SETA &000bfc ; NC modem
]
]
]
; Configurable Standby key
GBLA SpecialKeyStandby
[ M_Lazarus :LOR: M_32
SpecialKeyStandby SETA &D7
|
[ M_STB5 :LOR: M_STB400
SpecialKeyStandby SETA &D1
|
SpecialKeyStandby SETA -1
]
]
; Perform POST on non-power on resets (eg if ROM card selection is inside POST)
GBLL DoPOSTwithoutPowerOn
DoPOSTwithoutPowerOn SETL {FALSE}
; Offset from start of ROM to word containing ROM size.
GBLA ROMSizeOffset
ROMSizeOffset SETA &60
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Allocation of bits in 8bit I/O port at IOMD_CLINES
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Onboard podule 0 MPEG bit, 0 if bit not present
GBLA IOMD_C_MPEGfitted
[ M_Falcon :LOR: M_Morris :LOR: M_Phoebe :LOR: M_Peregrine :LOR: M_STB3
IOMD_C_MPEGfitted SETA (1<<0)
|
IOMD_C_MPEGfitted SETA 0
]
; MonitorTypeLatch, or 0 if latch not present
GBLA IOMD_C_MonitorType
[ M_Omega
IOMD_C_MonitorType SETA (1<<0)
|
IOMD_C_MonitorType SETA 0
]
; Front panel Red LED Write bit, or 0 if bit not present
GBLA IOMD_C_FrontPanelRedLED
[ M_Falcon :LOR: M_Morris :LOR: M_Phoebe :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400
IOMD_C_FrontPanelRedLED SETA (1<<1)
|
IOMD_C_FrontPanelRedLED SETA 0
]
; Video power down for Chrontel, or 0 if bit not present
GBLA IOMD_C_VideoPowerDown
IOMD_C_VideoPowerDown SETA 0
; ROM Card Vpp control, or 0 if bit not present
GBLA IOMD_C_ROMCardVpp
[ M_Omega
IOMD_C_ROMCardVpp SETA (1<<1)
|
IOMD_C_ROMCardVpp SETA 0
]
; EEPROM protection control, or 0 if bit not present
GBLA IOMD_C_EEPROMProtect
[ M_Lazarus
IOMD_C_EEPROMProtect SETA (1<<1)
|
IOMD_C_EEPROMProtect SETA 0
]
; Front panel Green LED Write bit, or 0 if bit not present
GBLA IOMD_C_FrontPanelGrnLED
[ M_Falcon :LOR: M_Morris :LOR: M_Phoebe :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400
IOMD_C_FrontPanelGrnLED SETA (1<<2)
|
IOMD_C_FrontPanelGrnLED SETA 0
]
; TVMode Write bit, or 0 if bit not present
GBLA IOMD_C_TVMode
[ M_Omega
IOMD_C_TVMode SETA (1<<2)
|
IOMD_C_TVMode SETA 0
]
; Right LED bit, or 0 if bit not present
GBLA IOMD_C_FrontPanelRightLED
[ M_Lazarus
IOMD_C_FrontPanelRightLED SETA (1<<3)
|
IOMD_C_FrontPanelRightLED SETA 0
]
; General IO bit
GBLA IOMD_C_GenIO
[ M_Omega
IOMD_C_GenIO SETA (1<<3)
|
IOMD_C_GenIO SETA 0
]
; SCART Control bit 0
GBLA IOMD_C_MPEG_CTRL_0
[ M_STB3 :LOR: M_STB400
IOMD_C_MPEG_CTRL_0 SETA (1<<3)
|
IOMD_C_MPEG_CTRL_0 SETA 0
]
; CD fitted bit. 0=fitted, or 0 if bit not present
GBLA IOMD_C_CDfitted
[ M_Falcon :LOR: M_Morris :LOR: M_Phoebe :LOR: M_Peregrine
IOMD_C_CDfitted SETA (1<<4)
|
IOMD_C_CDfitted SETA 0
]
; PAL/NTSC bit, or 0 if bit not present
GBLA IOMD_C_PALNTSCType
[ M_Omega :LOR: M_STB3 :LOR: M_STB400 :LOR: M_Lazarus
IOMD_C_PALNTSCType SETA (1<<4)
|
IOMD_C_PALNTSCType SETA 0
]
; Joystick type bits in IOMD, or 0 if bits not present
GBLA IOMD_C_JoystickDetectBits
[ M_Falcon :LOR: M_Morris :LOR: M_Phoebe :LOR: M_Peregrine
IOMD_C_JoystickDetectBits SETA (2_11<<5)
|
IOMD_C_JoystickDetectBits SETA 0
]
; Interlace phase bit in IOMD, or 0 if bit not present
GBLA IOMD_C_PhaseDetectBit
[ M_Omega :LOR: M_STB3 :LOR: M_STB400
IOMD_C_PhaseDetectBit SETA (1<<5)
|
IOMD_C_PhaseDetectBit SETA 0
]
; Front panel button (may not actually be on front panel), 0=pressed
GBLA IOMD_C_FrontPanelButton
[ M_Omega :LOR: M_Lazarus
IOMD_C_FrontPanelButton SETA (1<<6)
|
IOMD_C_FrontPanelButton SETA 0
]
; SCART Control bit 1
GBLA IOMD_C_MPEG_CTRL_1
[ M_STB3 :LOR: M_STB400
IOMD_C_MPEG_CTRL_1 SETA (1<<6)
|
IOMD_C_MPEG_CTRL_1 SETA 0
]
; Front panel button function
;selects the front panel buton function
;used to select the maintainance OS or clear CMOS setting
GBLL FrontPanelButtClearsCMOS
FrontPanelButtClearsCMOS SETL {TRUE}
; What is the maximum clock rate (in kHz) for the I2C bus? The
; Kernel will clock the EEPROM at up to this speed (depending
; on the part fitted). The limiting factor will be the slowest
; device on the bus.
GBLA MaxI2Cspeed
;default value
MaxI2Cspeed SETA 100
;different values for faster systems
[ M_Lazarus
MaxI2Cspeed SETA 1000
]
; If nothing relies on CLK16, CLK8, REF8M or CLK2 for anything other
; than timing processor I/O, we can stop them when the processor is
; placed into suspend mode. Any system with a real expansion card slot
; must keep them runnning.
GBLL StopClocksDuringIdle
StopClocksDuringIdle SETL M_Lazarus :LOR: M_STB400
; Front panel Write bit. 1=red, 0=green
GBLA IOMD_C_FrontPanelLED
[ M_Omega
IOMD_C_FrontPanelLED SETA (1<<7)
|
IOMD_C_FrontPanelLED SETA 0
]
; Left LED bit, or 0 if not present
GBLA IOMD_C_FrontPanelLeftLED
[ M_Lazarus
IOMD_C_FrontPanelLeftLED SETA (1<<7)
|
IOMD_C_FrontPanelLeftLED SETA 0
]
; Watchdog Write bit.
GBLA IOMD_C_Watchdog
[ M_Falcon :LOR: M_Morris :LOR: M_Phoebe :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400
IOMD_C_Watchdog SETA (1<<7)
|
IOMD_C_Watchdog SETA 0
]
; Mask of all the readable bits
GBLA IOMD_C_ReadMask
IOMD_C_ReadMask SETA (IOMD_C_MPEGfitted :OR: IOMD_C_MonitorType :OR: IOMD_C_GenIO :OR: IOMD_C_CDfitted :OR: IOMD_C_PALNTSCType :OR: IOMD_C_PhaseDetectBit :OR: IOMD_C_JoystickDetectBits :OR: IOMD_C_FrontPanelButton)
; Do we flash the LEDs in POST? Yes, if we have them, and we're not Lazarus (they're not
; really LEDs).
GBLL POSTFlashesFrontPanelLEDs
POSTFlashesFrontPanelLEDs SETL ((IOMD_C_FrontPanelLED <> 0) :LOR: (IOMD_C_FrontPanelRightLED <> 0 :LAND: IOMD_C_FrontPanelLeftLED <> 0)) :LAND: :LNOT: M_Lazarus
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; MAC Address Read from NVRAM
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; The MAC address can be read from the NVRAM tag MACAddress and
; a SetMac utility is provided in !Boot.Utils to enable the MAC address to be
; programmed for prototypes and development machines.
;
; Since it is dangerous to rely on the NVRAM to hold our MAC address when it is not
; protected in any way, we can store two copies of it, each with their own checksum.
; If either copy becomes damaged we can repair it using the other copy.
; MACNVRAM2COPIES is set to indicate that we are using two copies in the NVRAM.
;
; Paul Skirrow, 22 Feb 2000
GBLL MACNVRAM2copies
MACNVRAM2copies SETL {FALSE}
] ; :LNOT: :DEF: Included_Hdr_Machine_Machine
OPT OldOpt
END
; Copyright 2008 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at