Commit 154397df authored by Ben Avison's avatar Ben Avison
Browse files

First of a two-part update of Hdr:CPU.Generic*

Detail:
  Changes split into two parts to make the diffs readable. In this part:
  * Simplified the inclusion of Hdr:Machine.<Machine> - all current builds
    require a new enough version of objasm that the bug with GET directives
    inside conditionals appears to no longer apply.
  * A number of macros used to have large switches of almost-identical code
    depending upon whether an optional register was defined or not - these
    are now simplified by using a local variable to hold the register.
  * RETURNS is no longer wrapped in :LNOT: No26bitCode, since it could still
    be useful for exception return, non-transient callback handlers etc.
    However, its presence is still a warning sign for non-32-bit-compatible
    code, so it emits a warning unless you add an extra argument to indicate
    that you've vetted that the code is 32-bit safe.
  * Operator precedence bug fixed in SCPSR from Generic32 copied across to
    Generic26 (applies if bits to set/clear were given as expressions).
  * Conflicting set and clear bits in SCPSR now produce an error in both
    Generic26 and Generic32 (previously was only a warning in Generic26).
  * Added the same flag bit check in WritePSRc in Generic26 as already
    existed in Generic32.
  * Some comments reformatted for consistency.
  * Uses of mymrs replaced with MRS, and unconditional or flag-only uses of
    mymsr macro replaced with MSR (other ones remain to deal with the
    StrongARM bug).
  * RETURNVC and RETURNVS no longer accept NV condition code.
  * Removed BKPT macro (now implemented natively in objasm).
Admin:
  Update originally from Rob Sprowson, bugfixed and split into two parts by me.

Version 2.25. Tagged as 'HdrSrc-2_25'
parent 6b8c37eb
/* (2.24) /* (2.25)
* *
* This file is automatically maintained by srccommit, do not edit manually. * This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1. * Last processed by srccommit version: 1.1.
* *
*/ */
#define Module_MajorVersion_CMHG 2.24 #define Module_MajorVersion_CMHG 2.25
#define Module_MinorVersion_CMHG #define Module_MinorVersion_CMHG
#define Module_Date_CMHG 27 Jan 2013 #define Module_Date_CMHG 23 Mar 2013
#define Module_MajorVersion "2.24" #define Module_MajorVersion "2.25"
#define Module_Version 224 #define Module_Version 225
#define Module_MinorVersion "" #define Module_MinorVersion ""
#define Module_Date "27 Jan 2013" #define Module_Date "23 Mar 2013"
#define Module_ApplicationDate "27-Jan-13" #define Module_ApplicationDate "23-Mar-13"
#define Module_ComponentName "HdrSrc" #define Module_ComponentName "HdrSrc"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/HdrSrc" #define Module_ComponentPath "castle/RiscOS/Sources/Programmer/HdrSrc"
#define Module_FullVersion "2.24" #define Module_FullVersion "2.25"
#define Module_HelpVersion "2.24 (27 Jan 2013)" #define Module_HelpVersion "2.25 (23 Mar 2013)"
#define Module_LibraryVersionInfo "2:24" #define Module_LibraryVersionInfo "2:25"
...@@ -14,6 +14,13 @@ ...@@ -14,6 +14,13 @@
; ;
SUBT Generic CPU Specific Definitions SUBT Generic CPU Specific Definitions
OldOpt SETA {OPT}
OPT OptNoList+OptNoP1List
[ :LNOT: :DEF: Included_Hdr_CPU_Generic26
GBLL Included_Hdr_CPU_Generic26
Included_Hdr_CPU_Generic26 SETL {TRUE}
; *********************************** ; ***********************************
; *** C h a n g e L i s t *** ; *** C h a n g e L i s t ***
; *********************************** ; ***********************************
...@@ -24,20 +31,9 @@ ...@@ -24,20 +31,9 @@
; 30-Jun-94 AMcC Restore OPT ; 30-Jun-94 AMcC Restore OPT
; 05-Nov-99 KBracey Keep an eye on No26bitCode flag ; 05-Nov-99 KBracey Keep an eye on No26bitCode flag
GBLS CPU26_GetMachine
[ :LNOT: :DEF: Included_Hdr_Machine_Machine [ :LNOT: :DEF: Included_Hdr_Machine_Machine
CPU26_GetMachine SETS "GET Hdr:Machine.<Machine>" GET Hdr:Machine.<Machine>
|
CPU26_GetMachine SETS ""
] ]
$CPU26_GetMachine
OldOpt SETA {OPT}
OPT OptNoList+OptNoP1List
[ :LNOT: :DEF: Included_Hdr_CPU_Generic26
GBLL Included_Hdr_CPU_Generic26
Included_Hdr_CPU_Generic26 SETL {TRUE}
; Standard register names ; Standard register names
...@@ -247,18 +243,17 @@ $label CMP$cond pc, #0 ...@@ -247,18 +243,17 @@ $label CMP$cond pc, #0
; *** register, default R14. Note that this code preserves the C and V flags. *** ; *** register, default R14. Note that this code preserves the C and V flags. ***
; ********************************************************************************** ; **********************************************************************************
MACRO MACRO
$label PHPSEI $register, $regtmp ; (we don't use regtmp, 32-bit one does) $label PHPSEI $register=R14, $regtmp ; (we don't use regtmp, 32-bit one does)
LCLS usereg
[ "$register" = "" [ "$register" = ""
$label MOV R14, #I_bit usereg SETS "R14"
TST R14, PC ; is I_bit set ?
TEQEQP R14, PC ; no, then set it (and R14 = I_bit)
MOVNE R14, #0 ; yes, then leave alone (and R14=0)
| |
$label MOV $register, #I_bit usereg SETS "$register"
TST $register, PC ; is I_bit set ?
TEQEQP $register, PC ; no, then set it (and $reg. = I_bit)
MOVNE $register, #0 ; yes, then leave alone (and R14=0)
] ]
$label MOV $usereg, #I_bit
TST $usereg, PC ; is I_bit set ?
TEQEQP $usereg, PC ; no, then set it (and $register = I_bit)
MOVNE $usereg, #0 ; yes, then leave alone (and $register = 0)
MEND MEND
; ************************************************************************** ; **************************************************************************
...@@ -267,11 +262,13 @@ $label MOV $register, #I_bit ...@@ -267,11 +262,13 @@ $label MOV $register, #I_bit
; ************************************************************************** ; **************************************************************************
MACRO MACRO
$label PLP $register=R14 $label PLP $register=R14
LCLS usereg
[ "$register" = "" [ "$register" = ""
$label TEQP R14, PC usereg SETS "R14"
| |
$label TEQP $register, PC usereg SETS "$register"
] ]
$label TEQP $usereg, PC
MEND MEND
] ]
...@@ -283,15 +280,16 @@ $label RETURN $cond ...@@ -283,15 +280,16 @@ $label RETURN $cond
$label MOV$cond pc, lr $label MOV$cond pc, lr
MEND MEND
[ :LNOT: No26bitCode
; ***************** ; *****************
; *** RETURNS *** ; *** RETURNS ***
; ***************** ; *****************
MACRO MACRO
$label RETURNS $cond $label RETURNS $cond, $nowarn
[ "$nowarn"=""
! 0, "RETURNS macro indicates possible 32-bit incompatibility", 1
]
$label MOV$cond.S pc, lr $label MOV$cond.S pc, lr
MEND MEND
]
[ No32bitCode [ No32bitCode
; ****************** ; ******************
...@@ -321,7 +319,7 @@ $label MOV$cond $reg, pc ...@@ -321,7 +319,7 @@ $label MOV$cond $reg, pc
; **************************************************** ; ****************************************************
; *** RestPSR - Restore the PSR from a register *** ; *** RestPSR - Restore the PSR from a register ***
; *** set up by SavePSR *** ; *** set up by SavePSR ***
; *** $fields may be set to "f" if the PSR fields *** ; *** $fields may be set to "f" if the PSR fields ***
; *** c,x,s do not need restoring, which will *** ; *** c,x,s do not need restoring, which will ***
; *** save a few cycles on newer ARMs (but the *** ; *** save a few cycles on newer ARMs (but the ***
...@@ -350,8 +348,8 @@ srcreg SETS "$regtmp" ...@@ -350,8 +348,8 @@ srcreg SETS "$regtmp"
| |
srcreg SETS "$oldpsr" srcreg SETS "$oldpsr"
] ]
[ ($set :AND: $clr) <> 0 [ (($set) :AND: ($clr)) <> 0
! 0, "Attempt to simultaneously set and clear a bit in SCPSR" ! 1, "Attempt to simultaneously set and clear a bit in SCPSR"
] ]
$label MOV$cond $srcreg, pc $label MOV$cond $srcreg, pc
ORR$cond $regtmp, $srcreg, #($set) :OR: ($clr) ORR$cond $regtmp, $srcreg, #($set) :OR: ($clr)
...@@ -432,18 +430,25 @@ $label TEQ$cond.P $regtog, pc ...@@ -432,18 +430,25 @@ $label TEQ$cond.P $regtog, pc
; ************************************************* ; *************************************************
MACRO MACRO
$label WritePSRc $value, $regtmp, $cond, $oldpsr $label WritePSRc $value, $regtmp, $cond, $oldpsr
[ ($value :AND::NOT: (I_bit+F_bit+SVC_mode)) <> 0
! 1, "Illegal flags for WritePSRc"
]
[ "$oldpsr" <> "" [ "$oldpsr" <> ""
SavePSR $oldpsr, $cond SavePSR $oldpsr, $cond
] ]
$label TEQ$cond.P PC, #$value $label TEQ$cond.P PC, #$value
MEND MEND
]
] ; No32bitCode
; *************************************************
; *** RemovePSRFromReg - remove PSR bits from ***
; *** a PC (or register holding a PC, eg. lr) ***
; *** Preserves all PSR bits ***
; *************************************************
MACRO MACRO
$label RemovePSRFromReg $pcr, $tmp, $dest $label RemovePSRFromReg $pcr, $tmp, $dest
; This macro masks out the PSR bits from a pc (or register holding a pc - ; If $dest is supplied, it denotes an alternative target
; eg. lr). It does so only in 26-bit modes, and is required to not affect
; any PSR flags. If $dest is supplied, it denotes an alternative target
; register from $pcr. $dest and $tmp may be the same register. ; register from $pcr. $dest and $tmp may be the same register.
; ;
; MRS is safe as it is a NOP if the processor doesn't understand it. The code ; MRS is safe as it is a NOP if the processor doesn't understand it. The code
...@@ -466,7 +471,7 @@ dst SETS "$dest" ...@@ -466,7 +471,7 @@ dst SETS "$dest"
dst SETS "$pcr" dst SETS "$pcr"
] ]
[ No32bitCode [ No32bitCode
BIC $dst, $pcr, #&FC000003 ; 32-bit OK: inside No32bitCode macro BIC $dst, $pcr, #ARM_CC_Mask ; 32-bit OK: inside No32bitCode macro
| |
MRS $tmp, CPSR MRS $tmp, CPSR
MVN $tmp, $tmp, LSR #4 ; bit 0 set in *26, clear in *32 MVN $tmp, $tmp, LSR #4 ; bit 0 set in *26, clear in *32
......
...@@ -118,7 +118,7 @@ $psr32 SETA (($psr) :AND: :NOT: (I_bit:OR:F_bit)) :OR: ((($psr) :AND: (I_bit ...@@ -118,7 +118,7 @@ $psr32 SETA (($psr) :AND: :NOT: (I_bit:OR:F_bit)) :OR: ((($psr) :AND: (I_bit
; ************************************************ ; ************************************************
MACRO MACRO
$label CLC $cond $label CLC $cond
$label mymsr $cond, CPSR_f, #0 $label MSR$cond CPSR_f, #0
MEND MEND
; *********************************************** ; ***********************************************
...@@ -133,9 +133,10 @@ srcreg SETS "$regtmp" ...@@ -133,9 +133,10 @@ srcreg SETS "$regtmp"
| |
srcreg SETS "$oldpsr" srcreg SETS "$oldpsr"
] ]
$label mymrs $cond, $srcreg, CPSR CPU32_bits PSRto32 $bits ; Map to 32 bit PSR
CPU32_bits PSRto32 $bits $label MRS$cond $srcreg, CPSR
[ (CPU32_bits :AND: &F0000000) <> 0 :LAND: (CPU32_bits :AND: &F0) <> 0 [ (CPU32_bits :AND: &F0000000) <> 0 :LAND: (CPU32_bits :AND: &F0) <> 0
; Can't be expressed as a single ARM immediate constant
BIC$cond $regtmp, $srcreg, #CPU32_bits :AND: &F0000000 BIC$cond $regtmp, $srcreg, #CPU32_bits :AND: &F0000000
BIC$cond $regtmp, $regtmp, #CPU32_bits :AND: &0FFFFFFF BIC$cond $regtmp, $regtmp, #CPU32_bits :AND: &0FFFFFFF
| |
...@@ -149,7 +150,7 @@ CPU32_bits PSRto32 $bits ...@@ -149,7 +150,7 @@ CPU32_bits PSRto32 $bits
; ************************************************** ; **************************************************
MACRO MACRO
$label CLRV $cond $label CLRV $cond
$label mymsr $cond, CPSR_f, #C_bit $label MSR$cond CPSR_f, #C_bit
MEND MEND
; ********************************************************************************** ; **********************************************************************************
...@@ -159,32 +160,24 @@ $label mymsr $cond, CPSR_f, #C_bit ...@@ -159,32 +160,24 @@ $label mymsr $cond, CPSR_f, #C_bit
; ********************************************************************************** ; **********************************************************************************
MACRO MACRO
$label PHPSEI $register=R14, $regtmp $label PHPSEI $register=R14, $regtmp
LCLS usereg
[ "$register" = "" [ "$register" = ""
[ "$regtmp" = "" :LOR: StrongARM_MSR_bug usereg SETS "R14"
$label mymrs AL, R14, CPSR
TST R14, #I32_bit ; is I32_bit set?
ORREQ R14, R14, #I32_bit ; no, then set it
mymsr EQ, CPSR_c, R14, , safe
BICEQ R14, R14, #I32_bit ; $reg contains original PSR
| |
$label mymrs AL, R14, CPSR usereg SETS "$register"
TST R14, #I32_bit ; is I32_bit set?
ORREQ $regtmp, R14, #I32_bit ; no, then set it
mymsr EQ, CPSR_c, $regtmp ; $reg contains original PSR
] ]
| $label
[ "$regtmp" = "" :LOR: StrongARM_MSR_bug [ "$regtmp" = "" :LOR: StrongARM_MSR_bug
$label mymrs AL, $register, CPSR MRS $usereg, CPSR
TST $register, #I32_bit ; is I32_bit set? TST $usereg, #I32_bit ; is I32_bit set?
ORREQ $register, $register, #I32_bit ; no, then set it ORREQ $usereg, $usereg, #I32_bit ; no, then set it
mymsr EQ, CPSR_c, $register, , safe mymsr EQ, CPSR_c, $usereg, , safe
BICEQ $register, $register, #I32_bit ; $reg contains original PSR BICEQ $usereg, $usereg, #I32_bit ; $register contains original PSR
| |
$label mymrs AL, $register, CPSR MRS $usereg, CPSR
TST $register, #I32_bit ; is I32_bit set? TST $usereg, #I32_bit ; is I32_bit set?
ORREQ $regtmp, $register, #I32_bit ; no, then set it ORREQ $regtmp, $usereg, #I32_bit ; no, then set it
mymsr EQ, CPSR_c, $regtmp ; $reg contains original PSR mymsr EQ, CPSR_c, $regtmp ; $register contains original PSR
]
] ]
MEND MEND
...@@ -194,11 +187,13 @@ $label mymrs AL, $register, CPSR ...@@ -194,11 +187,13 @@ $label mymrs AL, $register, CPSR
; ************************************************************************** ; **************************************************************************
MACRO MACRO
$label PLP $register=R14 $label PLP $register=R14
LCLS usereg
[ "$register" = "" [ "$register" = ""
$label mymsr AL, CPSR_c, R14 usereg SETS "R14"
| |
$label mymsr AL, CPSR_c, $register usereg SETS "$register"
] ]
$label MSR CPSR_c, $usereg
MEND MEND
; ****************** ; ******************
...@@ -207,27 +202,29 @@ $label mymsr AL, CPSR_c, $register ...@@ -207,27 +202,29 @@ $label mymsr AL, CPSR_c, $register
MACRO MACRO
$label RETURNVC $cond $label RETURNVC $cond
$label $label
01 [ "$cond" = "NV"
! 1, "Deprecated use of NV condition code in RETURNVC"
]
[ "$cond" = "VC" [ "$cond" = "VC"
MOVVC pc, lr MOVVC pc, lr
] ]
[ "$cond" = "NE" :LOR: "$cond"="CC" :LOR: "$cond"="LO" :LOR: "$cond"="PL" :LOR: "$cond"="LS" :LOR: "$cond"="GE" :LOR: "$cond"="GT" :LOR: "$cond"="AL" :LOR: "$cond"="" :LOR: "$cond"="NV" [ "$cond" = "NE" :LOR: "$cond"="CC" :LOR: "$cond"="LO" :LOR: "$cond"="PL" :LOR: "$cond"="LS" :LOR: "$cond"="GE" :LOR: "$cond"="GT" :LOR: "$cond"="AL" :LOR: "$cond"=""
mymsr $cond, CPSR_f, #0 MSR$cond CPSR_f, #0
MOV$cond pc, lr MOV$cond pc, lr
] ]
[ "$cond" = "EQ" :LOR: "$cond"="CS" :LOR: "$cond"="HS" :LOR: "$cond"="MI" :LOR: "$cond"="LT" :LOR: "$cond"="LE" [ "$cond" = "EQ" :LOR: "$cond"="CS" :LOR: "$cond"="HS" :LOR: "$cond"="MI" :LOR: "$cond"="LT" :LOR: "$cond"="LE"
mymsr $cond, CPSR_f, #N_bit + Z_bit + C_bit MSR$cond CPSR_f, #N_bit + Z_bit + C_bit
MOV$cond pc, lr MOV$cond pc, lr
] ]
[ "$cond" = "HI" [ "$cond" = "HI"
mymsr $cond, CPSR_f, #C_bit MSR$cond CPSR_f, #C_bit
MOV$cond pc, lr MOV$cond pc, lr
] ]
[ . - %BT01 = 0 [ "$cond" = "VS"
; branch over on opposite condition BVC %FT01 ; Skip on opposite condition
DCI &1A000001 :EOR: Cond_$cond MSR CPSR_f, #0
mymsr ,CPSR_f, #0
MOV pc, lr MOV pc, lr
01
] ]
MEND MEND
...@@ -237,31 +234,33 @@ $label ...@@ -237,31 +234,33 @@ $label
MACRO MACRO
$label RETURNVS $cond $label RETURNVS $cond
$label $label
01 [ "$cond" = "NV"
! 1, "Deprecated use of NV condition code in RETURNVC"
]
[ "$cond" = "VS" [ "$cond" = "VS"
MOVVS pc, lr MOVVS pc, lr
] ]
[ "$cond" = "NE" :LOR: "$cond"="CC" :LOR: "$cond"="LO" :LOR: "$cond"="PL" :LOR: "$cond"="LS" :LOR: "$cond"="AL" :LOR: "$cond"="" :LOR: "$cond"="NV" [ "$cond" = "NE" :LOR: "$cond"="CC" :LOR: "$cond"="LO" :LOR: "$cond"="PL" :LOR: "$cond"="LS" :LOR: "$cond"="AL" :LOR: "$cond"=""
mymsr $cond, CPSR_f, #V_bit MSR$cond CPSR_f, #V_bit ; Condition is still satisfied
MOV$cond pc, lr MOV$cond pc, lr
] ]
[ "$cond" = "EQ" :LOR: "$cond"="CS" :LOR: "$cond"="HS" :LOR: "$cond"="MI" :LOR: "$cond"="GE" :LOR: "$cond"="LE" [ "$cond" = "EQ" :LOR: "$cond"="CS" :LOR: "$cond"="HS" :LOR: "$cond"="MI" :LOR: "$cond"="GE" :LOR: "$cond"="LE"
mymsr $cond, CPSR_f, #N_bit + Z_bit + C_bit + V_bit MSR$cond CPSR_f, #N_bit + Z_bit + C_bit + V_bit
MOV$cond pc, lr MOV$cond pc, lr
] ]
[ "$cond" = "HI" :LOR: "$cond"="LT" [ "$cond" = "HI" :LOR: "$cond"="LT"
mymsr $cond, CPSR_f, #C_bit + V_bit MSR$cond CPSR_f, #C_bit + V_bit
MOV$cond pc, lr MOV$cond pc, lr
] ]
[ "$cond" = "GT" [ "$cond" = "GT"
mymsr $cond, CPSR_f, #N_bit + V_bit MSR$cond CPSR_f, #N_bit + V_bit
MOV$cond pc, lr MOV$cond pc, lr
] ]
[ . - %BT01 = 0 [ "$cond" = "VC"
; branch over on opposite condition BVS %FT01 ; Skip on opposite condition
DCD &1A000001 :EOR: Cond_$cond MSR CPSR_f, #V_bit
mymsr ,CPSR_f, #V_bit
MOV pc, lr MOV pc, lr
01
] ]
MEND MEND
...@@ -272,17 +271,17 @@ $label ...@@ -272,17 +271,17 @@ $label
MACRO MACRO
$label SCPSR $set, $clr, $regtmp, $cond, $oldpsr $label SCPSR $set, $clr, $regtmp, $cond, $oldpsr
LCLS srcreg LCLS srcreg
CPU32_set PSRto32 $set
CPU32_clr PSRto32 $clr
[ "$oldpsr"="" [ "$oldpsr"=""
srcreg SETS "$regtmp" srcreg SETS "$regtmp"
| |
srcreg SETS "$oldpsr" srcreg SETS "$oldpsr"
] ]
$label mymrs $cond, $srcreg, CPSR
[ (($set) :AND: ($clr)) <> 0 [ (($set) :AND: ($clr)) <> 0
! 1, "Attempt to simultaneously set and clear a bit in SCPSR" ! 1, "Attempt to simultaneously set and clear a bit in SCPSR"
] ]
CPU32_set PSRto32 $set $label MRS$cond $srcreg, CPSR
CPU32_clr PSRto32 $clr
[ (CPU32_set :AND: &F0000000) <> 0 :LAND: (CPU32_set :AND: &F0) <> 0 [ (CPU32_set :AND: &F0000000) <> 0 :LAND: (CPU32_set :AND: &F0) <> 0
ORR$cond $regtmp, $srcreg, #CPU32_set :AND: &F0000000 ORR$cond $regtmp, $srcreg, #CPU32_set :AND: &F0000000
ORR$cond $regtmp, $regtmp, #CPU32_set :AND: &0FFFFFFF ORR$cond $regtmp, $regtmp, #CPU32_set :AND: &0FFFFFFF
...@@ -312,12 +311,12 @@ srcreg SETS "$regtmp" ...@@ -312,12 +311,12 @@ srcreg SETS "$regtmp"
; **************************************************** ; ****************************************************
MACRO MACRO
$label SavePSR $reg, $cond $label SavePSR $reg, $cond
$label mymrs $cond, $reg, CPSR $label MRS$cond $reg, CPSR
MEND MEND
; **************************************************** ; ****************************************************
; *** RestPSR - Restore the PSR from a register *** ; *** RestPSR - Restore the PSR from a register ***
; *** set up by SavePSR *** ; *** set up by SavePSR ***
; *** $fields may be set to "f" if the PSR fields *** ; *** $fields may be set to "f" if the PSR fields ***
; *** c,x,s do not need restoring, which will *** ; *** c,x,s do not need restoring, which will ***
; *** save a few cycles on newer ARMs (but the *** ; *** save a few cycles on newer ARMs (but the ***
...@@ -347,7 +346,7 @@ $label mymsr $cond, CPSR_$field, $reg, , unsafe ...@@ -347,7 +346,7 @@ $label mymsr $cond, CPSR_$field, $reg, , unsafe
; ********************************************** ; **********************************************
MACRO MACRO
$label SEC $cond $label SEC $cond
$label mymsr $cond, CPSR_f, #C_bit $label MSR$cond CPSR_f, #C_bit
MEND MEND
; ************************************************ ; ************************************************
...@@ -362,9 +361,10 @@ srcreg SETS "$regtmp" ...@@ -362,9 +361,10 @@ srcreg SETS "$regtmp"
| |
srcreg SETS "$oldpsr" srcreg SETS "$oldpsr"
] ]
$label mymrs $cond, $srcreg, CPSR CPU32_bits PSRto32 $bits ; Map to 32 bit PSR
CPU32_bits PSRto32 $bits $label MRS$cond $srcreg, CPSR
[ (CPU32_bits :AND: &F0000000) <> 0 :LAND: (CPU32_bits :AND: &F0) <> 0 [ (CPU32_bits :AND: &F0000000) <> 0 :LAND: (CPU32_bits :AND: &F0) <> 0
; Can't be expressed as a single ARM immediate constant
ORR$cond $regtmp, $srcreg, #CPU32_bits :AND: &F0000000 ORR$cond $regtmp, $srcreg, #CPU32_bits :AND: &F0000000
ORR$cond $regtmp, $regtmp, #CPU32_bits :AND: &0FFFFFFF ORR$cond $regtmp, $regtmp, #CPU32_bits :AND: &0FFFFFFF
| |
...@@ -378,13 +378,13 @@ CPU32_bits PSRto32 $bits ...@@ -378,13 +378,13 @@ CPU32_bits PSRto32 $bits
; ************************************************** ; **************************************************
MACRO MACRO
$label SETV $cond $label SETV $cond
$label mymsr $cond, CPSR_f, #N_bit+V_bit $label MSR$cond CPSR_f, #N_bit+V_bit
MEND MEND
; *********************************************** ; *********************************************************
; *** TOGPSR - Toggle bits in PSR from the *** ; *** TOGPSR - Toggle bits in PSR from the ***
; *** mask in $bits, using register $regtmp *** ; *** immediate mask in $bits, using register $regtmp ***
; *********************************************** ; *********************************************************
MACRO MACRO
$label TOGPSR $bits, $regtmp, $cond, $oldpsr $label TOGPSR $bits, $regtmp, $cond, $oldpsr
LCLS srcreg LCLS srcreg
...@@ -393,16 +393,16 @@ srcreg SETS "$regtmp" ...@@ -393,16 +393,16 @@ srcreg SETS "$regtmp"
| |
srcreg SETS "$oldpsr" srcreg SETS "$oldpsr"
] ]
$label mymrs $cond, $srcreg, CPSR CPU32_bits PSRto32 $bits ; Map to 32 bit PSR
CPU32_bits PSRto32 $bits $label MRS$cond $srcreg, CPSR
EOR$cond $regtmp, $srcreg, #CPU32_bits EOR$cond $regtmp, $srcreg, #CPU32_bits
somemsr $cond, CPSR, $regtmp, CPU32_bits, unsafe somemsr $cond, CPSR, $regtmp, CPU32_bits, unsafe
MEND MEND
; *********************************************** ; ************************************************
; *** TOGPSRR - Toggle bits in PSR from the *** ; *** TOGPSRR - Toggle bits in PSR from the ***
; *** mask in $regtog, using reg $regtmp *** ; *** mask in $regtog, using register $regtmp ***
; *********************************************** ; ************************************************
MACRO MACRO
$label TOGPSRR $regtog, $regtmp, $cond, $oldpsr, $fields $label TOGPSRR $regtog, $regtmp, $cond, $oldpsr, $fields
LCLS srcreg LCLS srcreg
...@@ -417,7 +417,7 @@ srcreg SETS "$regtmp" ...@@ -417,7 +417,7 @@ srcreg SETS "$regtmp"
| |