Commit 154397df authored by Ben Avison's avatar Ben Avison
Browse files

First of a two-part update of Hdr:CPU.Generic*

Detail:
  Changes split into two parts to make the diffs readable. In this part:
  * Simplified the inclusion of Hdr:Machine.<Machine> - all current builds
    require a new enough version of objasm that the bug with GET directives
    inside conditionals appears to no longer apply.
  * A number of macros used to have large switches of almost-identical code
    depending upon whether an optional register was defined or not - these
    are now simplified by using a local variable to hold the register.
  * RETURNS is no longer wrapped in :LNOT: No26bitCode, since it could still
    be useful for exception return, non-transient callback handlers etc.
    However, its presence is still a warning sign for non-32-bit-compatible
    code, so it emits a warning unless you add an extra argument to indicate
    that you've vetted that the code is 32-bit safe.
  * Operator precedence bug fixed in SCPSR from Generic32 copied across to
    Generic26 (applies if bits to set/clear were given as expressions).
  * Conflicting set and clear bits in SCPSR now produce an error in both
    Generic26 and Generic32 (previously was only a warning in Generic26).
  * Added the same flag bit check in WritePSRc in Generic26 as already
    existed in Generic32.
  * Some comments reformatted for consistency.
  * Uses of mymrs replaced with MRS, and unconditional or flag-only uses of
    mymsr macro replaced with MSR (other ones remain to deal with the
    StrongARM bug).
  * RETURNVC and RETURNVS no longer accept NV condition code.
  * Removed BKPT macro (now implemented natively in objasm).
Admin:
  Update originally from Rob Sprowson, bugfixed and split into two parts by me.

Version 2.25. Tagged as 'HdrSrc-2_25'
parent 6b8c37eb
/* (2.24)
/* (2.25)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 2.24
#define Module_MajorVersion_CMHG 2.25
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 27 Jan 2013
#define Module_Date_CMHG 23 Mar 2013
#define Module_MajorVersion "2.24"
#define Module_Version 224
#define Module_MajorVersion "2.25"
#define Module_Version 225
#define Module_MinorVersion ""
#define Module_Date "27 Jan 2013"
#define Module_Date "23 Mar 2013"
#define Module_ApplicationDate "27-Jan-13"
#define Module_ApplicationDate "23-Mar-13"
#define Module_ComponentName "HdrSrc"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/HdrSrc"
#define Module_FullVersion "2.24"
#define Module_HelpVersion "2.24 (27 Jan 2013)"
#define Module_LibraryVersionInfo "2:24"
#define Module_FullVersion "2.25"
#define Module_HelpVersion "2.25 (23 Mar 2013)"
#define Module_LibraryVersionInfo "2:25"
......@@ -14,6 +14,13 @@
;
SUBT Generic CPU Specific Definitions
OldOpt SETA {OPT}
OPT OptNoList+OptNoP1List
[ :LNOT: :DEF: Included_Hdr_CPU_Generic26
GBLL Included_Hdr_CPU_Generic26
Included_Hdr_CPU_Generic26 SETL {TRUE}
; ***********************************
; *** C h a n g e L i s t ***
; ***********************************
......@@ -24,20 +31,9 @@
; 30-Jun-94 AMcC Restore OPT
; 05-Nov-99 KBracey Keep an eye on No26bitCode flag
GBLS CPU26_GetMachine
[ :LNOT: :DEF: Included_Hdr_Machine_Machine
CPU26_GetMachine SETS "GET Hdr:Machine.<Machine>"
|
CPU26_GetMachine SETS ""
GET Hdr:Machine.<Machine>
]
$CPU26_GetMachine
OldOpt SETA {OPT}
OPT OptNoList+OptNoP1List
[ :LNOT: :DEF: Included_Hdr_CPU_Generic26
GBLL Included_Hdr_CPU_Generic26
Included_Hdr_CPU_Generic26 SETL {TRUE}
; Standard register names
......@@ -247,18 +243,17 @@ $label CMP$cond pc, #0
; *** register, default R14. Note that this code preserves the C and V flags. ***
; **********************************************************************************
MACRO
$label PHPSEI $register, $regtmp ; (we don't use regtmp, 32-bit one does)
$label PHPSEI $register=R14, $regtmp ; (we don't use regtmp, 32-bit one does)
LCLS usereg
[ "$register" = ""
$label MOV R14, #I_bit
TST R14, PC ; is I_bit set ?
TEQEQP R14, PC ; no, then set it (and R14 = I_bit)
MOVNE R14, #0 ; yes, then leave alone (and R14=0)
usereg SETS "R14"
|
$label MOV $register, #I_bit
TST $register, PC ; is I_bit set ?
TEQEQP $register, PC ; no, then set it (and $reg. = I_bit)
MOVNE $register, #0 ; yes, then leave alone (and R14=0)
usereg SETS "$register"
]
$label MOV $usereg, #I_bit
TST $usereg, PC ; is I_bit set ?
TEQEQP $usereg, PC ; no, then set it (and $register = I_bit)
MOVNE $usereg, #0 ; yes, then leave alone (and $register = 0)
MEND
; **************************************************************************
......@@ -267,11 +262,13 @@ $label MOV $register, #I_bit
; **************************************************************************
MACRO
$label PLP $register=R14
LCLS usereg
[ "$register" = ""
$label TEQP R14, PC
usereg SETS "R14"
|
$label TEQP $register, PC
usereg SETS "$register"
]
$label TEQP $usereg, PC
MEND
]
......@@ -283,15 +280,16 @@ $label RETURN $cond
$label MOV$cond pc, lr
MEND
[ :LNOT: No26bitCode
; *****************
; *** RETURNS ***
; *****************
MACRO
$label RETURNS $cond
$label RETURNS $cond, $nowarn
[ "$nowarn"=""
! 0, "RETURNS macro indicates possible 32-bit incompatibility", 1
]
$label MOV$cond.S pc, lr
MEND
]
[ No32bitCode
; ******************
......@@ -321,7 +319,7 @@ $label MOV$cond $reg, pc
; ****************************************************
; *** RestPSR - Restore the PSR from a register ***
; *** set up by SavePSR ***
; *** set up by SavePSR ***
; *** $fields may be set to "f" if the PSR fields ***
; *** c,x,s do not need restoring, which will ***
; *** save a few cycles on newer ARMs (but the ***
......@@ -350,8 +348,8 @@ srcreg SETS "$regtmp"
|
srcreg SETS "$oldpsr"
]
[ ($set :AND: $clr) <> 0
! 0, "Attempt to simultaneously set and clear a bit in SCPSR"
[ (($set) :AND: ($clr)) <> 0
! 1, "Attempt to simultaneously set and clear a bit in SCPSR"
]
$label MOV$cond $srcreg, pc
ORR$cond $regtmp, $srcreg, #($set) :OR: ($clr)
......@@ -432,18 +430,25 @@ $label TEQ$cond.P $regtog, pc
; *************************************************
MACRO
$label WritePSRc $value, $regtmp, $cond, $oldpsr
[ ($value :AND::NOT: (I_bit+F_bit+SVC_mode)) <> 0
! 1, "Illegal flags for WritePSRc"
]
[ "$oldpsr" <> ""
SavePSR $oldpsr, $cond
]
$label TEQ$cond.P PC, #$value
MEND
]
] ; No32bitCode
; *************************************************
; *** RemovePSRFromReg - remove PSR bits from ***
; *** a PC (or register holding a PC, eg. lr) ***
; *** Preserves all PSR bits ***
; *************************************************
MACRO
$label RemovePSRFromReg $pcr, $tmp, $dest
; This macro masks out the PSR bits from a pc (or register holding a pc -
; eg. lr). It does so only in 26-bit modes, and is required to not affect
; any PSR flags. If $dest is supplied, it denotes an alternative target
; If $dest is supplied, it denotes an alternative target
; register from $pcr. $dest and $tmp may be the same register.
;
; MRS is safe as it is a NOP if the processor doesn't understand it. The code
......@@ -466,7 +471,7 @@ dst SETS "$dest"
dst SETS "$pcr"
]
[ No32bitCode
BIC $dst, $pcr, #&FC000003 ; 32-bit OK: inside No32bitCode macro
BIC $dst, $pcr, #ARM_CC_Mask ; 32-bit OK: inside No32bitCode macro
|
MRS $tmp, CPSR
MVN $tmp, $tmp, LSR #4 ; bit 0 set in *26, clear in *32
......
......@@ -118,7 +118,7 @@ $psr32 SETA (($psr) :AND: :NOT: (I_bit:OR:F_bit)) :OR: ((($psr) :AND: (I_bit
; ************************************************
MACRO
$label CLC $cond
$label mymsr $cond, CPSR_f, #0
$label MSR$cond CPSR_f, #0
MEND
; ***********************************************
......@@ -133,9 +133,10 @@ srcreg SETS "$regtmp"
|
srcreg SETS "$oldpsr"
]
$label mymrs $cond, $srcreg, CPSR
CPU32_bits PSRto32 $bits
CPU32_bits PSRto32 $bits ; Map to 32 bit PSR
$label MRS$cond $srcreg, CPSR
[ (CPU32_bits :AND: &F0000000) <> 0 :LAND: (CPU32_bits :AND: &F0) <> 0
; Can't be expressed as a single ARM immediate constant
BIC$cond $regtmp, $srcreg, #CPU32_bits :AND: &F0000000
BIC$cond $regtmp, $regtmp, #CPU32_bits :AND: &0FFFFFFF
|
......@@ -149,7 +150,7 @@ CPU32_bits PSRto32 $bits
; **************************************************
MACRO
$label CLRV $cond
$label mymsr $cond, CPSR_f, #C_bit
$label MSR$cond CPSR_f, #C_bit
MEND
; **********************************************************************************
......@@ -159,32 +160,24 @@ $label mymsr $cond, CPSR_f, #C_bit
; **********************************************************************************
MACRO
$label PHPSEI $register=R14, $regtmp
LCLS usereg
[ "$register" = ""
[ "$regtmp" = "" :LOR: StrongARM_MSR_bug
$label mymrs AL, R14, CPSR
TST R14, #I32_bit ; is I32_bit set?
ORREQ R14, R14, #I32_bit ; no, then set it
mymsr EQ, CPSR_c, R14, , safe
BICEQ R14, R14, #I32_bit ; $reg contains original PSR
usereg SETS "R14"
|
$label mymrs AL, R14, CPSR
TST R14, #I32_bit ; is I32_bit set?
ORREQ $regtmp, R14, #I32_bit ; no, then set it
mymsr EQ, CPSR_c, $regtmp ; $reg contains original PSR
usereg SETS "$register"
]
$label
[ "$regtmp" = "" :LOR: StrongARM_MSR_bug
MRS $usereg, CPSR
TST $usereg, #I32_bit ; is I32_bit set?
ORREQ $usereg, $usereg, #I32_bit ; no, then set it
mymsr EQ, CPSR_c, $usereg, , safe
BICEQ $usereg, $usereg, #I32_bit ; $register contains original PSR
|
[ "$regtmp" = "" :LOR: StrongARM_MSR_bug
$label mymrs AL, $register, CPSR
TST $register, #I32_bit ; is I32_bit set?
ORREQ $register, $register, #I32_bit ; no, then set it
mymsr EQ, CPSR_c, $register, , safe
BICEQ $register, $register, #I32_bit ; $reg contains original PSR
|
$label mymrs AL, $register, CPSR
TST $register, #I32_bit ; is I32_bit set?
ORREQ $regtmp, $register, #I32_bit ; no, then set it
mymsr EQ, CPSR_c, $regtmp ; $reg contains original PSR
]
MRS $usereg, CPSR
TST $usereg, #I32_bit ; is I32_bit set?
ORREQ $regtmp, $usereg, #I32_bit ; no, then set it
mymsr EQ, CPSR_c, $regtmp ; $register contains original PSR
]
MEND
......@@ -194,11 +187,13 @@ $label mymrs AL, $register, CPSR
; **************************************************************************
MACRO
$label PLP $register=R14
LCLS usereg
[ "$register" = ""
$label mymsr AL, CPSR_c, R14
usereg SETS "R14"
|
$label mymsr AL, CPSR_c, $register
usereg SETS "$register"
]
$label MSR CPSR_c, $usereg
MEND
; ******************
......@@ -207,27 +202,29 @@ $label mymsr AL, CPSR_c, $register
MACRO
$label RETURNVC $cond
$label
01
[ "$cond" = "NV"
! 1, "Deprecated use of NV condition code in RETURNVC"
]
[ "$cond" = "VC"
MOVVC pc, lr
]
[ "$cond" = "NE" :LOR: "$cond"="CC" :LOR: "$cond"="LO" :LOR: "$cond"="PL" :LOR: "$cond"="LS" :LOR: "$cond"="GE" :LOR: "$cond"="GT" :LOR: "$cond"="AL" :LOR: "$cond"="" :LOR: "$cond"="NV"
mymsr $cond, CPSR_f, #0
[ "$cond" = "NE" :LOR: "$cond"="CC" :LOR: "$cond"="LO" :LOR: "$cond"="PL" :LOR: "$cond"="LS" :LOR: "$cond"="GE" :LOR: "$cond"="GT" :LOR: "$cond"="AL" :LOR: "$cond"=""
MSR$cond CPSR_f, #0
MOV$cond pc, lr
]
[ "$cond" = "EQ" :LOR: "$cond"="CS" :LOR: "$cond"="HS" :LOR: "$cond"="MI" :LOR: "$cond"="LT" :LOR: "$cond"="LE"
mymsr $cond, CPSR_f, #N_bit + Z_bit + C_bit
MSR$cond CPSR_f, #N_bit + Z_bit + C_bit
MOV$cond pc, lr
]
[ "$cond" = "HI"
mymsr $cond, CPSR_f, #C_bit
MSR$cond CPSR_f, #C_bit
MOV$cond pc, lr
]
[ . - %BT01 = 0
; branch over on opposite condition
DCI &1A000001 :EOR: Cond_$cond
mymsr ,CPSR_f, #0
[ "$cond" = "VS"
BVC %FT01 ; Skip on opposite condition
MSR CPSR_f, #0
MOV pc, lr
01
]
MEND
......@@ -237,31 +234,33 @@ $label
MACRO
$label RETURNVS $cond
$label
01
[ "$cond" = "NV"
! 1, "Deprecated use of NV condition code in RETURNVC"
]
[ "$cond" = "VS"
MOVVS pc, lr
]
[ "$cond" = "NE" :LOR: "$cond"="CC" :LOR: "$cond"="LO" :LOR: "$cond"="PL" :LOR: "$cond"="LS" :LOR: "$cond"="AL" :LOR: "$cond"="" :LOR: "$cond"="NV"
mymsr $cond, CPSR_f, #V_bit
[ "$cond" = "NE" :LOR: "$cond"="CC" :LOR: "$cond"="LO" :LOR: "$cond"="PL" :LOR: "$cond"="LS" :LOR: "$cond"="AL" :LOR: "$cond"=""
MSR$cond CPSR_f, #V_bit ; Condition is still satisfied
MOV$cond pc, lr
]
[ "$cond" = "EQ" :LOR: "$cond"="CS" :LOR: "$cond"="HS" :LOR: "$cond"="MI" :LOR: "$cond"="GE" :LOR: "$cond"="LE"
mymsr $cond, CPSR_f, #N_bit + Z_bit + C_bit + V_bit
MSR$cond CPSR_f, #N_bit + Z_bit + C_bit + V_bit
MOV$cond pc, lr
]
[ "$cond" = "HI" :LOR: "$cond"="LT"
mymsr $cond, CPSR_f, #C_bit + V_bit
MSR$cond CPSR_f, #C_bit + V_bit
MOV$cond pc, lr
]
[ "$cond" = "GT"
mymsr $cond, CPSR_f, #N_bit + V_bit
MSR$cond CPSR_f, #N_bit + V_bit
MOV$cond pc, lr
]
[ . - %BT01 = 0
; branch over on opposite condition
DCD &1A000001 :EOR: Cond_$cond
mymsr ,CPSR_f, #V_bit
[ "$cond" = "VC"
BVS %FT01 ; Skip on opposite condition
MSR CPSR_f, #V_bit
MOV pc, lr
01
]
MEND
......@@ -272,17 +271,17 @@ $label
MACRO
$label SCPSR $set, $clr, $regtmp, $cond, $oldpsr
LCLS srcreg
CPU32_set PSRto32 $set
CPU32_clr PSRto32 $clr
[ "$oldpsr"=""
srcreg SETS "$regtmp"
|
srcreg SETS "$oldpsr"
]
$label mymrs $cond, $srcreg, CPSR
[ (($set) :AND: ($clr)) <> 0
! 1, "Attempt to simultaneously set and clear a bit in SCPSR"
]
CPU32_set PSRto32 $set
CPU32_clr PSRto32 $clr
$label MRS$cond $srcreg, CPSR
[ (CPU32_set :AND: &F0000000) <> 0 :LAND: (CPU32_set :AND: &F0) <> 0
ORR$cond $regtmp, $srcreg, #CPU32_set :AND: &F0000000
ORR$cond $regtmp, $regtmp, #CPU32_set :AND: &0FFFFFFF
......@@ -312,12 +311,12 @@ srcreg SETS "$regtmp"
; ****************************************************
MACRO
$label SavePSR $reg, $cond
$label mymrs $cond, $reg, CPSR
$label MRS$cond $reg, CPSR
MEND
; ****************************************************
; *** RestPSR - Restore the PSR from a register ***
; *** set up by SavePSR ***
; *** set up by SavePSR ***
; *** $fields may be set to "f" if the PSR fields ***
; *** c,x,s do not need restoring, which will ***
; *** save a few cycles on newer ARMs (but the ***
......@@ -347,7 +346,7 @@ $label mymsr $cond, CPSR_$field, $reg, , unsafe
; **********************************************
MACRO
$label SEC $cond
$label mymsr $cond, CPSR_f, #C_bit
$label MSR$cond CPSR_f, #C_bit
MEND
; ************************************************
......@@ -362,9 +361,10 @@ srcreg SETS "$regtmp"
|
srcreg SETS "$oldpsr"
]
$label mymrs $cond, $srcreg, CPSR
CPU32_bits PSRto32 $bits
CPU32_bits PSRto32 $bits ; Map to 32 bit PSR
$label MRS$cond $srcreg, CPSR
[ (CPU32_bits :AND: &F0000000) <> 0 :LAND: (CPU32_bits :AND: &F0) <> 0
; Can't be expressed as a single ARM immediate constant
ORR$cond $regtmp, $srcreg, #CPU32_bits :AND: &F0000000
ORR$cond $regtmp, $regtmp, #CPU32_bits :AND: &0FFFFFFF
|
......@@ -378,13 +378,13 @@ CPU32_bits PSRto32 $bits
; **************************************************
MACRO
$label SETV $cond
$label mymsr $cond, CPSR_f, #N_bit+V_bit
$label MSR$cond CPSR_f, #N_bit+V_bit
MEND
; ***********************************************
; *** TOGPSR - Toggle bits in PSR from the ***
; *** mask in $bits, using register $regtmp ***
; ***********************************************
; *********************************************************
; *** TOGPSR - Toggle bits in PSR from the ***
; *** immediate mask in $bits, using register $regtmp ***
; *********************************************************
MACRO
$label TOGPSR $bits, $regtmp, $cond, $oldpsr
LCLS srcreg
......@@ -393,16 +393,16 @@ srcreg SETS "$regtmp"
|
srcreg SETS "$oldpsr"
]
$label mymrs $cond, $srcreg, CPSR
CPU32_bits PSRto32 $bits
CPU32_bits PSRto32 $bits ; Map to 32 bit PSR
$label MRS$cond $srcreg, CPSR
EOR$cond $regtmp, $srcreg, #CPU32_bits
somemsr $cond, CPSR, $regtmp, CPU32_bits, unsafe
MEND
; ***********************************************
; *** TOGPSRR - Toggle bits in PSR from the ***
; *** mask in $regtog, using reg $regtmp ***
; ***********************************************
; ************************************************
; *** TOGPSRR - Toggle bits in PSR from the ***
; *** mask in $regtog, using register $regtmp ***
; ************************************************
MACRO
$label TOGPSRR $regtog, $regtmp, $cond, $oldpsr, $fields
LCLS srcreg
......@@ -417,7 +417,7 @@ srcreg SETS "$regtmp"
|
srcreg SETS "$oldpsr"
]
$label mymrs $cond, $srcreg, CPSR
$label MRS$cond $srcreg, CPSR
EOR$cond $regtmp, $srcreg, $regtog
mymsr $cond, CPSR_$field, $regtmp, , unsafe
MEND
......@@ -441,10 +441,13 @@ $label SCPSR $value, (I_bit+F_bit+SVC_mode):EOR:($value), $regtmp, $cond, $ol
] ; :LNOT: No32bitCode
; Original AAsm macros
; ****************************************************
; *** mrs/msr - Lowercase funny names for aasm. ***
; *** Due for retirement, aasm is redundant now. ***
;*****************************************************
MACRO
$label mrs $cond, $rd, $psrs
$label mymrs $cond, $rd, $psrs
$label MRS$cond $rd, $psrs
MEND
MACRO
......@@ -452,7 +455,6 @@ $label msr $cond, $psrl, $op2a, $op2b
$label mymsr $cond, $psrl, $op2a, $op2b
MEND
; ***************************************************
; *** somemsr - Set some fields of the PSR from ***
; *** $op, according to $mask. The mask should ***
......@@ -480,7 +482,10 @@ s SETS s:CC:"f"
$label mymsr $cond, $s, $op, , $sabug
MEND
; Funny names for ObjAsm compatibility
; ****************************************************
; *** mymrs - Perform an MRS operation. ***
; *** Due for retirement, objasm supports MRS now. ***
;*****************************************************
MACRO
$label mymrs $cond, $rd, $psrs
$label
......@@ -600,37 +605,24 @@ op SETA ($op2a) :OR: (0:SHL:25)
]
MEND
; SetMode newmode, reg1, regoldpsr
;
; Sets processor mode to constant value newmode
; using register reg1 as a temporary.
; If regoldpsr is specified, then this register
; on exit holds the old PSR before the mode change
; reg1 on exit always holds the new PSR after the mode change
MACRO
SetMode $newmode, $reg1, $regoldpsr
[ "$regoldpsr"=""
mymrs AL, $reg1, CPSR
BIC $reg1, $reg1, #&1F
ORR $reg1, $reg1, #$newmode
mymsr AL, CPSR_c, $reg1
|
mymrs AL, $regoldpsr, CPSR
BIC $reg1, $regoldpsr, #&1F
ORR $reg1, $reg1, #$newmode
mymsr AL, CPSR_c, $reg1
]
MEND
; Assembly of the ARMv5 BKPT instruction
; ****************************************************
; *** SetMode - sets processor mode to constant ***
; *** value newmode using register regtmp as a ***
; *** temporary. ***
; ****************************************************
MACRO
$lbl BKPT $val
[ $val < 0 :LOR: $val > &FFFF
! 0, "immediate value out of range"
]
DCI &E1200070 + ((($val) :SHR: 4) :SHL: 8) + (($val) :AND: &F)
SetMode $newmode, $regtmp, $oldpsr
[ "$oldpsr"=""
MRS $regtmp, CPSR
BIC $regtmp, $regtmp, #M32_bits
ORR $regtmp, $regtmp, #$newmode
MSR CPSR_c, $regtmp
|
MRS $oldpsr, CPSR
BIC $regtmp, $oldpsr, #M32_bits
ORR $regtmp, $regtmp, #$newmode
MSR CPSR_c, $regtmp
]
MEND
] ; :LNOT: :DEF: Included_Hdr_CPU_Generic32
......
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