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; Copyright 2008 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
;     http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
        SUBT    Definition of the machine

OldOpt  SETA    {OPT}
        OPT     OptNoList+OptNoP1List

 [ :LNOT: :DEF: Included_Hdr_Machine_Machine
        GBLL    Included_Hdr_Machine_Machine
Included_Hdr_Machine_Machine SETL {TRUE}

; ***********************************
; ***    C h a n g e   L i s t    ***
; ***********************************
;
; Date       Name          Description
; ----       ----          -----------
; 21-Apr-97  SMC           Now only one header file.

; Define Machine variable and set it by including appropriate header.
;

; Define boolean variables for each machine to avoid possibility of typos in
; strings.  NEVER use these outside this header file.  Use feature tests
; instead.
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                GBLL    M_Falcon     ; }
                GBLL    M_Morris     ; }
                GBLL    M_Omega      ; } Support being
                GBLL    M_Peregrine  ; } phased out
                GBLL    M_STB3       ; }
                GBLL    M_STB400     ; }
                GBLL    M_Lazarus    ; }
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M_Falcon        SETL    Machine="Falcon"
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M_Lazarus       SETL    Machine="Lazarus"
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M_Morris        SETL    Machine="Morris"
M_Omega         SETL    Machine="Omega"
M_Peregrine     SETL    Machine="Peregrine"
M_STB3          SETL    Machine="STB3"
M_STB400        SETL    Machine="STB400"
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                GBLL    M_32
                GBLL    M_All
                GBLL    M_All32
                GBLL    M_Archimedes
                GBLL    M_ARM11ZF
                GBLL    M_CortexA8
                GBLL    M_CortexA9
                GBLL    M_IOMD
                GBLL    M_STB5
                GBLL    M_Tungsten
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M_32            SETL    Machine="32"
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M_All           SETL    Machine="All"
M_All32         SETL    Machine="All32"
M_Archimedes    SETL    Machine="Archimedes"
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M_ARM11ZF       SETL    Machine="ARM11ZF"
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M_CortexA8      SETL    Machine="CortexA8"
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M_CortexA9      SETL    Machine="CortexA9"
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M_IOMD          SETL    Machine="IOMD"
M_STB5          SETL    Machine="STB5"
M_Tungsten      SETL    Machine="Tungsten"
72

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; Are we only supporting 26bit processor modes?
; If true, we mustn't rely on MSR, MRS etc, and we should be
; RISC OS 3.1 compatible.
                GBLL    No32bitCode
No32bitCode     SETL    M_Archimedes :LOR: M_Morris :LOR: M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400

; Are we only supporting 32bit processor modes?
                GBLL    No26bitCode
No26bitCode     SETL    M_32 :LOR: M_Lazarus :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_CortexA8 :LOR: M_CortexA9

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        ; If this makes your head hurt, the other way of looking at it is
        ;   26/32 neutral => No32bitCode FALSE No26bitCode FALSE
        ;   32 only       => No32bitCode FALSE No26bitCode TRUE
        ;   26 only       => No32bitCode TRUE  No26bitCode FALSE
        ASSERT  :LNOT: (No26bitCode :LAND: No32bitCode)

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; Override optimisation settings to avoid using unaligned LDR(H)/STR(H) on ARMv6+
; This switch should only be enabled for debugging purposes
                GBLL    NoUnaligned
NoUnaligned     SETL    M_CortexA8 :LOR: M_ARM11ZF :LOR: M_CortexA9

; Do we need to deal with the StrongARM conditional MSR CPSR_c bug?
                GBLL    StrongARM_MSR_bug
StrongARM_MSR_bug SETL  M_All :LOR: M_All32 :LOR: M_IOMD

98
     [ :LNOT: M_All :LAND: :LNOT: M_All32
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; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;               Switches that should not be used by machine-independent code
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129

; CPU type (processor model, excluding cache and memory management)
                GBLS    CPU_Type
CPU_Type        SETS    "ARM600"
                GBLS    GetCPU
GetCPU          SETS    ("GET Hdr:CPU." :CC: "$CPU_Type")

; IO type (non generic interrupt masks, some IO locations)
                GBLS    IO_Type
IO_Type         SETS    "IOMD"
                GBLS    GetIO
GetIO           SETS    ("GET Hdr:IO." :CC: "$IO_Type")

; Video controller - does the sound too
                GBLS    VIDC_Type
VIDC_Type       SETS    "VIDC20"
                GBLS    GetVIDC
GetVIDC         SETS    "GET Hdr:VIDC." :CC: VIDC_Type

; Memory controller, excluding memory management stuff. This
; one deals with memory speeds and DMA
                GBLS    MEMC_Type
MEMC_Type       SETS    "IOMD"
                GBLS    GetMEMC
GetMEMC         SETS    "GET Hdr:IO." :CC: MEMC_Type

                GBLS    MEMM_Type
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        [ M_CortexA8 :LOR: M_CortexA9 :LOR: M_ARM11ZF
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MEMM_Type       SETS    "VMSAv6"
        |
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MEMM_Type       SETS    "ARM600"
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        ]
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                GBLS    GetMEMM
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GetMEMM         SETS    "GET Hdr:MEMM." :CC: MEMM_Type
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; Floppy controller
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                GBLS    FDC_Type
FDC_Type        SETS    "FDC711"
                GBLS    GetFDC
GetFDC          SETS    "GET Hdr:FDC." :CC: FDC_Type

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; Keyboard style
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                GBLS    Keyboard_Type
        [ M_Lazarus
Keyboard_Type   SETS    "RCMM"
        |
Keyboard_Type   SETS    "PC"
        ]

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; VIDC Clock sources
                GBLS    VIDCClockSource
        [ M_Falcon :LOR: M_Morris :LOR: M_IOMD :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_32
VIDCClockSource SETS    "VCO"
        |
         [ M_STB400
VIDCClockSource SETS    "HCLK"
         |
          [ M_Lazarus
VIDCClockSource SETS    "RCLK"
          |
VIDCClockSource SETS    "VCLK"
          ]
         ]
        ]
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; VCO not fitted, so don't attempt to use VCLK.
                GBLL    DontUseVCO
DontUseVCO      SETL    M_Lazarus :LOR: M_STB400
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; Are we using a HAL?
                GBLL    HAL
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HAL             SETL    M_32 :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_CortexA8 :LOR: M_CortexA9
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; General flag for STB/NCD-type products
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                GBLL    STB
STB             SETL    M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400 :LOR: M_Lazarus
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; Support for extension ROMs in 2nd bank
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                GBLL    ExtROMSupport
ExtROMSupport   SETL    M_Falcon :LOR: M_Peregrine :LOR: M_STB3 :LOR: ((M_Omega :LOR: M_Lazarus :LOR: M_STB400) :LAND: {FALSE})
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; Support for OS images in 2nd ROM bank
185 186
                GBLL    ROMCardSupport
ROMCardSupport  SETL    M_Omega
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; 2nd ROM bank is 16bit wide
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                GBLL    ExtROMis16bit
ExtROMis16bit   SETL    M_Falcon :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400
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; Maximum clock rate (in kHz) for the I2C bus? Limited by the slowest device on the bus.
                GBLA    MaxI2Cspeed
 [ M_Lazarus
MaxI2Cspeed     SETA    1000
 |
MaxI2Cspeed     SETA    100
 ]

200
; E2ROM is supported at i2c addresses >= A8 in addition to normal CMOS RAM
201
; Note that this also controls HAL NVRAM support, and RTCSupport.
202
                GBLL    E2ROMSupport
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E2ROMSupport    SETL    M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400 :LOR: M_STB5 :LOR: M_Lazarus :LOR: M_32 :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_ARM11ZF :LOR: M_CortexA8 :LOR: M_CortexA9
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; Should we probe IIC addresses &A0 and &D0 for an RTC? (Requires E2ROMSupport, else Phillips RTC at &A0 is assumed)
; Disabling this is useful for HAL platforms that use the HAL RTC API
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                GBLL    RTCSupport
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RTCSupport      SETL    :LNOT: (M_CortexA8 :LOR: M_CortexA9)
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; Support for network 'podule' cards
                GBLL    NetPodSupport
NetPodSupport   SETL    M_IOMD :LOR: M_Morris

; Number of podules to look at (can be zero)
                GBLA    NumberOfPodules
 [ M_STB400 :LOR: M_Lazarus
NumberOfPodules SETA    1
 |
   [ M_STB3 :LOR: M_Tungsten
NumberOfPodules SETA    4
   |
     [ M_Morris :LOR: M_IOMD
NumberOfPodules SETA    8
     |
NumberOfPodules SETA    0
     ]
   ]
 ]
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; Whether combo chip should be configured for active high interrupts
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                GBLL    ComboIRQsActiveHigh
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ComboIRQsActiveHigh SETL M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB400 :LOR: M_Lazarus

; Some IOMD interrupts have been reassigned, to cope with the combo chip
; now having active-high interrupts.
; Printer, serial, expansion card 0 move; floppy, IDE, NIC go; gain 2 MPEG interrupts
                GBLL    ReassignedIOMDInterrupts
ReassignedIOMDInterrupts SETL ComboIRQsActiveHigh :LAND: :LNOT: NetPodSupport :LAND: M_STB400

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; Power saving model from the Stork laptop
                GBLL    StorkPowerSave
StorkPowerSave  SETL    {TRUE}
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; Support for battery manager hardware
                GBLL    BatManSupport
BatManSupport   SETL    {FALSE} :LAND: StorkPowerSave
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; Support for 7500FE
                GBLL    MorrisSupport
MorrisSupport   SETL    {TRUE}
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; Less blocky teletext font
                GBLL    HiResTTX
HiResTTX        SETL    M_Lazarus :LOR: M_STB400 :LOR: M_STB5 :LOR: M_Tungsten :LOR: M_ARM11ZF
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; Teletext rendered at 8bpp
                GBLL    TTX256
TTX256          SETL    M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF
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; Safe area when doing TV modes
; Expressed as percentage of screen not to use - left, bottom, right, top
                GBLS    PALSafeArea
                GBLS    NTSCSafeArea
  [ M_Lazarus
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PALSafeArea     SETS    "6, 6, 6, 6"
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NTSCSafeArea    SETS    "3, 6, 3, 6" ; This is what the original Model 1 had
  |
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    [ M_STB400
PALSafeArea     SETS    "8, 6, 8, 6"
    |
PALSafeArea     SETS    "8, 8, 8, 8"
    ]
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NTSCSafeArea    SETS    "5, 6, 5, 6"
  ]

; Only 13.5MHz pixel clock available for TV monitor types
                GBLL    Only13500kHzTV
Only13500kHzTV  SETL    M_STB5

; Hardware interlace available from HAL
                GBLL    HWInterlace
HWInterlace     SETL    M_STB5

; Number of columns to use for default PAL mode - some systems
; don't use the standard 768.
                GBLA    PAL_Columns
 [ M_Lazarus
PAL_Columns     SETA    800
 |
  [ M_STB5 :LOR: M_STB400 :LOR: M_STB3
PAL_Columns     SETA    720
  |
PAL_Columns     SETA    768
  ]
 ]
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         [ :LNOT: HAL
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; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;               Switches that are pre-HAL & due for retirement
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

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; Define the number of cycles required to access the ROMs.  These only work in 7500/7500FE based systems at the moment.
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                        GBLS    ROMSpeedNSTicks
                        GBLS    ROMSpeedBurstTicks
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 [ M_STB3 :LOR: M_Lazarus
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ROMSpeedNSTicks         SETS    "4"
ROMSpeedBurstTicks      SETS    "0"
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; Ultimately STB400 should be 7+4 (109ns+62ns). For development, 10+8 (156ns+125ns)
 |
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ROMSpeedNSTicks         SETS    "5"
ROMSpeedBurstTicks      SETS    "4"
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 ]

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; ROM speed is normal, not divide by 2
                GBLL    ROMSpeedNormal
ROMSpeedNormal  SETL    M_Falcon :LOR: M_Morris
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                        GBLL    FECPUSpeedNormal
FECPUSpeedNormal        SETL    M_STB3 :LOR: M_STB400 :LOR: M_Lazarus
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                        GBLL    FEIOSpeedHalf
FEIOSpeedHalf           SETL    M_Lazarus

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         ] ; :LNOT: HAL
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328
         [ STB :LAND: :LNOT: HAL
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; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;               Switches that are pre-HAL set top box & due for retirement
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

; The combo chip is clocked at 14.318MHz, instead of 24MHz
                GBLL    ComboClock14MHz
ComboClock14MHz SETL    {FALSE}

; TV modes are produced by Chrontel device
                GBLL    ChrontelSupport
ChrontelSupport SETL    M_32

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; Modems as found in STB Roadsters, NC (Model 1) and NC
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        [ M_Falcon :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_Omega :LOR: M_Lazarus
                GBLA    Modem_DefaultPodule
                GBLA    Modem_RegisterSetOffset         ; offset within EASI
                GBLA    Modem_InterruptStatusOffset     ; offset within EASI
         [ M_Falcon :LOR: M_Peregrine :LOR: M_STB3
Modem_DefaultPodule     SETA    1       ; default podule is 1 on an STB
         |
Modem_DefaultPodule     SETA    0       ; have real podules on the rest
         ]
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         [ M_Lazarus
Modem_RegisterSetOffset         SETA    &800000         ; Kerner modem card
Modem_InterruptStatusOffset     SETA    -1              ; no status...
         |
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         [ M_Falcon :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_Omega
Modem_RegisterSetOffset         SETA    &803000         ; CME modem card
Modem_InterruptStatusOffset     SETA    &802000         ; CME modem card
         |
Modem_RegisterSetOffset         SETA    &000be0         ; NC modem
Modem_InterruptStatusOffset     SETA    &000bfc         ; NC modem
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         ]
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         ]
        ]
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; Configurable Standby key
                GBLA    SpecialKeyStandby
   [ M_Lazarus :LOR: M_32
SpecialKeyStandby SETA  &D7
   |
    [ M_STB5 :LOR: M_STB400
SpecialKeyStandby SETA  &D1
    |
374
SpecialKeyStandby SETA  -1
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    ]
   ]

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; Podule type of hardware in podule 0 address space
; number taken from Hdr:PoduleReg, or 0 if podule0 slot is a real slot.
                GBLA    FakePodule0
        [ M_Falcon
FakePodule0     SETA    &10E
        |
         [ M_Peregrine :LOR: M_STB3
FakePodule0     SETA    &121
         |
FakePodule0     SETA    0
         ]
        ]
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; Address of NTSC/not PAL flag, if on MPEG podule rather than CLINES, else 0
                GBLA    MPEGPoduleNTSCNotPALAddress
                GBLA    MPEGPoduleNTSCNotPALMask
        [ M_Falcon
MPEGPoduleNTSCNotPALAddress SETA    &88200000
MPEGPoduleNTSCNotPALMask    SETA    1 :SHL: 7
        |
         [ M_Peregrine
MPEGPoduleNTSCNotPALAddress SETA    &88400000
MPEGPoduleNTSCNotPALMask    SETA    1 :SHL: 5
         |
MPEGPoduleNTSCNotPALAddress SETA    0
MPEGPoduleNTSCNotPALMask    SETA    0
         ]
        ]
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; Name of the the header file which defines the MPEG podule
                GBLS    MPEGPoduleType
        [ M_Falcon
MPEGPoduleType  SETS    "MPEGCard"
        |
          [ M_Peregrine
MPEGPoduleType  SETS    "MPEG2Card"
          |
            [ M_STB3
MPEGPoduleType  SETS    "MPEG2bCard"
            |
              [ M_STB400
MPEGPoduleType  SETS    "MPEG2cCard"
              |
MPEGPoduleType  SETS    "Unknown..."    ; Unknown MPEG Podule type
              ]
            ]
          ]
        ]
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; Onboard podule 0 MPEG bit, 0 if bit not present
428
                GBLA    IOMD_C_MPEGfitted
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        [ M_Falcon :LOR: M_Morris :LOR: M_Peregrine :LOR: M_STB3
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IOMD_C_MPEGfitted       SETA    (1<<0)
431
        |
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IOMD_C_MPEGfitted       SETA    0
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        ]

; MonitorTypeLatch, or 0 if latch not present
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                GBLA    IOMD_C_MonitorType
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        [ M_Omega
438
IOMD_C_MonitorType      SETA    (1<<0)
439
        |
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IOMD_C_MonitorType      SETA    0
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        ]

; Front panel Red LED Write bit, or 0 if bit not present
444
                GBLA    IOMD_C_FrontPanelRedLED
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        [ M_Falcon :LOR: M_Morris :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400
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IOMD_C_FrontPanelRedLED SETA    (1<<1)
447
        |
448
IOMD_C_FrontPanelRedLED SETA    0
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        ]

; Video power down for Chrontel, or 0 if bit not present
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                GBLA    IOMD_C_VideoPowerDown
IOMD_C_VideoPowerDown   SETA    0
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; ROM Card Vpp control, or 0 if bit not present
456
                GBLA    IOMD_C_ROMCardVpp
457
        [ M_Omega
458
IOMD_C_ROMCardVpp       SETA    (1<<1)
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        |
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IOMD_C_ROMCardVpp       SETA    0
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        ]

; EEPROM protection control, or 0 if bit not present
                GBLA    IOMD_C_EEPROMProtect
        [ M_Lazarus
IOMD_C_EEPROMProtect    SETA    (1<<1)
        |
IOMD_C_EEPROMProtect    SETA    0
        ]

; Front panel Green LED Write bit, or 0 if bit not present
472
                GBLA    IOMD_C_FrontPanelGrnLED
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        [ M_Falcon :LOR: M_Morris :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400
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IOMD_C_FrontPanelGrnLED SETA    (1<<2)
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        |
476
IOMD_C_FrontPanelGrnLED SETA    0
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        ]

; TVMode Write bit, or 0 if bit not present
480
                GBLA    IOMD_C_TVMode
481
        [ M_Omega
482
IOMD_C_TVMode           SETA    (1<<2)
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        |
484
IOMD_C_TVMode           SETA    0
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        ]

; Right LED bit, or 0 if bit not present
488
                GBLA    IOMD_C_FrontPanelRightLED
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        [ M_Lazarus
490
IOMD_C_FrontPanelRightLED       SETA    (1<<3)
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        |
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IOMD_C_FrontPanelRightLED       SETA    0
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        ]

; General IO bit
496
                GBLA    IOMD_C_GenIO
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        [ M_Omega
498
IOMD_C_GenIO            SETA    (1<<3)
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        |
500
IOMD_C_GenIO            SETA    0
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        ]

; SCART Control bit 0
504
                GBLA    IOMD_C_MPEG_CTRL_0
505
        [ M_STB3 :LOR: M_STB400
506
IOMD_C_MPEG_CTRL_0      SETA    (1<<3)
507
        |
508
IOMD_C_MPEG_CTRL_0      SETA    0
509 510 511
        ]

; CD fitted bit. 0=fitted, or 0 if bit not present
512
                GBLA    IOMD_C_CDfitted
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        [ M_Falcon :LOR: M_Morris :LOR: M_Peregrine
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IOMD_C_CDfitted         SETA    (1<<4)
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        |
516
IOMD_C_CDfitted         SETA    0
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        ]

; PAL/NTSC bit, or 0 if bit not present
520
                GBLA    IOMD_C_PALNTSCType
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        [ M_Omega :LOR: M_STB3 :LOR: M_STB400 :LOR: M_Lazarus
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IOMD_C_PALNTSCType      SETA    (1<<4)
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        |
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IOMD_C_PALNTSCType      SETA    0
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        ]

; Joystick type bits in IOMD, or 0 if bits not present
528
                GBLA    IOMD_C_JoystickDetectBits
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        [ M_Falcon :LOR: M_Morris :LOR: M_Peregrine
530
IOMD_C_JoystickDetectBits       SETA    (2_11<<5)
531
        |
532
IOMD_C_JoystickDetectBits       SETA    0
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        ]

; Interlace phase bit in IOMD, or 0 if bit not present
536
                GBLA    IOMD_C_PhaseDetectBit
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        [ M_Omega :LOR: M_STB3 :LOR: M_STB400
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IOMD_C_PhaseDetectBit   SETA    (1<<5)
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        |
540
IOMD_C_PhaseDetectBit   SETA    0
541 542 543
        ]

; Front panel button (may not actually be on front panel), 0=pressed
544
                GBLA    IOMD_C_FrontPanelButton
545
        [ M_Omega :LOR: M_Lazarus
546
IOMD_C_FrontPanelButton SETA    (1<<6)
547
        |
548
IOMD_C_FrontPanelButton SETA    0
549 550 551
        ]

; SCART Control bit 1
552
                GBLA    IOMD_C_MPEG_CTRL_1
553
        [ M_STB3 :LOR: M_STB400
554
IOMD_C_MPEG_CTRL_1      SETA    (1<<6)
555
        |
556
IOMD_C_MPEG_CTRL_1      SETA    0
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        ]

; Front panel button function
;selects the front panel buton function
;used to select the maintainance OS or clear CMOS setting
562 563
                GBLL    FrontPanelButtClearsCMOS
FrontPanelButtClearsCMOS        SETL    {TRUE}
564 565 566 567 568 569 570 571 572

; If nothing relies on CLK16, CLK8, REF8M or CLK2 for anything other
; than timing processor I/O, we can stop them when the processor is
; placed into suspend mode. Any system with a real expansion card slot
; must keep them runnning.
                GBLL    StopClocksDuringIdle
StopClocksDuringIdle    SETL    M_Lazarus :LOR: M_STB400

; Front panel Write bit. 1=red, 0=green
573
                GBLA    IOMD_C_FrontPanelLED
574
        [ M_Omega
575
IOMD_C_FrontPanelLED    SETA    (1<<7)
576
        |
577
IOMD_C_FrontPanelLED    SETA    0
578 579 580
        ]

; Left LED bit, or 0 if not present
581
                GBLA    IOMD_C_FrontPanelLeftLED
582
        [ M_Lazarus
583
IOMD_C_FrontPanelLeftLED        SETA    (1<<7)
584
        |
585
IOMD_C_FrontPanelLeftLED        SETA    0
586 587 588
        ]

; Watchdog Write bit.
589
                GBLA    IOMD_C_Watchdog
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590
        [ M_Falcon :LOR: M_Morris :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400
591
IOMD_C_Watchdog         SETA    (1<<7)
592
        |
593
IOMD_C_Watchdog         SETA    0
594 595 596
        ]

; Mask of all the readable bits
597 598
                GBLA    IOMD_C_ReadMask
IOMD_C_ReadMask SETA    (IOMD_C_MPEGfitted :OR: IOMD_C_MonitorType :OR: IOMD_C_GenIO :OR: IOMD_C_CDfitted :OR: IOMD_C_PALNTSCType :OR: IOMD_C_PhaseDetectBit :OR: IOMD_C_JoystickDetectBits :OR: IOMD_C_FrontPanelButton)
599 600 601 602 603 604 605

; Do we flash the LEDs in POST? Yes, if we have them, and we're not Lazarus (they're not
; really LEDs).
                GBLL    POSTFlashesFrontPanelLEDs
POSTFlashesFrontPanelLEDs       SETL    ((IOMD_C_FrontPanelLED <> 0) :LOR: (IOMD_C_FrontPanelRightLED <> 0 :LAND: IOMD_C_FrontPanelLeftLED <> 0)) :LAND: :LNOT: M_Lazarus

; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
606
;               MAC Address Read from NVRAM
607 608
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
609 610 611
;       The MAC address can be read from the NVRAM tag MACAddress and
;       a SetMac utility is provided in !Boot.Utils to enable the MAC address to be
;       programmed for prototypes and development machines.
612
;
613 614 615 616
;       Since it is dangerous to rely on the NVRAM to hold our MAC address when it is not
;       protected in any way, we can store two copies of it, each with their own checksum.
;       If either copy becomes damaged we can repair it using the other copy.
;       MACNVRAM2COPIES is set to indicate that we are using two copies in the NVRAM.
617
;
618
;       Paul Skirrow, 22 Feb 2000
619

620 621
                GBLL    MACNVRAM2copies
MACNVRAM2copies SETL    {FALSE}
622

623 624
         ] ; STB :LAND: :LNOT: HAL
     ] ; :LNOT: M_All :LAND: :LNOT: M_All32
625 626 627 628
 ] ; :LNOT: :DEF: Included_Hdr_Machine_Machine

        OPT     OldOpt
        END