Arch 19.8 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98
; Copyright (c) 2009, RISC OS Open Ltd
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;     * Redistributions of source code must retain the above copyright
;       notice, this list of conditions and the following disclaimer.
;     * Redistributions in binary form must reproduce the above copyright
;       notice, this list of conditions and the following disclaimer in the
;       documentation and/or other materials provided with the distribution.
;     * Neither the name of RISC OS Open Ltd nor the names of its contributors
;       may be used to endorse or promote products derived from this software
;       without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY RISC OS OPEN LTD ''AS IS'' AND ANY EXPRESS OR
; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
; EVENT SHALL RISC OS OPEN LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


; Historically, RISC OS has usually tried to cater for all CPU types at run
; time. This was partly because CPUs were swappable in some machines, and
; partly because of economies of scale when manufacturing masked ROMs. Neither
; of these arguments are as important in today's environment.
;
; It is probably desirable for disc components to continue to be as widely
; applicable as possible to help with version control. However, there may be
; exceptions in certain cases, e.g. codecs will often want to be tuned to a
; specific architecture. But ROM builds can benefit, in terms of code size,
; speed and maintainability, from being targetted at the correct CPU -
; previously, such customisation was mainly confined to the FPASC/FPEmulator.
;
; This header file translates between the "Machine" build variable and a set of
; assembly-time variables that describe the range of CPUs which must be
; supported by that build. Thus, the author of the software can switch
; depending upon the specific CPU feature that they require, and build
; maintainers can select the range of CPUs that a given build must run on.
; Typically, except for IOMD machines, a ROM build will only target one CPU,
; but a disc build will target a wide range of CPUs.
;
; The assembler variables are of the form
;
;  SupportARMvx -> at least one supported platform is of architecture x or later
;  NoARMvx      -> at least one supported platform is of architecture before x
;
; or for architecture variants (usually a single letter), the variables
; indicate whether one or more supported platforms do or don't support that
; variant.


; Example 1: to provide a set of implementations to be selected on the basis of
; the oldest required architecture
;
;  [ NoARMa
;    ; implementation suitable for ARMv2 or later
;  |
;  [ NoARMv3
;    ; implementation suitable for ARMv2a or later
;  |
;  [ NoARMv4
;    ; implementation suitable for ARMv3 or later
;  |
;    ; implementation suitable for ARMv4 or later
;  ]
;  ]
;  ]

; Example 2: to bracket an implementation suitable for ARMv2 to v4 but not v5
; onwards - for example because it stores flags in bits 0 and 1 of PC addresses
; on the stack
;
;  [ :LNOT: SupportARMv5
;    ; insert code here
;  |
;    ! 1, "No suitable implementation for required architecture(s) yet"
;  ]

; Example 3: to bracket an implementation only suitable for v4T and v5 -
; for example because it uses fine (1K) page tables
;
;  [ SupportARMv6 :LOR: NoARMT
;    ; Build targets include pre-v4T and/or v6-or-later
;    ! 1, "No suitable implementation for required architecture(s) yet"
;  |
;    ; insert code here
;  ]

; Example 4: change from SVC mode to IRQ mode in the minimal number of
; instructions for the required architecture(s)
;
;  [ :LNOT: SupportARMv3
;    ; Can only be executed in 26-bit mode
99
;    TEQP    PC, #2
100 101 102 103
;    NOP
;  |
;  [ NoARMG
;    ; Could be either 26-bit mode or 32-bit mode
104 105 106
;    TEQ     PC, PC
;    MSREQ   CPSR_c, #&12
;    TEQNEP  PC, #2
107 108 109
;    NOP
;  |
;    ; Can only be executed in 32-bit mode
110
;    MSR     CPSR_c, #&12
111 112 113 114
;  ]
;  ]

; Example 5: load a word from address in r0, which may be non-word-aligned,
115
; into r1. Registers r0, r2 and r3 may be corrupted.
116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141
;
; Under ARMv6, unaligned behaviour can be configured either way, but since
; ARMv7 mandates the new behaviour we have to handle it anyway, so we may as
; well run ARMv6 CPUs in ARMv7 mode.
;
;  [ :LNOT: NoARMv6
;         ; Only has to operate on CPUs with automatic unaligned LDR
;         LDR     r1,[r0]
;  |
;         ANDS    r3,r0,#3
;    [ SupportARMv6
;         ; Need to handle both CPU types at run time
;         BICNE   r0,r0,#3
;    |
;         ; Only has to operate on CPUs with traditional ARM LDM behaviour
;         ; where the bottom two bits of r0 are ignored
;    ]
;         LDMNEIA r0!,{r1,r2}
;         MOVNE   r3,r3,LSL #3
;         LDREQ   r1,[r0]
;         MOVNE   r1,r1,LSR r3
;         RSBNE   r3,r3,#32
;         ORRNE   r1,r1,r2,LSL r3
;  ]


142 143 144
OldOpt  SETA    {OPT}
        OPT     OptNoList+OptNoP1List

145 146
 [ :LNOT: :DEF: Included_Hdr_CPU_Arch
        GBLL    Included_Hdr_CPU_Arch
147
Included_Hdr_CPU_Arch SETL {TRUE}
148

149
 [ :LNOT: :DEF: Included_Hdr_Machine_Machine
150
        GET     Hdr:Machine.<Machine>
151
 ]
152 153 154 155 156 157 158 159 160 161 162 163 164 165

; MRS/MSR and USR32, IRQ32, FIQ32, SVC32, ABT and UND modes
MchFlg_v3   * 2_00000000000000000000000000000001
; LDRH/STRH, LDRSB/H, SYS mode
MchFlg_v4   * 2_00000000000000000000000000000010
; CLZ, BLX, BKPT, LDC2, STC2, CDP2, MCR2, MRC2
MchFlg_v5   * 2_00000000000000000000000000000100
; LDREX/STREX, cross-mode exception save/restore, endian-switching, packed byte
; and halfword add/subtract/absolute/saturate/halve/pack/extract,
; sign-extension, saturation, 32+32+32*32, 32+16*16+16*16, 64+16*16+16*16 and
; MSW 32*32 MLA, MLS and MUL, MCRR2, MRRC2
MchFlg_v6   * 2_00000000000000000000000000001000
; DBG, DMB, PLI, PLDW and ThumbEE instruction set
MchFlg_v7   * 2_00000000000000000000000000010000
166 167
; CRC32, HLT, LDA(EX), SEVL, STL(EX), VMAXNM, VMINNM, VRINT, VSEL
MchFlg_v8   * 2_00000000000000000000000000100000
168
; SWP and SWPB
169
MchFlg_a    * 2_00000000000000000000000001000000
170
; Hardware FPA - FPA10 if v2 (ARM3); FPA11 if v3 (ARM700 or ARM7500FE)
171
MchFlg_F    * 2_00000000000000000000000010000000
172
; Withdrawal of 26-bit modes
173
MchFlg_G    * 2_00000000000000000000000100000000
174
; 64+32x32 bit MLA and MUL
175
MchFlg_M    * 2_00000000000000000000001000000000
176 177
; BX and Thumb - Thumbv1 if ARMv4; Thumbv2 if ARMv5; Thumbv3 if ARMv6
; no established terminology for later revisions
178
MchFlg_T    * 2_00000000000000000000010000000000
179 180
; Enhanced DSP extension - 32+16*16, 33+32*16, 64+16*16 MLA and MUL,
; saturated ADD/SUB
181
MchFlg_E    * 2_00000000000000000000100000000000
182
; PLD, LDRD/STRD, MRRC/MCRR
183
MchFlg_P    * 2_00000000000000000001000000000000
184 185
; Intel XScale extensions - 40+32*32, 40+16*16, 40+16*16+16*16 MLA,
; mini data cache
186
MchFlg_X    * 2_00000000000000000010000000000000
187
; Jazelle extension - BXJ
188
MchFlg_J    * 2_00000000000000000100000000000000
189 190
; Multiprocessing extensions - CLREX, YIELD, WFE, WFI, SEV, SMI and
; security extensions
191
MchFlg_K    * 2_00000000000000001000000000000000
192 193
; Thumb 2 and more - MOVW, MOVH, bitfield operations, DSB, ISB,
; 8/16/64 bit LDR/STREX, LDRT/STRT for halfwords and signed bytes, 32-32*32 MLS
194 195 196 197 198
MchFlg_T2   * 2_00000000000000010000000000000000
; Virtualisation extension - ERET, HVC, banked MRS and MSR and hardware divide
MchFlg_VE   * 2_00000000000000100000000000000000
; Cryptographic extension - AES, SHA1, SHA256
MchFlg_C    * 2_00000000000001000000000000000000
199
; VFP - VFPv1 if ARMv5T; VFPv2 if ARMv5TE or ARMv6; VFPv3 if ARMv7
200
MchFlg_V    * 2_00000000000010000000000000000000
201
; VFP D variant (double precision)
202
MchFlg_VD   * 2_00000000000100000000000000000000
203
; VFP 32 double-precision registers variant
204
MchFlg_V32  * 2_00000000001000000000000000000000
205
; VFP half-precision variant
206
MchFlg_VH   * 2_00000000010000000000000000000000
Ben Avison's avatar
Ben Avison committed
207
; VFPv4 - fused multiply-accumulate
208
MchFlg_Vv4  * 2_00000000100000000000000000000000
209 210
; Advanced SIMD extensions - integer only if no VFP; FP half or single
; precision options mirror the VFP options
211
MchFlg_A     * 2_00000010000000000000000000000000
212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227
; Remaining flags reserved for future use
;MchFlg_     * 2_00000100000000000000000000000000
;MchFlg_     * 2_00001000000000000000000000000000
;MchFlg_     * 2_00010000000000000000000000000000
;MchFlg_     * 2_00100000000000000000000000000000
;MchFlg_     * 2_01000000000000000000000000000000
;MchFlg_     * 2_10000000000000000000000000000000

; Common flag combinations, to make the ArchitectureOption macro smaller
MchFlgs_v3   * 0            :OR: MchFlg_v3 :OR: MchFlg_a
MchFlgs_v4   * MchFlgs_v3   :OR: MchFlg_v4 :OR: MchFlg_M
MchFlgs_v4T  * MchFlgs_v4   :OR: MchFlg_G  :OR: MchFlg_T
MchFlgs_v5T  * MchFlgs_v4T  :OR: MchFlg_v5
MchFlgs_v5TE * MchFlgs_v5T  :OR: MchFlg_E  :OR: MchFlg_P
MchFlgs_v6   * MchFlgs_v5TE :OR: MchFlg_v6 :OR: MchFlg_J
MchFlgs_v7   * MchFlgs_v6   :OR: MchFlg_v7 :OR: MchFlg_K :OR: MchFlg_T2
228
MchFlgs_v8   * (MchFlgs_v7 :AND: :NOT: MchFlg_a) :OR: MchFlg_v8 :OR: MchFlg_VE :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH :OR: MchFlg_Vv4 :OR: MchFlg_A
229 230 231 232 233 234 235 236 237 238 239

        GBLA    MchFlgs_Cumulative
MchFlgs_Cumulative    SETA 0
        GBLA    MchFlgs_CumulativeNOT
MchFlgs_CumulativeNOT SETA 0

        MACRO
$lab    ArchitectureOption $arch
        LCLA MchFlgs
 [ "$arch" = "v2"
MchFlgs SETA 0
240
 ELIF "$arch" = "v2a"
241
MchFlgs SETA MchFlg_a
242
 ELIF "$arch" = "v2a_FPA"
243
MchFlgs SETA MchFlg_a :OR: MchFlg_F
244
 ELIF "$arch" = "v3"
245
MchFlgs SETA MchFlgs_v3
246
 ELIF "$arch" = "v3_FPA"
247
MchFlgs SETA MchFlgs_v3 :OR: MchFlg_F
248
 ELIF "$arch" = "v3G"
249
MchFlgs SETA MchFlgs_v3 :OR: MchFlg_G
250
 ELIF "$arch" = "v3M"
251
MchFlgs SETA MchFlgs_v3 :OR: MchFlg_M
252
 ELIF "$arch" = "v4xM"
253
MchFlgs SETA MchFlgs_v4 :AND: :NOT: MchFlg_M
254
 ELIF "$arch" = "v4"
255
MchFlgs SETA MchFlgs_v4
256
 ELIF "$arch" = "v4TxM"
257
MchFlgs SETA MchFlgs_v4T :AND: :NOT: MchFlg_M
258
 ELIF "$arch" = "v4T"
259
MchFlgs SETA MchFlgs_v4T
260
 ELIF "$arch" = "v5xM"
261
MchFlgs SETA MchFlgs_v5T :AND: :NOT: (MchFlg_M :OR: MchFlg_T)
262
 ELIF "$arch" = "v5"
263
MchFlgs SETA MchFlgs_v5T :AND: :NOT: MchFlg_T
264
 ELIF "$arch" = "v5TxM"
265
MchFlgs SETA MchFlgs_v5T :AND: :NOT: MchFlg_M
266
 ELIF "$arch" = "v5T"
267
MchFlgs SETA MchFlgs_v5T
268
 ELIF "$arch" = "v5T_VFP1"
269
MchFlgs SETA MchFlgs_v5T :OR: MchFlg_V
270
 ELIF "$arch" = "v5T_VFP1D"
271
MchFlgs SETA MchFlgs_v5T :OR: MchFlg_V :OR: MchFlg_VD
272
 ELIF "$arch" = "v5TExP"
273
MchFlgs SETA MchFlgs_v5TE :AND: :NOT: MchFlg_P
274
 ELIF "$arch" = "v5TE"
275
MchFlgs SETA MchFlgs_v5TE
276
 ELIF "$arch" = "v5TEX"
277
MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_X
278
 ELIF "$arch" = "v5TE_VFP2"
279
MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_V
280
 ELIF "$arch" = "v5TE_VFP2D"
281
MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_V :OR: MchFlg_VD
282
 ELIF "$arch" = "v5TEJ"
283
MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_J
284
 ELIF "$arch" = "v5TEJ_VFP2"
285
MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_J :OR: MchFlg_V
286
 ELIF "$arch" = "v5TEJ_VFP2D"
287
MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_J :OR: MchFlg_V :OR: MchFlg_VD
288
 ELIF "$arch" = "v6"
289
MchFlgs SETA MchFlgs_v6
290
 ELIF "$arch" = "v6_VFP2"
291
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_V
292
 ELIF "$arch" = "v6_VFP2D"
293
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_V :OR: MchFlg_VD
294
 ELIF "$arch" = "v6K"
295
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_K
296
 ELIF "$arch" = "v6K_VFP2"
297
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_K :OR: MchFlg_V
298
 ELIF "$arch" = "v6K_VFP2D"
299
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_K :OR: MchFlg_V :OR: MchFlg_VD
300
 ELIF "$arch" = "v6T2"
301
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_T2
302
 ELIF "$arch" = "v6T2_VFP2"
303
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_T2 :OR: MchFlg_V
304
 ELIF "$arch" = "v6T2_VFP2D"
305
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_T2 :OR: MchFlg_V :OR: MchFlg_VD
306
 ELIF "$arch" = "v7"
307
MchFlgs SETA MchFlgs_v7
308
 ELIF "$arch" = "v7_VFP3"
309
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V
310
 ELIF "$arch" = "v7_VFP3D"
311
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD
312
 ELIF "$arch" = "v7_VFP3D32"
313
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32
314
 ELIF "$arch" = "v7_VFP3H"
315
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VH
316
 ELIF "$arch" = "v7_VFP3DH"
317
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_VH
318
 ELIF "$arch" = "v7_VFP3D32H"
319
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH
320
 ELIF "$arch" = "v7_SIMD"
321
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_A
322
 ELIF "$arch" = "v7_VFP3_SIMD"
323
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_A
324
 ELIF "$arch" = "v7_VFP3D32_SIMD"
325
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_A
326
 ELIF "$arch" = "v7_VFP3H_SIMD"
327
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VH :OR: MchFlg_A
328
 ELIF "$arch" = "v7_VFP3D32H_SIMD"
329
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH :OR: MchFlg_A
330
 ELIF "$arch" = "v7VE_VFP4D32_SIMD"
331
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_VE :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH :OR: MchFlg_Vv4 :OR: MchFlg_A
332
 ELIF "$arch" = "v8"
333
MchFlgs SETA MchFlgs_v8
Ben Avison's avatar
Ben Avison committed
334 335
 ELIF "$arch" = "v8_crypto"
MchFlgs SETA MchFlgs_v8 :OR: MchFlg_C
336 337 338 339 340 341 342 343 344 345 346
 |
   ! 1, "Unrecognised architecture: $arch"
 ]
MchFlgs_Cumulative    SETA MchFlgs_Cumulative    :OR: MchFlgs
MchFlgs_CumulativeNOT SETA MchFlgs_CumulativeNOT :OR: :NOT: MchFlgs
        MEND

      [ "$Machine" = "Archimedes" ; pre-IOMD Acorn machines, 26-bit only
        ArchitectureOption v2
        ArchitectureOption v2a
        ArchitectureOption v2a_FPA
347 348 349 350 351 352 353 354
      ELIF "$Machine" = "26" ; All 26-bit capable machines, running in 26-bit mode
        ArchitectureOption v2
        ArchitectureOption v2a
        ArchitectureOption v2a_FPA
        ArchitectureOption v3
        ArchitectureOption v3_FPA
        ArchitectureOption v4
      ELIF "$Machine" = "32" ; basic 32-bit capable machines (used for many ARM7TDMI and ARM9 ports)
Ben Avison's avatar
Ben Avison committed
355 356 357 358
        ArchitectureOption v3
        ArchitectureOption v3_FPA
        ArchitectureOption v4
        ArchitectureOption v4T
359
      ELIF "$Machine" = "IOMD" ; 32-bit IOMD-class machines ARM6/ARM7/StrongARM
360 361 362
        ArchitectureOption v3
        ArchitectureOption v3_FPA
        ArchitectureOption v4
363
      ELIF "$Machine" = "Tungsten" ; Iyonix PC
364
        ArchitectureOption v5TEX
365
      ELIF "$Machine" = "ARM11ZF"
Ben Avison's avatar
Ben Avison committed
366
        ArchitectureOption v6K_VFP2D
367
      ELIF "$Machine" = "RPi" ; Raspberry Pi versions are similar enough that one ROM can handle three architectures
Ben Avison's avatar
Ben Avison committed
368
        ArchitectureOption v6K_VFP2D
369 370
        ArchitectureOption v7VE_VFP4D32_SIMD
        ArchitectureOption v8
371
      ELIF "$Machine" = "CortexA7" ; Cortex A7, A15 or A17, e.g. BCM2836, TI OMAP543x, TI AM5728
372
        ArchitectureOption v7VE_VFP4D32_SIMD
373
      ELIF "$Machine" = "CortexA8" ; Cortex A8, e.g. TI OMAP35xx
374
        ArchitectureOption v7_VFP3D32_SIMD
375
      ELIF "$Machine" = "CortexA9" ; Cortex A9, e.g. TI OMAP44xx, Freescale i.MX6
376
        ArchitectureOption v7_VFP3D32H_SIMD
Ben Avison's avatar
Ben Avison committed
377 378
      ELIF "$Machine" = "CortexA53" ; Cortex A53, A57, A35, A72 or A73, e.g. Allwinner A64, Broadcom BCM2837, Rockchip RK3399
        ArchitectureOption v8_crypto
379
      ELIF "$Machine" = "All" ; if the target code is required to run on
380 381 382
                           ; any RISC OS machine
        ArchitectureOption v2
        ArchitectureOption v2a_FPA
383
        ArchitectureOption v8
384
      ELIF "$Machine" = "All32" ; if the target code is required to run on
385 386 387
                             ; any 32-bit capable RISC OS machine
        ArchitectureOption v3
        ArchitectureOption v3_FPA
388
        ArchitectureOption v8
389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417
      |
        ! 1, "Unrecognised machine: $Machine"
      ]

        GBLL    SupportARMv3
SupportARMv3 SETL  (MchFlgs_Cumulative :AND: MchFlg_v3) > 0
        GBLL    NoARMv3
NoARMv3 SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_v3) > 0

        GBLL    SupportARMv4
SupportARMv4 SETL  (MchFlgs_Cumulative :AND: MchFlg_v4) > 0
        GBLL    NoARMv4
NoARMv4 SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_v4) > 0

        GBLL    SupportARMv5
SupportARMv5 SETL  (MchFlgs_Cumulative :AND: MchFlg_v5) > 0
        GBLL    NoARMv5
NoARMv5 SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_v5) > 0

        GBLL    SupportARMv6
SupportARMv6 SETL  (MchFlgs_Cumulative :AND: MchFlg_v6) > 0
        GBLL    NoARMv6
NoARMv6 SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_v6) > 0

        GBLL    SupportARMv7
SupportARMv7 SETL  (MchFlgs_Cumulative :AND: MchFlg_v7) > 0
        GBLL    NoARMv7
NoARMv7 SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_v7) > 0

418 419 420 421 422
        GBLL    SupportARMv8
SupportARMv8 SETL  (MchFlgs_Cumulative :AND: MchFlg_v8) > 0
        GBLL    NoARMv8
NoARMv8 SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_v8) > 0

423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477
        GBLL    SupportARMa
SupportARMa SETL   (MchFlgs_Cumulative :AND: MchFlg_a) > 0
        GBLL    NoARMa
NoARMa  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_a) > 0

        GBLL    SupportARMF
SupportARMF SETL   (MchFlgs_Cumulative :AND: MchFlg_F) > 0
        GBLL    NoARMF
NoARMF  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_F) > 0

        GBLL    SupportARMG
SupportARMG SETL   (MchFlgs_Cumulative :AND: MchFlg_G) > 0
        GBLL    NoARMG
NoARMG  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_G) > 0

        GBLL    SupportARMM
SupportARMM SETL   (MchFlgs_Cumulative :AND: MchFlg_M) > 0
        GBLL    NoARMM
NoARMM  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_M) > 0

        GBLL    SupportARMT
SupportARMT SETL   (MchFlgs_Cumulative :AND: MchFlg_T) > 0
        GBLL    NoARMT
NoARMT  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_T) > 0

        GBLL    SupportARME
SupportARME SETL   (MchFlgs_Cumulative :AND: MchFlg_E) > 0
        GBLL    NoARME
NoARME  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_E) > 0

        GBLL    SupportARMP
SupportARMP SETL   (MchFlgs_Cumulative :AND: MchFlg_P) > 0
        GBLL    NoARMP
NoARMP  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_P) > 0

        GBLL    SupportARMX
SupportARMX SETL   (MchFlgs_Cumulative :AND: MchFlg_X) > 0
        GBLL    NoARMX
NoARMX  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_X) > 0

        GBLL    SupportARMJ
SupportARMJ SETL   (MchFlgs_Cumulative :AND: MchFlg_J) > 0
        GBLL    NoARMJ
NoARMJ  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_J) > 0

        GBLL    SupportARMK
SupportARMK SETL   (MchFlgs_Cumulative :AND: MchFlg_K) > 0
        GBLL    NoARMK
NoARMK  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_K) > 0

        GBLL    SupportARMT2
SupportARMT2 SETL  (MchFlgs_Cumulative :AND: MchFlg_T2) > 0
        GBLL    NoARMT2
NoARMT2 SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_T2) > 0

478 479 480 481 482 483 484 485 486 487
        GBLL    SupportARMVE
SupportARMVE SETL  (MchFlgs_Cumulative :AND: MchFlg_VE) > 0
        GBLL    NoARMVE
NoARMVE SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_VE) > 0

        GBLL    SupportARMC
SupportARMC SETL   (MchFlgs_Cumulative :AND: MchFlg_C) > 0
        GBLL    NoARMC
NoARMC  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_C) > 0

488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507
        GBLL    SupportARMV
SupportARMV SETL   (MchFlgs_Cumulative :AND: MchFlg_V) > 0
        GBLL    NoARMV
NoARMV  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_V) > 0

        GBLL    SupportARMVD
SupportARMVD SETL  (MchFlgs_Cumulative :AND: MchFlg_VD) > 0
        GBLL    NoARMVD
NoARMVD SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_VD) > 0

        GBLL    SupportARMV32
SupportARMV32 SETL (MchFlgs_Cumulative :AND: MchFlg_V32) > 0
        GBLL    NoARMV32
NoARMV32 SETL   (MchFlgs_CumulativeNOT :AND: MchFlg_V32) > 0

        GBLL    SupportARMVH
SupportARMVH SETL  (MchFlgs_Cumulative :AND: MchFlg_VH) > 0
        GBLL    NoARMVH
NoARMVH SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_VH) > 0

Ben Avison's avatar
Ben Avison committed
508
        GBLL    SupportARMVv4
509
SupportARMVv4 SETL  (MchFlgs_Cumulative :AND: MchFlg_Vv4) > 0
Ben Avison's avatar
Ben Avison committed
510
        GBLL    NoARMVv4
511
NoARMVv4 SETL   (MchFlgs_CumulativeNOT :AND: MchFlg_Vv4) > 0
Ben Avison's avatar
Ben Avison committed
512

513 514 515 516 517 518 519
        GBLL    SupportARMA
SupportARMA SETL   (MchFlgs_Cumulative :AND: MchFlg_A) > 0
        GBLL    NoARMA
NoARMA  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_A) > 0

 ]

520
        OPT     OldOpt
521
        END