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Commit 3adaec45 authored by Kevin Bracey's avatar Kevin Bracey
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Only wrap addresses in 64M space for branch disassembly and use of lr and pc in *Commands.

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Version
View file @ 3adaec45
SUBT > <wini>arm.Debugger.Version
GBLS Version
Version SETS "1.54"
Version SETS "1.55"
GBLS CurrentDate
CurrentDate SETS "27 Mar 1998"
CurrentDate SETS "08 May 1998"
END
s/Debugger
View file @ 3adaec45
......@@ -19,8 +19,8 @@
; Stuart K. Swales (Arthur fixes/enhancements)
; Tim Dobson (Adjusting headers, ARM600 variant)
; Alan Glover (fixes/enhancements, ARM6/ARM7 instructions)
; William Turner (StrongARM compatibility)
; Kevin Bracey (Architecture 4 instructions, fixes)
; William Turner (StrongARM compatibility)
; Kevin Bracey (Architecture 4 instructions, fixes)
; 1.18 SKS Fixed disassembly of #xx,yy operands
; 1.19 SKS Fixed disassembly of LSR #32, ASR #32
......@@ -136,28 +136,28 @@
; 1.46 WT 07-Feb-96 Made StrongARM compatible (breakpoint code breaks IDcache)
; 1.48 KJB 04-Jun-96 Added ARMv4 instructions (BX, LDR[H|SH|SB], STRH)
; SWP wasn't being disassembled
; CP15 comments amended to ARMv4
; ARM3 warning removed from SWP (after all, MRS,
; MULL etc don't have warnings!)
; CP15 comments amended to ARMv4
; ARM3 warning removed from SWP (after all, MRS,
; MULL etc don't have warnings!)
; ---- Released for RISC OS 3.70 ----
; 1.49 KJB 07-Oct-96 Operation code of MRC, MCR was shown times 2.
; FLT was showing wrong dest reg, with registers
; shown in wrong order.
; WFC etc were showing precision.
; Unknown FP opcodes now shown as normal coprocessor
; operations.
; LDC/STC (and FP derivatives) didn't detect
; post-indexing with no writeback. Now reported as
; undefined instructions.
; UMULLEQS no longer pushes registers into the
; comment field.
; MSR/MRS now specified as described in ARM
; Architecture Reference 4.
; FLT was showing wrong dest reg, with registers
; shown in wrong order.
; WFC etc were showing precision.
; Unknown FP opcodes now shown as normal coprocessor
; operations.
; LDC/STC (and FP derivatives) didn't detect
; post-indexing with no writeback. Now reported as
; undefined instructions.
; UMULLEQS no longer pushes registers into the
; comment field.
; MSR/MRS now specified as described in ARM
; Architecture Reference 4.
; 1.50 KJB 10-Oct-96 Lots of warnings added.
; More FP opcodes tightened up.
; PC-relative load/store with writeback no longer
; More FP opcodes tightened up.
; PC-relative load/store with writeback no longer
; shown as simple ADR.
; Thumb disassembly added.
; 1.51 KJB 29-Oct-96 Bugs introduced by 1.49 and 1.50 fixed.
......@@ -171,6 +171,10 @@
; Set Addr26 to True.
; 1.54 KJB 27-Mar-98 Test for post-indexed LDRH etc with W set didn't work.
; Service call table added.
; 1.55 KJB 08-May-98 Made Addr26 flag only affect disassembly of BL
; and use of lr and pc. Addresses are not wrapped
; to 64M. This makes sense for our 32-bit ARM in 26-bit
; mode.
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
GET Hdr:ListOpts
......@@ -2395,37 +2399,21 @@ MemoryI_Code ENTRY "r6-r11"
ADDEQ r7, r9, #4*24
[ Thumb
TEQ r6, #4
TEQ r6, #4
[ Addr26
BICEQ r9, r9, #ARM_CC_Mask ; Ensure in 64M space
BICEQ r7, r7, #ARM_CC_Mask
BICNE r9, r9, #1 ; ensure halfword aligned
BICNE r7, r7, #1
|
BICEQ r9, r9, #3 ; ensure word aligned
BICEQ r7, r7, #3
BICNE r9, r9, #1 ; ensure halfword aligned
BICNE r7, r7, #1
]
|
[ Addr26
BIC r9, r9, #ARM_CC_Mask ; Ensure in 64M space
BIC r7, r7, #ARM_CC_Mask
|
BIC r9, r9, #3 ; ensure word aligned
BIC r7, r7, #3
]
]
TEQS r9, r7 ; If same, ensure we do one word
BNE %FT05
BNE %FT05
ADD r7, r7, r6
[ Addr26
TEQ r6, #4
BICEQ r7, r7, #ARM_CC_Mask ; Ensure still in 64M space
]
ADD r7, r7, r6
05
[ rp0512
......@@ -2494,9 +2482,6 @@ MemoryI_Code ENTRY "r6-r11"
|
ADD r9, r9, #4
]
[ Addr26
BIC r9, r9, #&FC000000 ; Wrap within 64M
]
TEQS r9, r7
BNE %BT10
......@@ -2684,7 +2669,7 @@ Memory_Error
Memory_Code ENTRY "r6-r11"
[ Thumb
MOV R6,#"B"
MOV R6,#"B"
]
BL MemoryCommon
......@@ -2696,20 +2681,12 @@ Memory_Code ENTRY "r6-r11"
TST r8, #secondparm
ADDEQ r7, r9, #256 ; [no second parameter]
[ Addr26
BIC r9, r9, #&FC000000 ; Ensure in 64M space
BIC r7, r7, #&FC000000
]
TEQS r6, #4 ; Round down if words
BICEQ r9, r9, #3
BICEQ r7, r7, #3
TEQS r7, r9 ; If same, ensure we do one byte/word
ADDEQ r7, r7, r6
[ Addr26
BICEQ r7, r7, #&FC000000 ; Ensure still in 64M space
]
[ rp0512
BL memorytest
......@@ -2754,9 +2731,6 @@ Memory_Code ENTRY "r6-r11"
MOV r0, r9
10
[ Addr26
BIC r0, r0, #&FC000000 ; Wrap to keep in 64M each loop
]
TEQS r6, #4 ; Need to size reset each loop
MOVEQ r2, #32-4 ; word
BEQ %FT20
......@@ -2984,9 +2958,6 @@ MemoryA_Code ENTRY "r6-r11"
TST r8, #&FF00 ; had operator ?
BNE %FT99 ; [not permitted here]
[ Addr26
BIC r9, r9, #&FC000000 ; Ensure in 64M space
]
TEQS r6, #4 ; round down if words
BICEQ r9, r9, #3
......@@ -3068,9 +3039,6 @@ Interactive ROUT
MOV r8, r6 ; 1 or 4, initial step +ve
10
[ Addr26
BIC r9, r9, #&FC000000 ; Wrap in 64M space
]
CMPS r8, #0
MOVGE r0, #"+"
MOVLT r0, #"-"
......@@ -3194,17 +3162,10 @@ BreakSet_Code ENTRY "r6-r11"
TST r8, #parmfollowed
BNE BreakSetError0
[ Addr26
BIC r7, r7, #ARM_CC_Mask ; Can only set at word address in 64M
CMP r7, #&02000000 ; Can only set in LogRam
BHS BreakSetError1
|
BIC r7, r7, #3 ; Can only set at word address
CMP r7, #&04000000 ; Can only set in bottom 64M (has to
; construct a branch)
BHS BreakSetError1
]
[ rp0512
MOV r9,r7
......@@ -3725,9 +3686,6 @@ DisplayHexHalfword ENTRY "r2"
DisplayCharacters ENTRY "r0, r2, r9"
10
[ Addr26
BIC r9, r9, #&FC000000 ; Wrap within 64M each loop
]
LDRB r0, [r9], #1
CMPS r0, #delete
CMPNES r0, #space-1
......
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