Commit 4a16579f authored by Robert Sprowson's avatar Robert Sprowson Committed by ROOL

MII function updates

These change the prototypes of the MII read/write functions, so that the MII headers are at the same revision as those used by EtherGENET.
if_cpsw.c: Updated to NetBSD's revision 1.24
miivar.h: Updated to NetBSD's revision 1.69
mii.h: Updated to NetBSD's revision 1.27
glue.c: Refactor to use new function prototypes
glue.h: Merge macro improvements from EtherGENET-0_02, remove one made redundant now

Version 0.05. Tagged as 'EtherCPSW-0_05'
parent 4418fa49
/* (0.04) /* (0.05)
* *
* This file is automatically maintained by srccommit, do not edit manually. * This file is automatically maintained by srccommit, do not edit manually.
* *
*/ */
#define Module_MajorVersion_CMHG 0.04 #define Module_MajorVersion_CMHG 0.05
#define Module_MinorVersion_CMHG #define Module_MinorVersion_CMHG
#define Module_Date_CMHG 02 Apr 2020 #define Module_Date_CMHG 18 May 2020
#define Module_MajorVersion "0.04" #define Module_MajorVersion "0.05"
#define Module_Version 4 #define Module_Version 5
#define Module_MinorVersion "" #define Module_MinorVersion ""
#define Module_Date "02 Apr 2020" #define Module_Date "18 May 2020"
#define Module_ApplicationDate "02-Apr-20" #define Module_ApplicationDate "18-May-20"
#define Module_ComponentName "EtherCPSW" #define Module_ComponentName "EtherCPSW"
#define Module_FullVersion "0.04" #define Module_FullVersion "0.05"
#define Module_HelpVersion "0.04 (02 Apr 2020)" #define Module_HelpVersion "0.05 (18 May 2020)"
#define Module_LibraryVersionInfo "0:4" #define Module_LibraryVersionInfo "0:5"
...@@ -76,9 +76,11 @@ void mii_attach(device_t parent, struct mii_data *mii, int capmask, ...@@ -76,9 +76,11 @@ void mii_attach(device_t parent, struct mii_data *mii, int capmask,
/* Scan for all possible PHYs */ /* Scan for all possible PHYs */
for (mac = 0, address = MII_NPHY - 1; address >= 0; address--) for (mac = 0, address = MII_NPHY - 1; address >= 0; address--)
{ {
id = mii->mii_readreg(self, address, MII_PHYIDR1) | uint16_t *half = (uint16_t *)&id;
(mii->mii_readreg(self, address, MII_PHYIDR2) << 16);
if (id != 0) if ((mii->mii_readreg(self, address, MII_PHYIDR1, &half[0]) == 0) &&
(mii->mii_readreg(self, address, MII_PHYIDR2, &half[1]) == 0) &&
(id != 0uL))
{ {
if (mac < CPSW_ETH_PORTS) if (mac < CPSW_ETH_PORTS)
{ {
...@@ -153,8 +155,8 @@ int mii_mediachg(struct mii_data *mii) ...@@ -153,8 +155,8 @@ int mii_mediachg(struct mii_data *mii)
/* Everyone loves flashy lights, force single LED mode */ /* Everyone loves flashy lights, force single LED mode */
mii->mii_writereg(self, mii->mii_ifp->mac[i].phy_address, MII_MMDACR, MMDACR_FN_ADDRESS | MII_MMDCCD); mii->mii_writereg(self, mii->mii_ifp->mac[i].phy_address, MII_MMDACR, MMDACR_FN_ADDRESS | MII_MMDCCD);
mii->mii_writereg(self, mii->mii_ifp->mac[i].phy_address, MII_MMDAADR, MII_MMDCCA); mii->mii_writereg(self, mii->mii_ifp->mac[i].phy_address, MII_MMDAADR, MII_MMDCCA);
mii->mii_writereg(self, mii->mii_ifp->mac[i].phy_address, MII_MMDACR, MMDACR_FN_DATANPI | MII_MMDCCD); mii->mii_writereg(self, mii->mii_ifp->mac[i].phy_address, MII_MMDACR, MMDACR_FN_DATA | MII_MMDCCD);
reg = mii->mii_readreg(self, mii->mii_ifp->mac[i].phy_address, MII_MMDAADR); mii->mii_readreg(self, mii->mii_ifp->mac[i].phy_address, MII_MMDAADR, &reg);
mii->mii_writereg(self, mii->mii_ifp->mac[i].phy_address, MII_MMDAADR, reg | MMDCC_LEDOVRD); mii->mii_writereg(self, mii->mii_ifp->mac[i].phy_address, MII_MMDAADR, reg | MMDCC_LEDOVRD);
} }
...@@ -183,7 +185,11 @@ void mii_tick(struct mii_data *mii) ...@@ -183,7 +185,11 @@ void mii_tick(struct mii_data *mii)
for (i = 0; i < CPSW_ETH_PORTS; i++) for (i = 0; i < CPSW_ETH_PORTS; i++)
{ {
if (ifp->mac[i].phy_address == -1) continue; if (ifp->mac[i].phy_address == -1) continue;
reg = mii->mii_readreg(self, ifp->mac[i].phy_address, MII_VSPHYST); if (mii->mii_readreg(self, ifp->mac[i].phy_address, MII_VSPHYST, &reg) != 0)
{
/* Can't contact the PHY */
reg = 0;
}
if ((reg & (PHYST_SPD10 | PHYST_SPD100 | PHYST_SPD1000)) == 0) if ((reg & (PHYST_SPD10 | PHYST_SPD100 | PHYST_SPD1000)) == 0)
{ {
/* Link fail bit never seems to set even when cable unplugged, /* Link fail bit never seems to set even when cable unplugged,
......
/* $NetBSD: if_cpsw.c,v 1.21 2018/06/26 06:47:57 msaitoh Exp $ */ /* $NetBSD: if_cpsw.c,v 1.24 2019/05/29 05:05:24 msaitoh Exp $ */
/* /*
* Copyright (c) 2013 Jonathan A. Kollasch * Copyright (c) 2013 Jonathan A. Kollasch
...@@ -80,7 +80,7 @@ ...@@ -80,7 +80,7 @@
#include "if_cpswreg.h" #include "if_cpswreg.h"
#else #else
#include <sys/cdefs.h> #include <sys/cdefs.h>
__KERNEL_RCSID(1, "$NetBSD: if_cpsw.c,v 1.21 2018/06/26 06:47:57 msaitoh Exp $"); __KERNEL_RCSID(1, "$NetBSD: if_cpsw.c,v 1.24 2019/05/29 05:05:24 msaitoh Exp $");
#include <sys/param.h> #include <sys/param.h>
#include <sys/bus.h> #include <sys/bus.h>
...@@ -106,8 +106,6 @@ __KERNEL_RCSID(1, "$NetBSD: if_cpsw.c,v 1.21 2018/06/26 06:47:57 msaitoh Exp $") ...@@ -106,8 +106,6 @@ __KERNEL_RCSID(1, "$NetBSD: if_cpsw.c,v 1.21 2018/06/26 06:47:57 msaitoh Exp $")
#include <arch/arm/omap/sitara_cm.h> #include <arch/arm/omap/sitara_cm.h>
#endif #endif
#define ETHER_ALIGN (roundup2(ETHER_HDR_LEN, sizeof(uint32_t)) - ETHER_HDR_LEN)
#define CPSW_TXFRAGS 16 #define CPSW_TXFRAGS 16
#ifdef RISCOS #ifdef RISCOS
...@@ -189,8 +187,8 @@ static void cpsw_watchdog(struct ifnet *); ...@@ -189,8 +187,8 @@ static void cpsw_watchdog(struct ifnet *);
static int cpsw_init(struct ifnet *); static int cpsw_init(struct ifnet *);
static void cpsw_stop(struct ifnet *, int); static void cpsw_stop(struct ifnet *, int);
static int cpsw_mii_readreg(device_t, int, int); static int cpsw_mii_readreg(device_t, int, int, uint16_t *);
static void cpsw_mii_writereg(device_t, int, int, int); static int cpsw_mii_writereg(device_t, int, int, uint16_t);
static void cpsw_mii_statchg(struct ifnet *); static void cpsw_mii_statchg(struct ifnet *);
static int cpsw_new_rxbuf(struct cpsw_softc * const, const u_int); static int cpsw_new_rxbuf(struct cpsw_softc * const, const u_int);
...@@ -865,29 +863,31 @@ cpsw_mii_wait(struct cpsw_softc * const sc, int reg) ...@@ -865,29 +863,31 @@ cpsw_mii_wait(struct cpsw_softc * const sc, int reg)
} }
static int static int
cpsw_mii_readreg(device_t dev, int phy, int reg) cpsw_mii_readreg(device_t dev, int phy, int reg, uint16_t *val)
{ {
struct cpsw_softc * const sc = device_private(dev); struct cpsw_softc * const sc = device_private(dev);
uint32_t v; uint32_t v;
if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0) if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0)
return 0; return -1;
cpsw_write_4(sc, MDIOUSERACCESS0, (1 << 31) | cpsw_write_4(sc, MDIOUSERACCESS0, (1 << 31) |
((reg & 0x1F) << 21) | ((phy & 0x1F) << 16)); ((reg & 0x1F) << 21) | ((phy & 0x1F) << 16));
if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0) if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0)
return 0; return -1;
v = cpsw_read_4(sc, MDIOUSERACCESS0); v = cpsw_read_4(sc, MDIOUSERACCESS0);
if (v & __BIT(29)) if (v & __BIT(29)) {
return v & 0xffff; *val = v & 0xffff;
else
return 0; return 0;
}
return -1;
} }
static void static int
cpsw_mii_writereg(device_t dev, int phy, int reg, int val) cpsw_mii_writereg(device_t dev, int phy, int reg, uint16_t val)
{ {
struct cpsw_softc * const sc = device_private(dev); struct cpsw_softc * const sc = device_private(dev);
uint32_t v; uint32_t v;
...@@ -904,10 +904,13 @@ cpsw_mii_writereg(device_t dev, int phy, int reg, int val) ...@@ -904,10 +904,13 @@ cpsw_mii_writereg(device_t dev, int phy, int reg, int val)
goto out; goto out;
v = cpsw_read_4(sc, MDIOUSERACCESS0); v = cpsw_read_4(sc, MDIOUSERACCESS0);
if ((v & __BIT(29)) == 0) if ((v & __BIT(29)) == 0) {
out: out:
device_printf(sc->sc_dev, "%s error\n", __func__); device_printf(sc->sc_dev, "%s error\n", __func__);
return -1;
}
return 0;
} }
static void static void
...@@ -991,11 +994,13 @@ cpsw_init(struct ifnet *ifp) ...@@ -991,11 +994,13 @@ cpsw_init(struct ifnet *ifp)
/* Reset wrapper */ /* Reset wrapper */
cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1); cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1);
while(cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1); while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1)
;
/* Reset SS */ /* Reset SS */
cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1); cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1);
while(cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1); while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1)
;
/* Clear table and enable ALE */ /* Clear table and enable ALE */
cpsw_write_4(sc, CPSW_ALE_CONTROL, cpsw_write_4(sc, CPSW_ALE_CONTROL,
...@@ -1007,7 +1012,8 @@ cpsw_init(struct ifnet *ifp) ...@@ -1007,7 +1012,8 @@ cpsw_init(struct ifnet *ifp)
/* Reset */ /* Reset */
cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1); cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1);
while(cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1); while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1)
;
/* Set Slave Mapping */ /* Set Slave Mapping */
cpsw_write_4(sc, CPSW_SL_RX_PRI_MAP(i), 0x76543210); cpsw_write_4(sc, CPSW_SL_RX_PRI_MAP(i), 0x76543210);
cpsw_write_4(sc, CPSW_PORT_P_TX_PRI_MAP(i+1), 0x33221100); cpsw_write_4(sc, CPSW_PORT_P_TX_PRI_MAP(i+1), 0x33221100);
...@@ -1055,7 +1061,8 @@ cpsw_init(struct ifnet *ifp) ...@@ -1055,7 +1061,8 @@ cpsw_init(struct ifnet *ifp)
cpsw_write_4(sc, CPSW_SS_STAT_PORT_EN, 7); cpsw_write_4(sc, CPSW_SS_STAT_PORT_EN, 7);
cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1); cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1);
while(cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1); while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1)
;
for (i = 0; i < 8; i++) { for (i = 0; i < 8; i++) {
cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(i), 0); cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(i), 0);
...@@ -1179,20 +1186,24 @@ cpsw_stop(struct ifnet *ifp, int disable) ...@@ -1179,20 +1186,24 @@ cpsw_stop(struct ifnet *ifp, int disable)
/* Reset wrapper */ /* Reset wrapper */
cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1); cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1);
while(cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1); while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1)
;
/* Reset SS */ /* Reset SS */
cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1); cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1);
while(cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1); while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1)
;
for (i = 0; i < CPSW_ETH_PORTS; i++) { for (i = 0; i < CPSW_ETH_PORTS; i++) {
cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1); cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1);
while(cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1); while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1)
;
} }
/* Reset CPDMA */ /* Reset CPDMA */
cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1); cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1);
while(cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1); while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1)
;
/* Release any queued transmit buffers. */ /* Release any queued transmit buffers. */
for (i = 0; i < CPSW_NTXDESCS; i++) { for (i = 0; i < CPSW_NTXDESCS; i++) {
......
...@@ -114,17 +114,17 @@ struct ethercom ...@@ -114,17 +114,17 @@ struct ethercom
#define IFQ_POLL(q,v) do { v = *(q); } while (0); #define IFQ_POLL(q,v) do { v = *(q); } while (0);
#define m_length(m) (MBCTL.count_bytes)(&MBCTL,(m)) #define m_length(m) (MBCTL.count_bytes)(&MBCTL,(m))
#define powerof2(x) ((((x)-1)&(x))==0) #define powerof2(x) ((((x)-1)&(x))==0)
#define roundup2(v,r) (((v)+((r)-1)) & ~((r)-1))
#define CTASSERT(e) CTASSERT0(e, __LINE__) #define CTASSERT(e) CTASSERT0(e, __LINE__)
#define CTASSERT0(e,n) CTASSERT1(e,n) #define CTASSERT0(e,n) CTASSERT1(e,n)
#define CTASSERT1(e,n) typedef char _ct ## n[(e) ? 1 : -1] #define CTASSERT1(e,n) typedef char _ct ## n[(e) ? 1 : -1]
#define device_xname(k) "ecp" #define device_xname(k) "ecp"
#define strlcpy(d,s,x) strcpy(d,s) #define strlcpy(d,s,x) strcpy(d,s)
#define device_private(k) (struct cpsw_softc *)(k) #define device_private(k) (struct cpsw_softc *)(k)
#define device_parent(k) (device_t)(k)
#define MCLBYTES 4096 #define MCLBYTES 4096
#define hz 1 #define hz 1
#define ISSET(a,b) (((a) & (b)) ? 1 : 0) #define ISSET(a,b) (((a) & (b)) ? 1 : 0)
#define __BIT(k) (1u<<(k)) #define __BIT(k) ((k>=32) ? 0 : 1u<<((k)&31))
#define __BITS(hi,lo) ((__BIT((hi)+1)-1)^(__BIT((lo))-1)) #define __BITS(hi,lo) ((__BIT((hi)+1)-1)^(__BIT((lo))-1))
#define __SHIFTOUT(a,b) shiftout(a,b) #define __SHIFTOUT(a,b) shiftout(a,b)
#define ifmedia_init(a,b,c,d) (a)->ifm_cur = (a) #define ifmedia_init(a,b,c,d) (a)->ifm_cur = (a)
...@@ -138,6 +138,7 @@ struct ethercom ...@@ -138,6 +138,7 @@ struct ethercom
#define ether_ifdetach(a) /* Nothing */ #define ether_ifdetach(a) /* Nothing */
#define ether_sprintf(k) "Unused" #define ether_sprintf(k) "Unused"
#define ether_ioctl(a,b,c) (0 * (int)(b) * (int)(c)) #define ether_ioctl(a,b,c) (0 * (int)(b) * (int)(c))
#define ETHER_ALIGN 2
#define __predict_false(k) k #define __predict_false(k) k
#define __diagused /* Nothing */ #define __diagused /* Nothing */
#define __arraycount(a) (sizeof((a))/sizeof((a[0]))) #define __arraycount(a) (sizeof((a))/sizeof((a[0])))
......
/* $NetBSD: mii.h,v 1.17 2013/06/16 06:29:08 msaitoh Exp $ */ /* $NetBSD: mii.h,v 1.27 2019/04/11 09:14:07 msaitoh Exp $ */
/* /*
* Copyright (c) 1997 Manuel Bouyer. All rights reserved. * Copyright (c) 1997 Manuel Bouyer. All rights reserved.
...@@ -35,6 +35,8 @@ ...@@ -35,6 +35,8 @@
*/ */
#define MII_NPHY 32 /* max # of PHYs per MII */ #define MII_NPHY 32 /* max # of PHYs per MII */
#define MII_ADDRBITS 5 /* Register address bits (0x00..0x1f) */
#define MII_ADDRMASK 0x1f /* Address mask */
/* /*
* MII commands, used if a device must drive the MII lines * MII commands, used if a device must drive the MII lines
...@@ -45,7 +47,7 @@ ...@@ -45,7 +47,7 @@
#define MII_COMMAND_WRITE 0x01 #define MII_COMMAND_WRITE 0x01
#define MII_COMMAND_ACK 0x02 #define MII_COMMAND_ACK 0x02
#define MII_BMCR 0x00 /* Basic mode control register (rw) */ #define MII_BMCR 0x00 /* Basic mode control register (rw) */
#define BMCR_RESET 0x8000 /* reset */ #define BMCR_RESET 0x8000 /* reset */
#define BMCR_LOOP 0x4000 /* loopback */ #define BMCR_LOOP 0x4000 /* loopback */
#define BMCR_SPEED0 0x2000 /* speed selection (LSB) */ #define BMCR_SPEED0 0x2000 /* speed selection (LSB) */
...@@ -56,12 +58,13 @@ ...@@ -56,12 +58,13 @@
#define BMCR_FDX 0x0100 /* Set duplex mode */ #define BMCR_FDX 0x0100 /* Set duplex mode */
#define BMCR_CTEST 0x0080 /* collision test */ #define BMCR_CTEST 0x0080 /* collision test */
#define BMCR_SPEED1 0x0040 /* speed selection (MSB) */ #define BMCR_SPEED1 0x0040 /* speed selection (MSB) */
#define BMCR_UNIDIR 0x0020 /* Unidirectional enable */
#define BMCR_S10 0x0000 /* 10 Mb/s */ #define BMCR_S10 0x0000 /* 10 Mb/s */
#define BMCR_S100 BMCR_SPEED0 /* 100 Mb/s */ #define BMCR_S100 BMCR_SPEED0 /* 100 Mb/s */
#define BMCR_S1000 BMCR_SPEED1 /* 1000 Mb/s */ #define BMCR_S1000 BMCR_SPEED1 /* 1000 Mb/s */
#define BMCR_SPEED(x) ((x) & (BMCR_SPEED0|BMCR_SPEED1)) #define BMCR_SPEED(x) ((x) & (BMCR_SPEED0 | BMCR_SPEED1))
#define MII_BMSR 0x01 /* Basic mode status register (ro) */ #define MII_BMSR 0x01 /* Basic mode status register (ro) */
#define BMSR_100T4 0x8000 /* 100 base T4 capable */ #define BMSR_100T4 0x8000 /* 100 base T4 capable */
...@@ -72,6 +75,7 @@ ...@@ -72,6 +75,7 @@
#define BMSR_100T2FDX 0x0400 /* 100 base T2 full duplex capable */ #define BMSR_100T2FDX 0x0400 /* 100 base T2 full duplex capable */
#define BMSR_100T2HDX 0x0200 /* 100 base T2 half duplex capable */ #define BMSR_100T2HDX 0x0200 /* 100 base T2 half duplex capable */
#define BMSR_EXTSTAT 0x0100 /* Extended status in register 15 */ #define BMSR_EXTSTAT 0x0100 /* Extended status in register 15 */
#define BMSR_UNIDIR 0x0080 /* Unidirectional ability */
#define BMSR_MFPS 0x0040 /* MII Frame Preamble Suppression */ #define BMSR_MFPS 0x0040 /* MII Frame Preamble Suppression */
#define BMSR_ACOMP 0x0020 /* Autonegotiation complete */ #define BMSR_ACOMP 0x0020 /* Autonegotiation complete */
#define BMSR_RFAULT 0x0010 /* Link partner fault */ #define BMSR_RFAULT 0x0010 /* Link partner fault */
...@@ -83,11 +87,11 @@ ...@@ -83,11 +87,11 @@
/* /*
* Note that the EXTSTAT bit indicates that there is extended status * Note that the EXTSTAT bit indicates that there is extended status
* info available in register 15, but 802.3 section 22.2.4.3 also * info available in register 15, but 802.3 section 22.2.4.3 also
* states that that all 1000 Mb/s capable PHYs will set this bit to 1. * states that all 1000 Mb/s capable PHYs will set this bit to 1.
*/ */
#define BMSR_MEDIAMASK (BMSR_100T4|BMSR_100TXFDX|BMSR_100TXHDX| \ #define BMSR_MEDIAMASK (BMSR_100T4 | BMSR_100TXFDX | BMSR_100TXHDX | \
BMSR_10TFDX|BMSR_10THDX|BMSR_100T2FDX|BMSR_100T2HDX) BMSR_10TFDX | BMSR_10THDX | BMSR_100T2FDX | BMSR_100T2HDX)
/* /*
* Convert BMSR media capabilities to ANAR bits for autonegotiation. * Convert BMSR media capabilities to ANAR bits for autonegotiation.
...@@ -107,6 +111,7 @@ ...@@ -107,6 +111,7 @@
#define ANAR_NP 0x8000 /* Next page (ro) */ #define ANAR_NP 0x8000 /* Next page (ro) */
#define ANAR_ACK 0x4000 /* link partner abilities acknowledged (ro) */ #define ANAR_ACK 0x4000 /* link partner abilities acknowledged (ro) */
#define ANAR_RF 0x2000 /* remote fault (ro) */ #define ANAR_RF 0x2000 /* remote fault (ro) */
#define ANAR_XNP 0x1000 /* Extended Next Page */
/* Annex 28B.2 */ /* Annex 28B.2 */
#define ANAR_FC 0x0400 /* local device supports PAUSE */ #define ANAR_FC 0x0400 /* local device supports PAUSE */
#define ANAR_T4 0x0200 /* local device supports 100bT4 */ #define ANAR_T4 0x0200 /* local device supports 100bT4 */
...@@ -127,12 +132,21 @@ ...@@ -127,12 +132,21 @@
#define ANAR_X_PAUSE_SYM (1 << 7) #define ANAR_X_PAUSE_SYM (1 << 7)
#define ANAR_X_PAUSE_ASYM (2 << 7) #define ANAR_X_PAUSE_ASYM (2 << 7)
#define ANAR_X_PAUSE_TOWARDS (3 << 7) #define ANAR_X_PAUSE_TOWARDS (3 << 7)
/* 37.2.1.5 Remore Fault */
#define ANAR_X_RF1 0x1000
#define ANAR_X_RF2 0x2000
#define ANAR_X_RF_MASK (ANAR_X_RF1 | ANAR_X_RF2)
#define ANAR_X_RF_NONE (0 << 12)
#define ANAR_X_RF_OFFLINE (1 << 12)
#define ANAR_X_RF_LINKFAIL (2 << 12)
#define ANAR_X_RF_ANEGERR (3 << 12)
#define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */ #define MII_ANLPAR 0x05 /* ANEG Link Partner Base Page abilities (rw)*/
/* section 28.2.4.1 and 37.2.6.1 */ /* section 28.2.4.1 and 37.2.6.1 */
#define ANLPAR_NP 0x8000 /* Next page (ro) */ #define ANLPAR_NP 0x8000 /* Next page (ro) */
#define ANLPAR_ACK 0x4000 /* link partner accepted ACK (ro) */ #define ANLPAR_ACK 0x4000 /* link partner accepted ACK (ro) */
#define ANLPAR_RF 0x2000 /* remote fault (ro) */ #define ANLPAR_RF 0x2000 /* remote fault (ro) */
#define ANLPAR_XNP 0x1000 /* Extended Next Page */
#define ANLPAR_FC 0x0400 /* link partner supports PAUSE */ #define ANLPAR_FC 0x0400 /* link partner supports PAUSE */
#define ANLPAR_T4 0x0200 /* link partner supports 100bT4 */ #define ANLPAR_T4 0x0200 /* link partner supports 100bT4 */
#define ANLPAR_TX_FD 0x0100 /* link partner supports 100bTx FD */ #define ANLPAR_TX_FD 0x0100 /* link partner supports 100bTx FD */
...@@ -153,23 +167,61 @@ ...@@ -153,23 +167,61 @@
#define ANLPAR_X_PAUSE_SYM (1 << 7) #define ANLPAR_X_PAUSE_SYM (1 << 7)
#define ANLPAR_X_PAUSE_ASYM (2 << 7) #define ANLPAR_X_PAUSE_ASYM (2 << 7)
#define ANLPAR_X_PAUSE_TOWARDS (3 << 7) #define ANLPAR_X_PAUSE_TOWARDS (3 << 7)
/* 37.2.1.5 Remore Fault */
#define ANLPAR_X_RF1 0x1000
#define ANLPAR_X_RF2 0x2000
#define ANLPAR_X_RF_MASK (ANLPAR_X_RF1 | ANLPAR_X_RF2)
#define ANLPAR_X_RF_NONE (0 << 12)
#define ANLPAR_X_RF_OFFLINE (1 << 12)
#define ANLPAR_X_RF_LINKFAIL (2 << 12)
#define ANLPAR_X_RF_ANEGERR (3 << 12)
#define MII_ANER 0x06 /* Autonegotiation expansion (ro) */ #define MII_ANER 0x06 /* Autonegotiation expansion (ro) */
/* section 28.2.4.1 and 37.2.6.1 */ /* section 28.2.4.1 and 37.2.6.1 */
#define ANER_RNPLA 0x0040 /* Receive Next Page Location Able */
#define ANER_RNPSL 0x0020 /* Received Next Page Storage Location */
#define ANER_MLF 0x0010 /* multiple link detection fault */ #define ANER_MLF 0x0010 /* multiple link detection fault */
#define ANER_LPNP 0x0008 /* link parter next page-able */ #define ANER_LPNP 0x0008 /* link partner next page-able */
#define ANER_NP 0x0004 /* next page-able */ #define ANER_NP 0x0004 /* next page-able */
#define ANER_PAGE_RX 0x0002 /* Page received */ #define ANER_PAGE_RX 0x0002 /* Page received */
#define ANER_LPAN 0x0001 /* link parter autoneg-able */ #define ANER_LPAN 0x0001 /* link partner autoneg-able */
#define MII_ANNP 0x07 /* Autonegotiation next page */ #define MII_ANNPT 0x07 /* Autonegotiation next page transmit (rw) */
/* section 28.2.4.1 and 37.2.6.1 */ /* section 28.2.4.1 and 37.2.6.1 */
#define ANNPT_NP 0x8000 /* Next Page */
#define ANNPT_MP 0x2000 /* Message Page */
#define ANNPT_ACK2 0x1000 /* Acknowledge 2 */
#define ANNPT_TOGGLE 0x0800 /* Toggle */
#define ANNPT_MSGUNF_MASK 0x07ff /* Message(Annex28C)/Unformatted Code Field */
/* Next Page Message Code used in ANNPT and ANLPRNP */
#define ANNP_MSG_NULL 1 /* Null Message */
#define ANNP_MSG_1UP_TAF 2 /* 1Up w/ Tech. Ability Field follows */
#define ANNP_MSG_2UP_TAF 3 /* 2Up w/ Tech. Ability Field follows */
#define ANNP_MSG_1UP_BCRF 4 /* 1Up w/ Bin. coded Remote Flt follows */
#define ANNP_MSG_OUIDTMSG 5 /* OUI tagged Message */
#define ANNP_MSG_PHYIDTC 6 /* PHY Identifier Tag Code */
#define ANNP_MSG_TMC_100T2 7 /* 100BASE-T2 Tech. Message Code */
#define ANNP_MSG_TMC_1000T 8 /* 1000BASE-T Tech. Message Code */
#define ANNP_MSG_TMC_10G1G 9 /* 10GBASE-T/1000BASE-T TMC: (XNP) */
#define ANNP_MSG_TMC_EEE 10 /* EEE Technology Message Code */
#define ANNP_MSG_OUIDTM_XNP 11 /* OUI tagged Message (XNP) */
#define MII_ANLPRNP 0x08 /* Autonegotiation link partner rx next page */ #define MII_ANLPRNP 0x08 /* Autonegotiation link partner rx next page */
/* section 32.5.1 and 37.2.6.1 */ /* section 32.5.1 and 37.2.6.1 */
#define ANLPRNP_NP 0x8000 /* Next Page */
#define ANLPRNP_ACK 0x4000 /* Acknowledge */
#define ANLPRNP_MP 0x2000 /* Message Page */
#define ANLPRNP_ACK2 0x1000 /* Acknowledge 2 */
#define ANLPRNP_TOGGLE 0x0800 /* Toggle */
#define ANLPRNP_MSGUNF_MASK 0x07ff /* Message(Anx28C)/Unformatted Code Field */
/* This is also the 1000baseT control register */ #define MII_GTCR 0x09 /*
#define MII_100T2CR 0x09 /* 100base-T2 control register */ * Master-Slave control register for
* 100BASE-T2 and 1000BASE-T.
*/
#define MII_100T2CR MII_GTCR /* alias */
#define GTCR_TEST_MASK 0xe000 /* see 802.3ab ss. 40.6.1.1.2 */ #define GTCR_TEST_MASK 0xe000 /* see 802.3ab ss. 40.6.1.1.2 */
#define GTCR_MAN_MS 0x1000 /* enable manual master/slave control */ #define GTCR_MAN_MS 0x1000 /* enable manual master/slave control */
#define GTCR_ADV_MS 0x0800 /* 1 = adv. master, 0 = adv. slave */ #define GTCR_ADV_MS 0x0800 /* 1 = adv. master, 0 = adv. slave */
...@@ -177,49 +229,72 @@ ...@@ -177,49 +229,72 @@
#define GTCR_ADV_1000TFDX 0x0200 /* adv. 1000baseT FDX */ #define GTCR_ADV_1000TFDX 0x0200 /* adv. 1000baseT FDX */
#define GTCR_ADV_1000THDX 0x0100 /* adv. 1000baseT HDX */ #define GTCR_ADV_1000THDX 0x0100 /* adv. 1000baseT HDX */
/* This is also the 1000baseT status register */ #define T2CR_TEST_NORMAL (0 << 13) /* Normal Operation */
#define MII_100T2SR 0x0a /* 100base-T2 status register */ #define T2CR_TEST_RX (1 << 13) /* RX test */
#define T2CR_TEST_TX_WAVEFORM (1 << 14) /* Mode 1. TX waveform test */
#define T2CR_TEST_TX_JITTER (2 << 14) /* Mode 2. TX jitter test */
#define T2CR_TEST_TX_IDLE (3 << 14) /* Mode 3. TX idle test */
#define GTCR_TEST_NORMAL (0 << 13) /* Normal Operation */
#define GTCR_TEST_TX_WAVEFORM (1 << 13) /* Mode 1. TX waveform test */
#define GTCR_TEST_TX_JITTER_M (2 << 13) /* Mode 2. TX jitter test (Master) */
#define GTCR_TEST_TX_JITTER_S (3 << 13) /* Mode 3. TX jitter test (Slave) */
#define GTCR_TEST_TX_DISTORTION (4 << 13) /* Mode 4. TX distortion test */
#define MII_GTSR 0x0a /*
* Master-Slave status register for
* 100BASE-T2 and 1000BASE-T.
*/
#define MII_100T2SR MII_GTSR /* alias */
#define GTSR_MAN_MS_FLT 0x8000 /* master/slave config fault */ #define GTSR_MAN_MS_FLT 0x8000 /* master/slave config fault */
#define GTSR_MS_RES 0x4000 /* result: 1 = master, 0 = slave */ #define GTSR_MS_RES 0x4000 /* result: 1 = master, 0 = slave */
#define GTSR_LRS 0x2000 /* local rx status, 1 = ok */ #define GTSR_LRS 0x2000 /* local rx status, 1 = ok */
#define GTSR_RRS 0x1000 /* remote rx status, 1 = ok */ #define GTSR_RRS 0x1000 /* remote rx status, 1 = ok */
#define GTSR_LP_1000TFDX 0x0800 /* link partner 1000baseT FDX capable */ #define GTSR_LP_1000TFDX 0x0800 /* link partner 1000baseT FDX capable */
#define GTSR_LP_1000THDX 0x0400 /* link partner 1000baseT HDX capable */ #define GTSR_LP_1000THDX 0x0400 /* link partner 1000baseT HDX capable */
#define GTSR_LP_ASM_DIR 0x0200 /* link partner asym. pause dir. capable */
#define GTSR_IDLE_ERR 0x00ff /* IDLE error count */ #define GTSR_IDLE_ERR 0x00ff /* IDLE error count */
#define MII_PSECR 0x0b /* PSE control register */ #define MII_PSECR 0x0b /* PSE control register */
#define PSECR_DLLC 0x0020 /* Data Link Layer Classification capability */
#define PSECR_EPLC 0x0010 /* Enable Physical Layer Classification */
#define PSECR_PACTLMASK 0x000c /* pair control mask */ #define PSECR_PACTLMASK 0x000c /* pair control mask */
#define PSECR_PSEENMASK 0x0003 /* PSE enable mask */
#define PSECR_PINOUTB 0x0008 /* PSE pinout Alternative B */ #define PSECR_PINOUTB 0x0008 /* PSE pinout Alternative B */
#define PSECR_PINOUTA 0x0004 /* PSE pinout Alternative A */ #define PSECR_PINOUTA 0x0004 /* PSE pinout Alternative A */
#define PSECR_PSEENMASK 0x0003 /* PSE enable mask */
#define PSECR_FOPOWTST 0x0002 /* Force Power Test Mode */ #define PSECR_FOPOWTST 0x0002 /* Force Power Test Mode */
#define PSECR_PSEEN 0x0001 /* PSE Enabled */ #define PSECR_PSEEN 0x0001 /* PSE Enabled */
#define PSECR_PSEDIS 0x0000 /* PSE Disabled */ #define PSECR_PSEDIS 0x0000 /* PSE Disabled */
#define MII_PSESR 0x0c /* PSE status register */ #define MII_PSESR 0x0c /* PSE status register */
#define PSESR_PWRDENIED 0x1000 /* Power Deined */ #define PSESR_PWRDENIED 0x1000 /* Power Denied */
#define PSESR_VALSIG 0x0800 /* Valid PD signature detected */ #define PSESR_VALSIG 0x0800 /* Valid PD signature detected */
#define PSESR_INVALSIG 0x0400 /* Inalid PD signature detected */ #define PSESR_INVALSIG 0x0400 /* Invalid PD signature detected */
#define PSESR_SHORTCIRC 0x0200 /* Short circuit condition detected */ #define PSESR_SHORTCIRC 0x0200 /* Short circuit condition detected */
#define PSESR_OVERLOAD 0x0100 /* Overload condition detected */ #define PSESR_OVERLOAD 0x0100 /* Overload condition detected */
#define PSESR_MPSABSENT 0x0080 /* MPS absent condition detected */ #define PSESR_MPSABSENT 0x0080 /* MPS absent condition detected */
#define PSESR_PDCLMASK 0x0070 /* PD Class mask */ #define PSESR_PDCLMASK 0x0070 /* PD Class mask */
#define PSESR_STATMASK 0x000e /* PSE Status mask */ #define PSESR_STATMASK 0x000e /* PSE Status mask */
#define PSESR_PAIRCTABL 0x0001 /* PAIR Control Ability */ #define PSESR_PAIRCTABL 0x0001 /* PAIR Control Ability */
#define PSESR_PDCL_INVALID (5 << 4) /* Invalid Class */
#define PSESR_PDCL_4 (4 << 4) /* Class 4 */ #define PSESR_PDCL_4 (4 << 4) /* Class 4 */
#define PSESR_PDCL_3 (3 << 4) /* Class 3 */ #define PSESR_PDCL_3 (3 << 4) /* Class 3 */
#define PSESR_PDCL_2 (2 << 4) /* Class 2 */ #define PSESR_PDCL_2 (2 << 4) /* Class 2 */
#define PSESR_PDCL_1 (1 << 4) /* Class 1 */ #define PSESR_PDCL_1 (1 << 4) /* Class 1 */
#define PSESR_PDCL_0 (0 << 4) /* Class 0 */ #define PSESR_PDCL_0 (0 << 4) /* Class 0 */
#define PSESR_STAT_ISFLT (5 << 1) /* Implement specific fault */
#define PSESR_STAT_TSTERR (4 << 1) /* Test Error */
#define PSESR_STAT_TSTMODE (3 << 1) /* Test Mode */
#define PSESR_STAT_DELVPWR (2 << 1) /* Delivering power */
#define PSESR_STAT_SEARCH (1 << 1) /* Searching */
#define PSESR_STAT_DIS (0 << 1) /* Disabled */
#define MII_MMDACR 0x0d /* MMD access control register */ #define MII_MMDACR 0x0d /* MMD access control register */
#define MMDACR_FUNCMASK 0xc000 /* function */ #define MMDACR_FUNCMASK 0xc000 /* function */
#define MMDACR_DADDRMASK 0x001f /* device address */ #define MMDACR_DADDRMASK 0x001f /* device address */
#define MMDACR_FN_ADDRESS (0 << 14) /* address */ #define MMDACR_FN_ADDRESS (0 << 14) /* address */
#define MMDACR_FN_DATANPI (1 << 14) /* data, no post increment */ #define MMDACR_FN_DATA (1 << 14) /* data, no post increment */
#define MMDACR_FN_DATAPIRW (2 << 14) /* data, post increment on r/w */ #define MMDACR_FN_DATA_INC_RW (2 << 14) /* data, post increment on r/w */
#define MMDACR_FN_DATAPIW (3 << 14) /* data, post increment on wr only */ #define MMDACR_FN_DATA_INC_W (3 << 14) /* data, post increment on wr only */
#define MII_MMDAADR 0x0e /* MMD access address data register */ #define MII_MMDAADR 0x0e /* MMD access address data register */
...@@ -229,7 +304,7 @@ ...@@ -229,7 +304,7 @@
#define EXTSR_1000TFDX 0x2000 /* 1000T full-duplex capable */ #define EXTSR_1000TFDX 0x2000 /* 1000T full-duplex capable */
#define EXTSR_1000THDX 0x1000 /* 1000T half-duplex capable */ #define EXTSR_1000THDX 0x1000 /* 1000T half-duplex capable */
#define EXTSR_MEDIAMASK (EXTSR_1000XFDX|EXTSR_1000XHDX| \ #define EXTSR_MEDIAMASK (EXTSR_1000XFDX | EXTSR_1000XHDX | \
EXTSR_1000TFDX|EXTSR_1000THDX) EXTSR_1000TFDX | EXTSR_1000THDX)
#endif /* _DEV_MII_MII_H_ */ #endif /* _DEV_MII_MII_H_ */
/* $NetBSD: miivar.h,v 1.61 2013/03/15 06:18:13 msaitoh Exp $ */ /* $NetBSD: miivar.h,v 1.69 2019/11/20 08:50:59 msaitoh Exp $ */
/*- /*-
* Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
...@@ -37,11 +37,12 @@ ...@@ -37,11 +37,12 @@
#include <sys/queue.h> #include <sys/queue.h>
#include <sys/callout.h> #include <sys/callout.h>
#include <dev/mii/mii.h>
#include <dev/mii/mii_verbose.h> #include <dev/mii/mii_verbose.h>
#endif #endif
/* /*
* Media Independent Interface datat structure definitions. * Media Independent Interface data structure definitions.
*/ */
struct ifnet; struct ifnet;
...@@ -50,8 +51,8 @@ struct mii_softc; ...@@ -50,8 +51,8 @@ struct mii_softc;
/* /*
* Callbacks from MII layer into network interface device driver. * Callbacks from MII layer into network interface device driver.
*/ */
typedef int (*mii_readreg_t)(device_t, int, int); typedef int (*mii_readreg_t)(device_t, int, int, uint16_t *);
typedef void (*mii_writereg_t)(device_t, int, int, int); typedef int (*mii_writereg_t)(device_t, int, int, uint16_t);
typedef void (*mii_statchg_t)(struct ifnet *); typedef void (*mii_statchg_t)(struct ifnet *);
/* /*
...@@ -73,15 +74,11 @@ struct mii_data { ...@@ -73,15 +74,11 @@ struct mii_data {
LIST_HEAD(mii_listhead, mii_softc) mii_phys; LIST_HEAD(mii_listhead, mii_softc) mii_phys;
u_int mii_instance; u_int mii_instance;
/* /* PHY driver fills this in with active media status. */
* PHY driver fills this in with active media status.
*/
int mii_media_status; int mii_media_status;
u_int mii_media_active; u_int mii_media_active;
/* /* Calls from MII layer into network interface driver. */
* Calls from MII layer into network interface driver.
*/
mii_readreg_t mii_readreg;