Commit eb3ebf01 authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Update atomic_process_smp to cope with the possibility of the process function...

Update atomic_process_smp to cope with the possibility of the process function altering the state of the exclusive monitor. Prefer CPS over MSR when performing PSR manipulation.

  s/atomic - Since the exclusive monitor can have its state affected by almost anything, atomic_process_smp can't assume that the state remains stable across the call to the user's process function. Instead we must perform our LDREX-STREX sequence after the callback, manually checking that the value being updated hasn't been altered by anyone else while the process function was executing.
  s/spin, s/spinrw - When disabling interrupts prefer CPS over MSR. Apart from making the sequences one instruction shorter, CPS generally delivers better performance than the equivalent MSR.
  Tested on Cortex-A15

Version 0.03. Tagged as 'SyncLib-0_03'
parent ebe048fb
/* (0.02)
/* (0.03)
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
#define Module_MajorVersion_CMHG 0.02
#define Module_MajorVersion_CMHG 0.03
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 29 Feb 2016
#define Module_Date_CMHG 08 May 2016
#define Module_MajorVersion "0.02"
#define Module_Version 2
#define Module_MajorVersion "0.03"
#define Module_Version 3
#define Module_MinorVersion ""
#define Module_Date "29 Feb 2016"
#define Module_Date "08 May 2016"
#define Module_ApplicationDate "29-Feb-16"
#define Module_ApplicationDate "08-May-16"
#define Module_ComponentName "SyncLib"
#define Module_ComponentPath "bsd/RiscOS/Sources/Lib/SyncLib"
#define Module_FullVersion "0.02"
#define Module_HelpVersion "0.02 (29 Feb 2016)"
#define Module_LibraryVersionInfo "0:2"
#define Module_FullVersion "0.03"
#define Module_HelpVersion "0.03 (08 May 2016)"
#define Module_LibraryVersionInfo "0:3"
......@@ -145,13 +145,18 @@ atomic_process_smp ROUT
MOV v3, a3
MOV v2, a2
MOV v1, a1
01 LDREX a1, [v3]
; The process function may affect the state of the exclusive monitor,
; so we must perform the LDREX-STREX in one go afterwards (manually
; checking [v3] for any changes that happened during the function call)
01 LDR a1, [v3]
MOV a2, v2
MOV v4, a1
BLX v1 ; any CPU that has LDREX will have BLX too
STREX ip, a1, [v3]
TEQ ip, #Strex_Failed
BEQ %B01 ; another exclusive access happened between LDREX and STREX
LDREX a2, [v3]
TEQ a2, v4
STREXEQ ip, a1, [v3]
TEQEQ ip, #Strex_Succeeded
BNE %B01 ; another exclusive access happened between LDR and STREX
MOV a1, v4
Return "v1-v4"
......@@ -107,8 +107,7 @@ spin_unlock_uniproc ROUT
spin_lock_smp ROUT
ORR a3, a2, #I32_bit
MSR CPSR_c, a3 ; IRQs now disabled
CPSID i ; IRQs now disabled
MOV a3, #Mutex_Locked
ASSERT :INDEX: Mutex = 0 :LAND: :BASE: Mutex = a1
01 LDREX a4, [a1]
......@@ -147,11 +147,15 @@ spinrw_read_unlock ROUT
$label MetaLock $origpsr, $locked_const, $tmp
[ "$origpsr" <> ""
[ "$origpsr" <> ""
MRS $origpsr, CPSR
[ variant = "smp"
CPSID i ; IRQs now disabled
ORR $tmp, $origpsr, #I32_bit
MSR CPSR_c, $tmp ; IRQs now disabled
[ variant = "smp"
ASSERT :INDEX: Mutex = 0 :LAND: :BASE: Mutex = a1
01 LDREX $tmp, [a1]
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