Commit fa89c230 authored by Jeffrey Lee's avatar Jeffrey Lee Committed by ROOL
Browse files

Adjust 26 vs. 32 bit mode checks

As noted in https://www.riscosopen.org/forum/forums/9/topics/15359, MRS
instructions which are executed in user mode may return unknown values
for the CPSR E, A, I, F and M fields on ARMv8 CPUs. At the moment the
only observed deviation from normal behaviour is that CPUs which lack
AArch32 privileged-mode support may return zero for the fields. This was
found to confuse some 26 vs. 32 bit mode checks in CLib.

Clearly we're a long way away from having a version of RISC OS which can
run on a CPU that lacks AArch32 privileged mode support, but we can
still try and make sure user-mode applications are compatible with them.
So this change adjusts the mode checks in the stubs and overlay manager
so that programs linked with them should function correctly (TEQ is now
used instead of MRS)

Note that once we do start porting RISC OS to one of the troublesome
CPUs, there are many more potentially troublesome MRS's within the
module code that will need adjusting, especially if CPUs start returning
values other than zero.

Version 6.07. Tagged as 'RISC_OSLib-6_07'
parent d3688b4c
...@@ -9,12 +9,12 @@ ...@@ -9,12 +9,12 @@
GBLS Module_ApplicationDate GBLS Module_ApplicationDate
GBLS Module_HelpVersion GBLS Module_HelpVersion
GBLS Module_ComponentName GBLS Module_ComponentName
Module_MajorVersion SETS "6.06" Module_MajorVersion SETS "6.07"
Module_Version SETA 606 Module_Version SETA 607
Module_MinorVersion SETS "" Module_MinorVersion SETS ""
Module_Date SETS "09 May 2020" Module_Date SETS "06 Jul 2020"
Module_ApplicationDate SETS "09-May-20" Module_ApplicationDate SETS "06-Jul-20"
Module_ComponentName SETS "RISC_OSLib" Module_ComponentName SETS "RISC_OSLib"
Module_FullVersion SETS "6.06" Module_FullVersion SETS "6.07"
Module_HelpVersion SETS "6.06 (09 May 2020)" Module_HelpVersion SETS "6.07 (06 Jul 2020)"
END END
/* (6.06) /* (6.07)
* *
* This file is automatically maintained by srccommit, do not edit manually. * This file is automatically maintained by srccommit, do not edit manually.
* *
*/ */
#define Module_MajorVersion_CMHG 6.06 #define Module_MajorVersion_CMHG 6.07
#define Module_MinorVersion_CMHG #define Module_MinorVersion_CMHG
#define Module_Date_CMHG 09 May 2020 #define Module_Date_CMHG 06 Jul 2020
#define Module_MajorVersion "6.06" #define Module_MajorVersion "6.07"
#define Module_Version 606 #define Module_Version 607
#define Module_MinorVersion "" #define Module_MinorVersion ""
#define Module_Date "09 May 2020" #define Module_Date "06 Jul 2020"
#define Module_ApplicationDate "09-May-20" #define Module_ApplicationDate "06-Jul-20"
#define Module_ComponentName "RISC_OSLib" #define Module_ComponentName "RISC_OSLib"
#define Module_FullVersion "6.06" #define Module_FullVersion "6.07"
#define Module_HelpVersion "6.06 (09 May 2020)" #define Module_HelpVersion "6.07 (06 Jul 2020)"
#define Module_LibraryVersionInfo "6:6" #define Module_LibraryVersionInfo "6:7"
...@@ -115,10 +115,9 @@ SharedLibrary SETL {TRUE} ...@@ -115,10 +115,9 @@ SharedLibrary SETL {TRUE}
MOV r6, r6, ASR #10 MOV r6, r6, ASR #10
MOV r6, r6, ASL #16 MOV r6, r6, ASL #16
[ APCS_Type <> "APCS-R" [ APCS_Type <> "APCS-R"
MOV r14, #0 TEQ r0, r0 ; sets Z
MRS r14, CPSR ; will be a NOP for 26-bit only processors TEQ pc, pc ; EQ if in a 32-bit mode, NE if 26-bit
TST r14, #&1C ; all these bits are clear if 26-bit ORREQ r6, r6, #1
ORRNE r6, r6, #1
] ]
[ Code_Destination = "RAM" [ Code_Destination = "RAM"
[ APCS_Type = "APCS-R" [ APCS_Type = "APCS-R"
...@@ -256,10 +255,9 @@ LookupError ...@@ -256,10 +255,9 @@ LookupError
MOV r6, r6, ASR #10 MOV r6, r6, ASR #10
MOV r6, r6, ASL #16 MOV r6, r6, ASL #16
[ APCS_Type <> "APCS-R" [ APCS_Type <> "APCS-R"
MOV r14, #0 TEQ r0, r0 ; sets Z
MRS r14, CPSR ; will be a NOP for 26-bit only processors TEQ pc, pc ; EQ if in a 32-bit mode, NE if 26-bit
TST r14, #&1C ; all these bits are clear if 26-bit ORREQ r6, r6, #1
ORRNE r6, r6, #1
] ]
[ Code_Destination = "RAM" [ Code_Destination = "RAM"
[ APCS_Type = "APCS-R" [ APCS_Type = "APCS-R"
......
...@@ -234,11 +234,10 @@ InitDone ...@@ -234,11 +234,10 @@ InitDone
[ {CONFIG}=26 [ {CONFIG}=26
BIC R8, LR, #PSRmask ; Clear psr BIC R8, LR, #PSRmask ; Clear psr
| |
MOV R4, #0 TEQ R0, R0 ; sets Z
MRS R4, CPSR TEQ PC, PC ; EQ if in a 32-bit mode, NE if 26-bit
TST R4, #2_11100 MOVEQ R8, LR
MOVNE R8, LR BICNE R8, LR, #PSRmask ; Clear psr
BICEQ R8, LR, #PSRmask ; Clear psr
] ]
LDR R0, [R8, #-8] ; saved R14... (is end of PCIT) LDR R0, [R8, #-8] ; saved R14... (is end of PCIT)
STR R0, [R3, #Work_LRSave] ; ...save it here ready for retry STR R0, [R3, #Work_LRSave] ; ...save it here ready for retry
...@@ -252,9 +251,10 @@ InitDone ...@@ -252,9 +251,10 @@ InitDone
AND R0, LR, #PSRmask ; psr at point of call... AND R0, LR, #PSRmask ; psr at point of call...
ORR R1, R1, R0 ; combine with address branched via ORR R1, R1, R0 ; combine with address branched via
| |
TST R4, #2_11100 TEQ R0, R0 ; sets Z
ANDEQ R0, LR, #PSRmask ; psr at point of call... TEQ PC, PC ; EQ if in a 32-bit mode, NE if 26-bit
ORREQ R1, R1, R0 ; combine with address branched via ANDNE R0, LR, #PSRmask ; psr at point of call...
ORRNE R1, R1, R0 ; combine with address branched via
] ]
STR R1, [R3, #Work_PCSave] ; where to resume at STR R1, [R3, #Work_PCSave] ; where to resume at
......
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