• Jeffrey Lee's avatar
    Adjust 26 vs. 32 bit mode checks · fa89c230
    Jeffrey Lee authored
    As noted in https://www.riscosopen.org/forum/forums/9/topics/15359, MRS
    instructions which are executed in user mode may return unknown values
    for the CPSR E, A, I, F and M fields on ARMv8 CPUs. At the moment the
    only observed deviation from normal behaviour is that CPUs which lack
    AArch32 privileged-mode support may return zero for the fields. This was
    found to confuse some 26 vs. 32 bit mode checks in CLib.
    Clearly we're a long way away from having a version of RISC OS which can
    run on a CPU that lacks AArch32 privileged mode support, but we can
    still try and make sure user-mode applications are compatible with them.
    So this change adjusts the mode checks in the stubs and overlay manager
    so that programs linked with them should function correctly (TEQ is now
    used instead of MRS)
    Note that once we do start porting RISC OS to one of the troublesome
    CPUs, there are many more potentially troublesome MRS's within the
    module code that will need adjusting, especially if CPUs start returning
    values other than zero.
    Version 6.07. Tagged as 'RISC_OSLib-6_07'
cl_stub 15.5 KB