Adapt clz (and family) to use CLZ instructions where available

Version 0.20. Tagged as 'AsmUtils-0_20'

VersionNum

-/* (0.19)
+/* (0.20)
  *
  * This file is automatically maintained by srccommit, do not edit manually.
- * Last processed by srccommit version: 1.1.
  *
  */
-#define Module_MajorVersion_CMHG        0.19
-#define Module_MinorVersion_CMHG        
-#define Module_Date_CMHG                12 Jun 2016
+#define Module_MajorVersion_CMHG        0.20
+#define Module_MinorVersion_CMHG
+#define Module_Date_CMHG                25 Jun 2022
 
-#define Module_MajorVersion             "0.19"
-#define Module_Version                  19
+#define Module_MajorVersion             "0.20"
+#define Module_Version                  20
 #define Module_MinorVersion             ""
-#define Module_Date                     "12 Jun 2016"
+#define Module_Date                     "25 Jun 2022"
 
-#define Module_ApplicationDate          "12-Jun-16"
+#define Module_ApplicationDate          "25-Jun-22"
 
 #define Module_ComponentName            "AsmUtils"
-#define Module_ComponentPath            "castle/RiscOS/Sources/Lib/AsmUtils"
 
-#define Module_FullVersion              "0.19"
-#define Module_HelpVersion              "0.19 (12 Jun 2016)"
-#define Module_LibraryVersionInfo       "0:19"
+#define Module_FullVersion              "0.20"
+#define Module_HelpVersion              "0.20 (25 Jun 2022)"
+#define Module_LibraryVersionInfo       "0:20"

h/clz

@@ -28,7 +28,7 @@
 extern "C" {
 #endif
 
-/* These functions are designed for CPUs without the CLZ instruction */
+/* These functions adapt to be optimal for CPUs with or without the CLZ instruction */
 
 extern unsigned int clz(unsigned int);
   /* Returns the number of leading zero bits in the argument, 0 ... 32 */

s/clz

@@ -19,6 +19,7 @@
         GET     Hdr:ListOpts
         GET     Hdr:Macros
         GET     Hdr:APCS.<APCS>
+        GET     Hdr:CPU.Arch
 
         AREA    |Asm$$Code|, CODE, READONLY
 
@@ -27,7 +28,28 @@
         EXPORT  |clo|
         EXPORT  |cto|
 
+|clo|
+      [ NoARMv5
+        ANDS    a4, a1, a1, ASR #1
+        MOVPL   a1, #0
+        ANDMI   a1, a4, a4, ASR #2
+        Return  , LinkNotStacked, PL
+        AND     a1, a1, a1, ASR #4
+        LDR     a2, =&06C9C57D
+        AND     a1, a1, a1, ASR #8
+        ADR     a3, table
+        AND     a1, a1, a1, ASR #16
+        RSB     a1, a1, #0
+        MUL     a1, a2, a1
+        LDRB    a1, [a3, a1, LSR #27]
+        Return  , LinkNotStacked
+      |
+        MVN     a1, a1
+        ; drop through...
+      ]
+
 |clz|
+      [ NoARMv5
         ORRS    a4, a1, a1, LSR #1
         MOVEQ   a1, #32
         ORRNE   a1, a4, a4, LSR #2
@@ -39,49 +61,50 @@
         ORR     a1, a1, a1, LSR #16
         MLAS    a1, a2, a1, a2
         LDRNEB  a1, [a3, a1, LSR #27]
+      |
+        CLZ     a1, a1
+      ]
         Return  , LinkNotStacked
 
-|ctz|
-        SUBS    a4, a1, #1
-        MOVCC   a1, #32
-        Return  , LinkNotStacked, CC
+|cto|
+      [ NoARMv5
+        ADDS    a4, a1, #1
+        MOVEQ   a1, #32
+        Return  , LinkNotStacked, EQ
         LDR     a2, =&06C9C57D
-        BIC     a1, a1, a4
+        BIC     a1, a4, a1
         MUL     a1, a2, a1
         ADR     a3, table
         LDRB    a1, [a3, a1, LSR #27]
         RSB     a1, a1, #32
         Return  , LinkNotStacked
+      |
+        MVN     a1, a1
+        ; drop through...
+      ]
 
-|clo|
-        ANDS    a4, a1, a1, ASR #1
-        MOVPL   a1, #0
-        ANDMI   a1, a4, a4, ASR #2
-        Return  , LinkNotStacked, PL
-        AND     a1, a1, a1, ASR #4
-        LDR     a2, =&06C9C57D
-        AND     a1, a1, a1, ASR #8
-        ADR     a3, table
-        AND     a1, a1, a1, ASR #16
-        RSB     a1, a1, #0
-        MUL     a1, a2, a1
-        LDRB    a1, [a3, a1, LSR #27]
-        Return  , LinkNotStacked
-
-|cto|
-        ADDS    a4, a1, #1
-        MOVEQ   a1, #32
-        Return  , LinkNotStacked, EQ
+|ctz|
+        SUBS    a4, a1, #1
+        MOVCC   a1, #32
+        Return  , LinkNotStacked, CC
+      [ NoARMv5
         LDR     a2, =&06C9C57D
-        BIC     a1, a4, a1
+        BIC     a1, a1, a4
         MUL     a1, a2, a1
         ADR     a3, table
         LDRB    a1, [a3, a1, LSR #27]
         RSB     a1, a1, #32
+      |
+        BIC     a4, a1, a4 ; identifies the bit position at which the borrow stopped
+        CLZ     a1, a4
+        RSB     a1, a1, #31
+      ]
         Return  , LinkNotStacked
 
+      [ NoARMv5
 table
         = 32, 31, 14, 30, 22, 13, 29, 19,  2, 21, 12, 10, 25, 28, 18,  8
         =  1, 15, 23, 20,  3, 11, 26,  9, 16, 24,  4, 27, 17,  5,  6,  7
+      ]
 
         END