Commit 0ee90f05 authored by Jeffrey Lee's avatar Jeffrey Lee Committed by ROOL

Fix a couple of RISCOS_MapInIO bugs

Detail:

- s/HAL - Fix ADD v. SUB muddle that could prevent addresses from being rounded down correctly. Fix incorrect logical address being returned to caller on pre-ARMv6 machines due to PageTableSync corrupting a1.
- s/NewReset - Initialising the CMOS RAM cache while in the middle of setting up the processor vectors feels a bit silly. Move the code to just afterwards so that it feels a bit safer, and so that early crashes are easier to debug (processor vectors in stable state)

Admin:

Tested on Iyonix.
Fixes ROM softload failure reported on forums:
https://www.riscosopen.org/forum/forums/11/topics/14749

Version 6.23. Tagged as 'Kernel-6_23'
parent bd294cf9
......@@ -9,12 +9,12 @@
GBLS Module_ApplicationDate
GBLS Module_HelpVersion
GBLS Module_ComponentName
Module_MajorVersion SETS "6.22"
Module_Version SETA 622
Module_MajorVersion SETS "6.23"
Module_Version SETA 623
Module_MinorVersion SETS ""
Module_Date SETS "16 Aug 2019"
Module_ApplicationDate SETS "16-Aug-19"
Module_Date SETS "21 Sep 2019"
Module_ApplicationDate SETS "21-Sep-19"
Module_ComponentName SETS "Kernel"
Module_FullVersion SETS "6.22"
Module_HelpVersion SETS "6.22 (16 Aug 2019)"
Module_FullVersion SETS "6.23"
Module_HelpVersion SETS "6.23 (21 Sep 2019)"
END
/* (6.22)
/* (6.23)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
#define Module_MajorVersion_CMHG 6.22
#define Module_MajorVersion_CMHG 6.23
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 16 Aug 2019
#define Module_Date_CMHG 21 Sep 2019
#define Module_MajorVersion "6.22"
#define Module_Version 622
#define Module_MajorVersion "6.23"
#define Module_Version 623
#define Module_MinorVersion ""
#define Module_Date "16 Aug 2019"
#define Module_Date "21 Sep 2019"
#define Module_ApplicationDate "16-Aug-19"
#define Module_ApplicationDate "21-Sep-19"
#define Module_ComponentName "Kernel"
#define Module_FullVersion "6.22"
#define Module_HelpVersion "6.22 (16 Aug 2019)"
#define Module_LibraryVersionInfo "6:22"
#define Module_FullVersion "6.23"
#define Module_HelpVersion "6.23 (21 Sep 2019)"
#define Module_LibraryVersionInfo "6:23"
......@@ -2387,7 +2387,7 @@ RISCOS_MapInIO_PTE ; a1 bits 0-19 = L1 section entry flags, bits 20+ = our extra
50 ; Request not currently mapped, only partially mapped, or mapped with wrong flags
LDR ip, =ZeroPage
ADD v8, v3, #1 ; v8 = number of MB to use in rounding (0 for sections, 15 for supersections)
SUB v8, v3, #1 ; v8 = number of MB to use in rounding (0 for sections, 15 for supersections)
LDR a3, [ip, #IOAllocPtr]
MOV a3, a3, LSR #20
BIC a3, a3, v8 ; round down to 1MB or 16MB boundary (some memory may remain unmapped above when we map in a supersection)
......@@ -2414,7 +2414,9 @@ RISCOS_MapInIO_PTE ; a1 bits 0-19 = L1 section entry flags, bits 20+ = our extra
CMP v4, v5
BLO %BT60
PageTableSync
MOV a2, a1
PageTableSync ; corrupts a1
MOV a1, a2
80
LDR a2, [sp] ; retrieve original physical address from stack
BIC a2, a2, #&FF000000 ; distance from 16MB boundary for supersections
......
......@@ -132,24 +132,6 @@ Continue_after_HALInit
ChangedProcVecs r0
[ CacheCMOSRAM
DebugTX "InitCMOSCache entry"
BL InitCMOSCache ; initialise cache of CMOS RAM
TEQ R0, #0 ; returns zero on failure
[ ZeroPage <> 0
LDREQ R0, =ZeroPage
]
LDREQ R1, [R0, #HAL_StartFlags]
ORREQ R1, R1, #OSStartFlag_NoCMOS
STREQ R1, [R0, #HAL_StartFlags]
BEQ %FT41
DebugTX "InitCMOSCache done"
B %FT42
41
DebugTX "InitCMOSCache failed"
42
]
; Now copy the initialised data
LDR R0, =ZeroPage+IRQ1V
ADRL r1, StartData
......@@ -218,6 +200,24 @@ conversionSWIfill
BL MakePageTablesCacheable
]
[ CacheCMOSRAM
DebugTX "InitCMOSCache entry"
BL InitCMOSCache ; initialise cache of CMOS RAM
TEQ R0, #0 ; returns zero on failure
[ ZeroPage <> 0
LDREQ R0, =ZeroPage
]
LDREQ R1, [R0, #HAL_StartFlags]
ORREQ R1, R1, #OSStartFlag_NoCMOS
STREQ R1, [R0, #HAL_StartFlags]
BEQ %FT41
DebugTX "InitCMOSCache done"
B %FT42
41
DebugTX "InitCMOSCache failed"
42
]
; Initialise CAO ptr to none.
LDR R0, =ZeroPage
......
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