;
; A600tlb
;
; POST procedure for checking the TLB in A600 MMU.
;
; for each of level 1, level 2 small-page, level 2 large-page
;	construct page table
; 	flush cache
; 	start timer
; 	for 32 addresses (with different mappings)
;		check address mapping
; 	save timer
; 	for same 32 addresses
;		check address mapping
; 	compare test times (did 2nd test require table walk ?)





Use a list of addresses that cover a good mixture of virtual addresses
Build a page table that maps these to physical RAM addresses in various ways
Access the addresses in such an order that the cache rotates, scrapping 
one entry each time through the list, and loading another. So each cache
entry gets used 31 times, then is lost.
Choice of physical mapping should ensure that the cache entries contain
lots of different values of page and section base addresses.
Choice of virtual test address should ensure that cache tag varies as
widely as posible, too.  PRBS ?
Very widely varying values of  cache tag require that a large number
of mappings exist .. if  these are 2-level mappings, that requires
a lot of RAM. Page tables should be multiply-mapped.
RISC OS puts lots of stuff below the 4M mark. Limits App space to 16M
for backwards compatibility. Probably worth testing outside these 
limits to ensure Gold doesn't fall over, but failure rates would be
very low.




;
; POST procedure for checking access faults (was PPL test)
;
; for each of level 1, level 2 small-page, level 2 large-page
;	construct page table
;	for user, supervisor mode
;		check address alignment fault
;		check section translation fault
;		check 
;		check page translation fault
;		for 3 domain types
;			for 16 domains
;	 			check access permissions
;



;
; POST procedure for checking IDC
;
;