; Copyright 2000 Pace Micro Technology plc
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; GET Hdr:ListOpts
; GET Hdr:Macros
; GET Hdr:System
; $GetCPU
; $GetMEMM
; GET hdr.Options
; GET Hdr:PublicWS
; GET Hdr:KernelWS
; GET hdr.Copro15ops
; GET hdr.ARMops
v7 RN 10
; EXPORT Init_ARMarch
; EXPORT ARM_Analyse
; EXPORT ARM_PrintProcessorType
; AREA KernelCode,CODE,READONLY
; ARM keep changing their mind about ID field layout.
; Here's a summary, courtesy of the ARM ARM (v5):
;
; pre-ARM 7: xxxx0xxx
; ARM 7: xxxx7xxx where bit 23 indicates v4T/~v3
; post-ARM 7: xxxanxxx where n<>0 or 7 and a = architecture (1=4,2=4T,3=5,4=5T)
;
; int Init_ARMarch(void)
; Returns architecture, as above in a1. Also EQ if ARMv3, NE if ARMv4 or later.
; Corrupts only ip, no RAM usage.
Init_ARMarch
ARM_read_ID ip
ANDS a1, ip, #&0000F000
MOVEQ pc, lr ; ARM 3 or ARM 6
TEQ a1, #&00007000
BNE %FT20
TST ip, #&00800000 ; ARM 7 - check for Thumb
MOVNE a1, #ARMv4T
MOVEQ a1, #ARMv3
MOV pc, lr
20 ANDS a1, ip, #&000F0000 ; post-ARM 7
MOV a1, a1, LSR #16
MOV pc, lr
ARM_Analyse
Push "v1,v2,v5,v6,v7,lr"
ARM_read_ID v1
ARM_read_cachetype v2
MOV v6, #ZeroPage
ADR v7, KnownCPUTable
FindARMloop
LDMIA v7!, {a1, a2} ; See if it's a known ARM
CMP a1, #-1
BEQ %FT20
AND a2, v1, a2
TEQ a1, a2
ADDNE v7, v7, #8
BNE FindARMloop
TEQ v2, v1 ; If we don't have cache attributes, read from table
LDREQ v2, [v7]
20 TEQ v2, v1
BEQ %BT20 ; Cache unknown: panic
CMP a1, #-1
LDRNEB a2, [v7, #4]
MOVEQ a2, #ARMunk
STRB a2, [v6, #ProcessorType]
ASSERT CT_Isize_pos = 0
MOV a1, v2
ADD a2, v6, #ICache_Info
BL EvaluateCache
MOV a1, v2, LSR #CT_Dsize_pos
ADD a2, v6, #DCache_Info
BL EvaluateCache
AND a1, v2, #CT_ctype_mask
MOV a1, a1, LSR #CT_ctype_pos
STRB a1, [v6, #Cache_Type]
MOV v5, #0
TST v2, #CT_S
ORRNE v5, v5, #CPUFlag_SplitCache
; Test abort timing (base restored or base updated)
MOV a1, #&8000
LDR a2, [a1], #4 ; Will abort - DAb handler will continue execution
TEQ a1, #&8000
ORREQ v5, v5, #CPUFlag_BaseRestored
; Check store of PC
30 STR pc, [sp, #-4]!
ADR a2, %BT30 + 8
LDR a1, [sp], #4
TEQ a1, a2
ORREQ v5, v5, #CPUFlag_StorePCplus8
[ 0=1
; Check whether 26-bit mode is available
MSR CPSR_c, #F32_bit+I32_bit+SVC26_mode
MRS a1, CPSR
AND a1, a1, #M32_bits
TEQ a1, #SVC26_mode
ORRNE v5, v5, #CPUFlag_No26bitMode
MSREQ CPSR_c, #F32_bit+I32_bit+SVC32_mode
BNE %FT35
; Do we get vector exceptions on read?
MOV a1, #0
LDR a1, [a1] ; If this aborts a1 will be left unchanged
TEQ a1, #0
ORREQ v5, v5, #CPUFlag_VectorReadException
]
35
BL Init_ARMarch
STRB a1, [v6, #ProcessorArch]
LDRB v4, [v6, #ProcessorType]
TEQ v4, #ARMunk ; Modify deduced flags
ADRNE lr, KnownCPUFlags
ADDNE lr, lr, v4, LSL #3
LDMNEIA lr, {a1, a2}
ORRNE v5, v5, a1
BICNE v5, v5, a2
STR v5, [v6, #ProcessorFlags]
; Now, a1 = processor architecture (ARMv3, ARMv4 ...)
; v4 = processor type (ARM600, ARM610, ...)
; v5 = processor flags
CMP a1, #ARMv4
BLO Analyse_ARMv3
LDRB a2, [v6, #Cache_Type]
TEQ a2, #CT_ctype_WT
TSTEQ v5, #CPUFlag_SplitCache
BEQ Analyse_WriteThroughUnified
50 B %50 ; stiff :)
Analyse_ARMv3
ADR a1, NullOp
ADR a2, Cache_Invalidate_ARMv3
ADR a3, WriteBuffer_Drain_ARMv3
ADR a4, TLB_Invalidate_ARMv3
ADR ip, TLB_InvalidateEntry_ARMv3
STR a1, [v6, #Proc_Cache_CleanAll]
STR a2, [v6, #Proc_Cache_CleanInvalidateAll]
STR a2, [v6, #Proc_Cache_InvalidateAll]
STR a3, [v6, #Proc_WriteBuffer_Drain]
STR a4, [v6, #Proc_TLB_InvalidateAll]
STR ip, [v6, #Proc_TLB_InvalidateEntry]
STR a1, [v6, #Proc_IMB_Full]
STR a1, [v6, #Proc_IMB_Range]
ADR a1, MMU_Changing_ARMv3
ADR a2, MMU_ChangingEntry_ARMv3
ADR a3, MMU_ChangingUncached_ARMv3
ADR a4, MMU_ChangingUncachedEntry_ARMv3
STR a1, [v6, #Proc_MMU_Changing]
STR a2, [v6, #Proc_MMU_ChangingEntry]
STR a3, [v6, #Proc_MMU_ChangingUncached]
STR a4, [v6, #Proc_MMU_ChangingUncachedEntry]
ADR a1, MMU_ChangingEntries_ARMv3
ADR a2, MMU_ChangingUncachedEntries_ARMv3
ADR a3, Cache_RangeThreshold_ARMv3
STR a1, [v6, #Proc_MMU_ChangingEntries]
STR a2, [v6, #Proc_MMU_ChangingUncachedEntries]
STR a3, [v6, #Proc_Cache_RangeThreshold]
B %FT90
Analyse_WriteThroughUnified
ADR a1, NullOp
ADR a2, Cache_InvalidateUnified
TST v5, #CPUFlag_NoWBDrain
ADRNE a3, WriteBuffer_Drain_OffOn
ADREQ a3, WriteBuffer_Drain
ADR a4, TLB_Invalidate_Unified
ADR ip, TLB_InvalidateEntry_Unified
STR a1, [v6, #Proc_Cache_CleanAll]
STR a2, [v6, #Proc_Cache_CleanInvalidateAll]
STR a2, [v6, #Proc_Cache_InvalidateAll]
STR a3, [v6, #Proc_WriteBuffer_Drain]
STR a4, [v6, #Proc_TLB_InvalidateAll]
STR ip, [v6, #Proc_TLB_InvalidateEntry]
STR a1, [v6, #Proc_IMB_Full]
STR a1, [v6, #Proc_IMB_Range]
ADR a1, MMU_Changing_Writethrough
ADR a2, MMU_ChangingEntry_Writethrough
ADR a3, MMU_ChangingUncached
ADR a4, MMU_ChangingUncachedEntry
STR a1, [v6, #Proc_MMU_Changing]
STR a2, [v6, #Proc_MMU_ChangingEntry]
STR a3, [v6, #Proc_MMU_ChangingUncached]
STR a4, [v6, #Proc_MMU_ChangingUncachedEntry]
ADR a1, MMU_ChangingEntries_Writethrough
ADR a2, MMU_ChangingUncachedEntries
ADR a3, Cache_RangeThreshold_Writethrough
STR a1, [v6, #Proc_MMU_ChangingEntries]
STR a2, [v6, #Proc_MMU_ChangingUncachedEntries]
STR a3, [v6, #Proc_Cache_RangeThreshold]
B %FT90
90
Pull "v1,v2,v5,v6,v7,pc"
; This routine works out the values LINELEN, ASSOCIATIVITY, NSETS and CACHE_SIZE defined in section
; B2.3.3 of the ARMv5 ARM.
EvaluateCache
AND a3, a1, #CT_assoc_mask+CT_M
TEQ a3, #(CT_assoc_0:SHL:CT_assoc_pos)+CT_M
BEQ %FT80
MOV ip, #1
ASSERT CT_len_pos = 0
AND a4, a1, #CT_len_mask
ADD a4, a4, #3
MOV a4, ip, LSL a4 ; LineLen = 1 << (len+3)
STRB a4, [a2, #ICache_LineLen-ICache_Info]
MOV a3, #2
TST a1, #CT_M
ADDNE a3, a3, #1 ; Multiplier = 2 + M
AND a4, a1, #CT_assoc_mask
RSB a4, ip, a4, LSR #CT_assoc_pos
MOV a4, a3, LSL a4 ; Associativity = Multiplier << (assoc-1)
STRB a4, [a2, #ICache_Associativity-ICache_Info]
AND a4, a1, #CT_size_mask
MOV a4, a4, LSR #CT_size_pos
MOV a3, a3, LSL a4
MOV a3, a3, LSL #8 ; Size = Multiplier << (size+8)
STR a3, [a2, #ICache_Size-ICache_Info]
ADD a4, a4, #6
AND a3, a1, #CT_assoc_mask
SUB a4, a4, a3, LSR #CT_assoc_pos
AND a3, a1, #CT_len_mask
ASSERT CT_len_pos = 0
SUB a4, a4, a3
MOV a4, ip, LSL a4 ; NSets = 1 << (size + 6 - assoc - len)
STR a4, [a2, #ICache_NSets-ICache_Info]
MOV pc, lr
80 MOV a1, #0
STR a1, [a2, #ICache_NSets-ICache_Info]
STR a1, [a2, #ICache_Size-ICache_Info]
STRB a1, [a2, #ICache_LineLen-ICache_Info]
STRB a1, [a2, #ICache_Associativity-ICache_Info]
MOV pc, lr
; Create a list of CPUs, 16 bytes per entry:
; ID bits (1 word)
; Test mask for ID (1 word)
; Cache type register value (1 word)
; Processor type (1 byte)
; Architecture type (1 byte)
; Reserved (2 bytes)
GBLA tempcpu
MACRO
CPUDesc $proc, $id, $mask, $arch, $type, $s, $dsz, $das, $dln, $isz, $ias, $iln
LCLA type
type SETA (CT_ctype_$type:SHL:CT_ctype_pos)+($s:SHL:CT_S_pos)
tempcpu CSzDesc $dsz, $das, $dln
type SETA type+(tempcpu:SHL:CT_Dsize_pos)
[ :LNOT:($s=0 :LAND: "$isz"="")
tempcpu CSzDesc $isz, $ias, $iln
]
type SETA type+(tempcpu:SHL:CT_Isize_pos)
ASSERT ($id :AND: :NOT: $mask) = 0
DCD $id, $mask, type
DCB $proc, $arch, 0, 0
MEND
MACRO
$var CSzDesc $sz, $as, $ln
$var SETA (CT_size_$sz:SHL:CT_size_pos)+(CT_assoc_$as:SHL:CT_assoc_pos)+(CT_len_$ln:SHL:CT_len_pos)
$var SETA $var+(CT_M_$sz:SHL:CT_M_pos)
MEND
KnownCPUTable
; /------Cache Type register fields-----\�
; ID reg Mask Arch Type S Dsz Das Dln Isz Ias Iln
CPUDesc ARM600, &000600, &00FFF0, ARMv3, WT, 0, 4K, 64, 4
CPUDesc ARM610, &000610, &00FFF0, ARMv3, WT, 0, 4K, 64, 4
CPUDesc ARMunk, &000000, &00F000, ARMv3, WT, 0, 4K, 64, 4
CPUDesc ARM700, &007000, &FFFFF0, ARMv3, WT, 0, 8K, 4, 8
CPUDesc ARM710, &007100, &FFFFF0, ARMv3, WT, 0, 8K, 4, 8
CPUDesc ARM710a, &047100, &FDFFF0, ARMv3, WT, 0, 8K, 4, 4
CPUDesc ARM7500, &067100, &FFFFF0, ARMv3, WT, 0, 4K, 4, 4
CPUDesc ARM7500FE,&077100, &FFFFF0, ARMv3, WT, 0, 4K, 4, 4
CPUDesc ARMunk, &007000, &80F000, ARMv3, WT, 0, 8K, 4, 4
CPUDesc ARM720T, &807200, &FFFFF0, ARMv4T, WT, 0, 8K, 4, 4
CPUDesc ARMunk, &807000, &80F000, ARMv4T, WT, 0, 8K, 4, 4
CPUDesc SA110, &01A100, &0FFFF0, ARMv4, WB_Crd, 1, 16K, 32, 8, 16K, 32, 8
CPUDesc SA1100, &01A110, &0FFFF0, ARMv4, WB_Crd, 1, 8K, 32, 8, 16K, 32, 8
CPUDesc SA1110, &01B110, &0FFFF0, ARMv4, WB_Crd, 1, 8K, 32, 8, 16K, 32, 8
CPUDesc ARM920T, &029200, &0FFFF0, ARMv4T, WB_CR7_LDa, 1, 16K, 64, 8, 16K, 64, 8
CPUDesc ARM922T, &029220, &0FFFF0, ARMv4T, WB_CR7_LDa, 1, 8K, 64, 8, 8K, 64, 8
CPUDesc X80200, &052000, &0FFFF0, ARMv5TE, WB_Cal_LD, 1, 32K, 32, 8, 32K, 32, 8
DCD -1
; Peculiar characteristics of individual ARMs not deducable otherwise. First field is
; flags to set, second flags to clear.
KnownCPUFlags
DCD 0, 0 ; ARM 600
DCD 0, 0 ; ARM 610
DCD 0, 0 ; ARM 700
DCD 0, 0 ; ARM 710
DCD 0, 0 ; ARM 710a
DCD 0, 0 ; SA 110
DCD 0, 0 ; ARM 7500
DCD 0, 0 ; ARM 7500FE
DCD 0, 0 ; SA 1100
DCD 0, 0 ; SA 1110
DCD CPUFlag_NoWBDrain, 0 ; ARM 720T
DCD 0, 0 ; ARM 920T
DCD 0, 0 ; ARM 922T
DCD 0, 0 ; X80200
; THE RULES: These routines may corrupt a1 only
Cache_Invalidate_ARMv3
MCR p15, 0, a1, c7, c0
NullOp MOV pc, lr
WriteBuffer_Drain_ARMv3
;swap forces unbuffered write, stalling till WB empty
SUB a1, sp, #4
SWP a1, a1, [a1]
MOV pc, lr
TLB_Invalidate_ARMv3
MCR p15, 0, a1, c5, c0
MOV pc, lr
TLB_InvalidateEntry_ARMv3
MCR p15, 0, a1, c6, c0
MOV pc, lr
MMU_Changing_ARMv3
MCR p15, 0, a1, c7, c0 ; invalidate cache
MCR p15, 0, a1, c5, c0 ; invalidate TLB
MOV pc, lr
MMU_ChangingUncached_ARMv3
MCR p15, 0, a1, c5, c0 ; invalidate TLB
MOV pc, lr
MMU_ChangingEntry_ARMv3
MCR p15, 0, a1, c7, c0 ; invalidate cache
MCR p15, 0, a1, c6, c0 ; invalidate TLB entry
MOV pc, lr
MMU_ChangingEntries_ARMv3 ROUT
Push "a2"
MCR p15, 0, a1, c7, c0 ; invalidate cache
10
MCR p15, 0, a1, c6, c0 ; invalidate TLB entry
SUBS a2, a2, #1 ; next page
ADD a1, a1, #PageSize
BNE %BT10
Pull "a2"
MOV pc, lr
MMU_ChangingUncachedEntry_ARMv3
MCR p15, 0, a1, c6, c0 ; invalidate TLB entry
MOV pc, lr
MMU_ChangingUncachedEntries_ARMv3 ROUT
Push "a2"
10
MCR p15, 0, a1, c6, c0 ; invalidate TLB entry
SUBS a2, a2, #1 ; next page
ADD a1, a1, #PageSize
BNE %BT10
Pull "a2"
MOV pc, lr
Cache_RangeThreshold_ARMv3
! 0, "arbitrary Cache_RangeThreshold_ARMv3"
MOV a1, #16*PageSize
MOV pc, lr
Cache_InvalidateUnified
MOV a1, #0
MCR p15, 0, a1, c7, c7
MOV pc, lr
WriteBuffer_Drain_OffOn
Push "a2"
ARM_read_control a1
BIC a2, a1, #MMUC_W
ARM_write_control a2
ARM_write_control a1
Pull "a2"
MOV pc, lr
WriteBuffer_Drain
MOV a1, #0
MCR p15, 0, a1, c7, c10, 4
MOV pc, lr
TLB_Invalidate_Unified
MOV a1, #0
MCR p15, 0, a1, c8, c7
MOV pc, lr
TLB_InvalidateEntry_Unified
MCR p15, 0, a1, c8, c7, 1
MOV pc, lr
MMU_Changing_Writethrough
MOV a1, #0
MCR p15, 0, a1, c7, c7 ; invalidate cache
MCR p15, 0, a1, c8, c7 ; invalidate TLB
MOV pc, lr
MMU_ChangingUncached
MOV a1, #0
MCR p15, 0, a1, c8, c7 ; invalidate TLB
MOV pc, lr
MMU_ChangingEntry_Writethrough
Push "a4"
MOV a4, #0
MCR p15, 0, a4, c7, c7 ; invalidate cache
MCR p15, 0, a1, c8, c7, 1 ; invalidate TLB entry
Pull "a4"
MOV pc, lr
MMU_ChangingEntries_Writethrough ROUT
Push "a2,a4"
MOV a4, #0
MCR p15, 0, a4, c7, c7 ; invalidate cache
10
MCR p15, 0, a1, c8, c7, 1 ; invalidate TLB entry
SUBS a2, a2, #1 ; next page
ADD a1, a1, #PageSize
BNE %BT10
Pull "a2,a4"
MOV pc, lr
MMU_ChangingUncachedEntry
MCR p15, 0, a1, c8, c7, 1 ; invalidate TLB entry
MOV pc, lr
MMU_ChangingUncachedEntries ROUT
Push "a2"
10
MCR p15, 0, a1, c8, c7, 1 ; invalidate TLB entry
SUBS a2, a2, #1 ; next page
ADD a1, a1, #PageSize
BNE %BT10
Pull "a2"
MOV pc, lr
Cache_RangeThreshold_Writethrough
! 0, "arbitrary Cache_RangeThreshold_Writethrough"
MOV a1, #16*PageSize
MOV pc, lr
; IMPORT Write0_Translated
ARM_PrintProcessorType
MOV a1, #ZeroPage
LDRB a1, [a1, #ProcessorType]
TEQ a1, #ARMunk
MOVEQ pc, lr
Push "lr"
ADR a2, processor_names
ADD a1, a2, a1, LSL #5
BL Write0_Translated
SWI XOS_NewLine
SWI XOS_NewLine
Pull "pc"
processor_names
= "600:ARM 600 Processor",0
ALIGN 32
= "610:ARM 610 Processor",0
ALIGN 32
= "700:ARM 700 Processor",0
ALIGN 32
= "710:ARM 710 Processor",0
ALIGN 32
= "710a:ARM 710a Processor",0
ALIGN 32
= "SA110:SA-110 Processor",0
ALIGN 32
= "7500:ARM 7500 Processor",0
ALIGN 32
= "7500FE:ARM 7500FE Processor",0
ALIGN 32
= "SA1100:SA-1100 Processor",0
ALIGN 32
= "SA1110:SA-1110 Processor",0
ALIGN 32
= "720T:ARM 720T Processor",0
ALIGN 32
= "920T:ARM 920T Processor",0
ALIGN 32
= "922T:ARM 922T Processor",0
ALIGN 32
= "X80200:80200 Processor",0
ALIGN
END