; Copyright 2015 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
;     http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;

; Miscellaneous public definitions that aren't important enough to pollute
; Hdr:RISCOS or to have their own header

; OS_PlatformFeatures reason codes

OSPlatformFeatures_ReadCodeFeatures     * 0
OSPlatformFeatures_ReadProcessorVectors * 32
OSPlatformFeatures_ReadCacheInfo        * 33

; These flags are returned by OS_PlatformFeatures 0 (Read code features)

CPUFlag_SynchroniseCodeAreas    * 1:SHL:0       ; Calls to OS_SynchroniseCodeAreas required
CPUFlag_InterruptDelay          * 1:SHL:1       ; Clearing then setting I bit immediately doesn't trigger IRQs
CPUFlag_VectorReadException     * 1:SHL:2       ; 26-bit reads of hardware vectors abort
CPUFlag_StorePCplus8            * 1:SHL:3       ; Stores of R15 store PC+8 rather than PC+12
CPUFlag_BaseRestored            * 1:SHL:4       ; Base Restored abort model rather than Base Updated
CPUFlag_SplitCache              * 1:SHL:5       ; CPU has separate I and D caches
CPUFlag_32bitOS                 * 1:SHL:6       ; OS is 32-bit
CPUFlag_No26bitMode             * 1:SHL:7       ; CPU does not support 26-bit modes
CPUFlag_LongMul                 * 1:SHL:8       ; Has M extensions (UMULL etc)
CPUFlag_Thumb                   * 1:SHL:9       ; Supports Thumb
CPUFlag_DSP                     * 1:SHL:10      ; Has E extensions (QADD etc)
CPUFlag_NoSWP                   * 1:SHL:11      ; CPU does not support SWP/SWPB
CPUFlag_LoadStoreEx             * 1:SHL:12      ; Has LDR/STREX
CPUFlag_LoadStoreClearExSizes   * 1:SHL:13      ; Has CLREX and LDR/STREX[B|H|D]
CPUFlag_ExtendedPages           * 1:SHL:15      ; Supports extended small page L2 descriptors
CPUFlag_NoWBDrain               * 1:SHL:16      ; CPU does not support Drain Write Buffer instruction
CPUFlag_AbortRestartBroken      * 1:SHL:17      ; Aborts do not correctly follow documented abort model
CPUFlag_XScale                  * 1:SHL:18      ; it's an XScale, so weird debug etc
CPUFlag_XScaleJTAGconnected     * 1:SHL:19      ; JTAG has been connected
CPUFlag_HiProcVecs              * 1:SHL:20      ; High processor vectors are in use

; OS_MMUControl reason codes

                                ^ 0
MMUCReason_ModifyControl        # 1
MMUCReason_Flush                # 1
MMUCReason_GetARMop             # 1
MMUCReason_Unknown              # 0

; These are the ARMops exposed by OS_MMUControl 2

                                  ^ 0
ARMop_Cache_CleanInvalidateAll    # 1 ; 0
ARMop_Cache_CleanAll              # 1 ; 1
ARMop_Cache_InvalidateAll         # 1 ; 2
ARMop_Cache_RangeThreshold        # 1 ; 3
ARMop_TLB_InvalidateAll           # 1 ; 4
ARMop_TLB_InvalidateEntry         # 1 ; 5
ARMop_DSB_ReadWrite               # 1 ; 6
ARMop_IMB_Full                    # 1 ; 7
ARMop_IMB_Range                   # 1 ; 8
ARMop_IMB_List                    # 1 ; 9
ARMop_MMU_Changing                # 1 ; 10
ARMop_MMU_ChangingEntry           # 1 ; 11
ARMop_MMU_ChangingUncached        # 1 ; 12
ARMop_MMU_ChangingUncachedEntry   # 1 ; 13
ARMop_MMU_ChangingEntries         # 1 ; 14
ARMop_MMU_ChangingUncachedEntries # 1 ; 15
ARMop_DSB_Write                   # 1 ; 16
ARMop_DSB_Read                    # 1 ; 17
ARMop_DMB_ReadWrite               # 1 ; 18
ARMop_DMB_Write                   # 1 ; 19
ARMop_DMB_Read                    # 1 ; 20
ARMop_Cache_CleanInvalidateRange  # 1 ; 21
ARMop_Max                         # 0

        END