REM Copyright (c) 2021, RISC OS Open Ltd
REM All rights reserved.
REM
REM Redistribution and use in source and binary forms, with or without
REM modification, are permitted provided that the following conditions are met:
REM     * Redistributions of source code must retain the above copyright
REM       notice, this list of conditions and the following disclaimer.
REM     * Redistributions in binary form must reproduce the above copyright
REM       notice, this list of conditions and the following disclaimer in the
REM       documentation and/or other materials provided with the distribution.
REM     * Neither the name of RISC OS Open Ltd nor the names of its contributors
REM       may be used to endorse or promote products derived from this software
REM       without specific prior written permission.
REM
REM THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
REM AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
REM IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
REM ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
REM LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
REM CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
REM SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
REM INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
REM CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
REM ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
REM POSSIBILITY OF SUCH DAMAGE.

REM Test AbortTrap handling of different instructions

is_basicvfp%=INSTR(REPORT$,"VFP") > 0

ON ERROR ERROR EXT 0,REPORT$+" at "+STR$(ERL)
da_size%=4096*3
SYS "OS_Module",6,,,4096+da_size% TO ,,rma%

swi$="OS_AbortTrap"

REM Relevant OS_PlatformFeatures 34 feature flags
CPUFeature_CLREX_LDREXB_LDREXH_STREXB_STREXH =5
CPUFeature_Interworking_MOV_pc               =11
CPUFeature_LDAx_STLx                         =12
CPUFeature_LDM_STM_continuable               =13
CPUFeature_LDM_STM_noninterruptible          =14
CPUFeature_LDM_STM_restartable               =15
CPUFeature_LDRD_STRD                         =16
CPUFeature_LDREXD_STREXD                     =17
CPUFeature_LDREX_STREX                       =18
CPUFeature_LDRHT_LDRSBT_LDRSHT_STRHT         =19
CPUFeature_LDRH_LDRSH_STRH                   =20
CPUFeature_LDRSB                             =21
CPUFeature_LDR_STR_Rd_Rn_restriction         =22
CPUFeature_SRS_RFE_CPS                       =45
CPUFeature_SWP_SWPB                          =47
CPUFeature_SWP_SWPB_uniproc                  =48
CPUFeature_Rotated_loads                     =58
CPUFeature_Unaligned_loads                   =59

REM Work out whether we can test rotated or unaligned loads
SYS "OS_ReadSysInfo",8 TO ,rsi_flags%,rsi_valid%
can_rotate%=FALSE
can_unaligned%=FALSE
can_align%=FALSE
IF (rsi_valid% AND 96)=96 THEN
 REM Can test rotated loads if they're supported, and the OS isn't using unaligned loads
 can_rotate%=(FNfeature("Rotated_loads")<>0) AND (rsi_flags% AND 64)=0
 REM Can test unaligned loads if they're supported, and the OS isn't using rotated loads
 can_unaligned%=(FNfeature("Unaligned_loads")<>0) AND (rsi_flags% AND 32)=0
 REM Can test aligned loads if the OS isn't using aligned/rotated loads
 can_align%=(rsi_flags% AND 96)=0
ENDIF

REM Work out if VFP/NEON supported
SYS &78EC8,0 TO ,MVFR0%,MVFR1%;flags% : REM XVFPSupport_Features
IF flags% AND 1 THEN
 have_vfp%=FALSE
 have_neon%=FALSE
ELSE
 have_vfp%=(MVFR0% AND &F)<>0
 have_neon%=(MVFR1% AND &F00)<>0
 IF (MVFR0% AND &F)=1 THEN max_dregs%=16 ELSE max_dregs%=32
ENDIF

sctlr_a%=1<<1
sctlr_u%=1<<22

FOR pass=0 TO 2 STEP 2
P%=rma%
[ OPT pass
.handler%
; R0 = flags
; R1 = buffer
; R2 = required address
; R3 = length
; R12 = param
STMFD R13!,{R0-R5,R14}
ADR R4,last_call%
MRS R5,CPSR
STMIA R4,{R0-R3,R5,R12}
LDR R5,call_count%
ADD R5,R5,#1
STR R5,call_count%
AND R0,R0,#15
CMP R0,#2
BEQ mapin%
LDMHIFD R13!,{R0-R5,R14}
MSRHI CPSR_f,#(1<<28)+(1<<29)
ADRHI R0,bad_reason
MOVHI PC,LR

ADR R4,buffer%
LDR R5,da_base_ptr%
SUB R2,R2,R5
ADD R2,R2,R4
TST R0,#1
EORNE R1,R1,R2 ; R1^R2, R2
EORNE R2,R2,R1 ; R1^R2, R1
EORNE R1,R1,R2 ; R2, R1
.loop%
SUBS R3,R3,#1
LDRB R5,[R1],#1
STRB R5,[R2],#1
BNE loop%
LDMFD R13!,{R0-R5,PC}

.mapin%
MOV R0,#9
LDR R1,da_num_val%
; R2, R3 already correct
SWI "OS_DynamicArea"
STRVS R0,[SP]
LDMFD R13!,{R0-R5,PC}

.bad_reason
EQUD 0
EQUS "Bad reason" : EQUB 0
ALIGN

.writew_svc%
SWI "OS_EnterOS"
STR R1,[R0]
SWI "OS_LeaveOS"
MOV PC,R14

.readb_svc%
SWI "OS_EnterOS"
LDRB R0,[R0]
SWI "OS_LeaveOS"
MOV PC,R14

.readw_svc%
SWI "OS_EnterOS"
LDR R0,[R0]
SWI "OS_LeaveOS"
MOV PC,R14

.read_sctlr%
SWI "OS_EnterOS"
MRC CP15,0,R0,C1,C0,0
SWI "OS_LeaveOS"
MOV PC,R14

.write_sctlr%
SWI "OS_EnterOS"
MCR CP15,0,R0,C1,C0,0
SWI "OS_LeaveOS"
MOV PC,R14

.read_fpsr%
RFS R0
MOV PC,R14

.ldm_usr%
ADR R1, ldm_buf%
LDMIA R0,{R2-R3}
STMIA R1,{R2-R3}
MOV PC,R14

.stm_usr%
ADR R1, ldm_buf%
LDMIA R1,{R2-R3}
STMIA R0,{R2-R3}
MOV PC,R14

.ldm_svc%
SWI "OS_EnterOS"
ADR R1, ldm_buf%
LDMIA R0,{R2-R3}
STMIA R1,{R2-R3}
SWI "OS_LeaveOS"
MOV PC,R14

.stm_svc%
SWI "OS_EnterOS"
ADR R1, ldm_buf%
LDMIA R1,{R2-R3}
STMIA R0,{R2-R3}
SWI "OS_LeaveOS"
MOV PC,R14

.call_count% EQUD 0
.last_call%
.last_R0% EQUD 0
.last_R1% EQUD 0
.last_R2% EQUD 0
.last_R3% EQUD 0
.last_PSR% EQUD 0
.last_R12% EQUD 0

.da_base_ptr% EQUD 0
.da_num_val% EQUD 0

.ldm_buf% EQUD 0 : EQUD 0

.buffer%
]
NEXT pass

seed%=-TIME
PRINT "seed: ";seed%
A%=RND(seed%)

wp%=RND
da_num%=0
at_registered%=FALSE

REM Check for FPA hardware
have_fpa%=((USR read_fpsr%)>>>24) = &81
REM Extended packed decimal in use?
IF (USR read_fpsr%) AND (1<<11) THEN ep_len%=16 ELSE ep_len%=12

IF have_vfp% AND NOT is_basicvfp% THEN
 REM Create our own VFP context
 SYS "VFPSupport_CreateContext",&80000001,max_dregs%,0,0 TO vfp_context%,vfp_context_old%
ELSE
 vfp_context%=0
ENDIF

orig_sctlr% = USR read_sctlr%

ON ERROR PRINT REPORT$;" at ";ERL : PROCend(1)

PRINT "handler: ";~handler%
PRINT "wp: ";~wp%

DIM expected% 16*8

SYS "OS_PlatformFeatures",0 TO plat_features%
IF plat_features% AND 8 THEN str_pc_offset%=8 ELSE str_pc_offset%=12

REM Create a sparse DA
SYS "OS_DynamicArea",0,-1,da_size%,-1,0+(1<<7)+(1<<10),da_size%,0,0,"ATTest" TO ,da_num%,,da_base%

!da_base_ptr%=da_base%
!da_num_val%=da_num%

PRINT "da_base: ";~da_base%

REM Place the test code in the middle of the DA
code% = da_base% + 4096 + 1024

PRINT "code: ";~code%

vfp_scratch%=code% : code%+=32 : REM 256 bit alignment for VLD/VST
in_regs%=code% : code%+=64
out_regs%=code% : code%+=64
scratch%=code% : code%+=8
in_vfp%=code% : code%+=32*8
out_vfp%=code% : code%+=32*8

DIM out_vfp2% 32*8

testcode_start% = da_base%+4096
testcode_end% = da_base%+8192-8 : REM Enough for 2 words of test code
carry_in%=0

FOR pass=0 TO 2 STEP 2
P%=code%
[ OPT pass
MSR CPSR_f,R0
STR R13,scratch%
STR R14,scratch%+4
ADR R0,in_regs%
LDMIA R0,{R0-R14}
LDR pc, testcode_ptr%

.testcode_ptr%
EQUD 0
.ldr_pc_success%
EQUD 0
.out_psr%
EQUD 0

.ldr_pc_success_code%
STR PC,ldr_pc_success%
; Fall through
.aftertest%
STR R0,out_regs%
ADR R0,out_regs%
STMIB R0,{R1-R14}
MRS R0,CPSR
STR R0,out_psr%
MSR CPSR_f,#0
LDR R13,scratch%
LDR PC,scratch%+4

.aftertest_priv%
MSR CPSR_c,#&13 ; Back to SVC
SWI "OS_LeaveOS"
B aftertest%
]

IF have_vfp% THEN
IF max_dregs%>16 THEN
[ OPT pass
.vfp_code%
STMFD R13!,{R14}
ADR R14,in_vfp%
VLDMIA R14!,{D0-D15}
VLDMIA R14,{D16-D31}
BL code%
ADR R14,out_vfp%
VSTMIA R14!,{D0-D15}
VSTMIA R14,{D16-D31}
LDMFD R13!,{PC}
]
ELSE
[ OPT pass
.vfp_code%
STMFD R13!,{R14}
ADR R14,in_vfp%
VLDMIA R14!,{D0-D15}
BL code%
ADR R14,out_vfp%
VSTMIA R14!,{D0-D15}
LDMFD R13!,{PC}
]
ENDIF
ENDIF

[ OPT pass

.fpa_code%
; Disable all exception traps so we can safely load/store complete garbage
RFS R1
STMFD R13!,{R1,R14}
BIC R1,R1,#&FF0000
WFS R1
BL code%
LDMFD R13!,{R1,R14}
WFS R1
MOV PC,R14

.testcode_normal%
]
NEXT pass

REM Fill the first & last pages with test data
PROCfill(da_base%,4096)
PROCfill(da_base%+8192,4096)
test_base%=da_base%

REM Count number of tests
counting%=TRUE
test_count%=0
PROCruntests
counting%=FALSE

REM Run self-tests; the tests target normal RAM (the first and last pages of the DA), to make sure the test code is correctly checking for real-world behaviour of the host CPU
PROCruntests2("Self-tests")

REM Now unmap the first & last pages and register the AbortTrap handler, so we can run the AbortTrap tests against those unmapped regions
SYS "OS_DynamicArea",10,da_num%,da_base%,4096
SYS "OS_DynamicArea",10,da_num%,da_base%+8192,4096

SYS swi$,0,da_base%,da_base%+da_size%,handler%,wp%
at_registered%=TRUE

REM Fill AbortTrap buffer with test data
PROCfill(buffer%,da_size%)
test_base%=buffer%

REM Run the AbortTrap tests; the tests are still targeting the first & last pages of the DA, but this time they're unmapped, causing the AbortTrap handler to be invoked
PROCruntests2("AbortTrap")

PROCend(0)

DEF PROCruntests2(phase1$)
 REM Test all the different alignment modes
 IF can_rotate%=0 AND can_unaligned%=0 AND can_align%=0 THEN
  REM Not allowed to alter alignment settings
  test_idx%=0
  phase$=phase1$
  PROCruntests
  ENDPROC
 ENDIF
 IF can_align% THEN
  A%=orig_sctlr% OR sctlr_a%
  CALL write_sctlr%
  test_idx%=0
  phase$=phase1$+", aligned"
  PROCruntests
 ENDIF
 IF can_rotate% THEN
  A%=orig_sctlr% AND NOT (sctlr_a%+sctlr_u%)
  CALL write_sctlr%
  test_idx%=0
  phase$=phase1$+", rotated"
  PROCruntests
 ENDIF
 IF can_unaligned% THEN
  A%=(orig_sctlr% AND NOT sctlr_a%) OR sctlr_u%
  CALL write_sctlr%
  test_idx%=0
  phase$=phase1$+", unaligned"
  PROCruntests
 ENDIF
ENDPROC

DEF PROCruntests
 PROCtest("FNcheck_ldr(FNldr_imm  ,FALSE,FALSE,FALSE)","")
 PROCtest("FNcheck_ldr(FNldrb_imm ,FALSE,FALSE,FALSE)","")
 PROCtest("FNcheck_ldr(FNldrh_imm ,FALSE,FALSE,FALSE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_ldr(FNldrd_imm ,FALSE,FALSE,FALSE)","LDRD_STRD")
 PROCtest("FNcheck_str(FNstr_imm  ,FALSE,FALSE,FALSE)","")
 PROCtest("FNcheck_str(FNstrb_imm ,FALSE,FALSE,FALSE)","")
 PROCtest("FNcheck_str(FNstrh_imm ,FALSE,FALSE,FALSE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_str(FNstrd_imm ,FALSE,FALSE,FALSE)","LDRD_STRD")
 PROCtest("FNcheck_ldr(FNldrsb_imm,FALSE,FALSE,FALSE)","LDRSB")
 PROCtest("FNcheck_ldr(FNldrsh_imm,FALSE,FALSE,FALSE)","LDRH_LDRSH_STRH")

 PROCtest("FNcheck_ldr(FNldr_imm_wb  ,TRUE,FALSE,FALSE)","")
 PROCtest("FNcheck_ldr(FNldrb_imm_wb ,TRUE,FALSE,FALSE)","")
 PROCtest("FNcheck_ldr(FNldrh_imm_wb ,TRUE,FALSE,FALSE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_ldr(FNldrd_imm_wb ,TRUE,FALSE,FALSE)","LDRD_STRD")
 PROCtest("FNcheck_str(FNstr_imm_wb  ,TRUE,FALSE,FALSE)","")
 PROCtest("FNcheck_str(FNstrb_imm_wb ,TRUE,FALSE,FALSE)","")
 PROCtest("FNcheck_str(FNstrh_imm_wb ,TRUE,FALSE,FALSE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_str(FNstrd_imm_wb ,TRUE,FALSE,FALSE)","LDRD_STRD")
 PROCtest("FNcheck_ldr(FNldrsb_imm_wb,TRUE,FALSE,FALSE)","LDRSB")
 PROCtest("FNcheck_ldr(FNldrsh_imm_wb,TRUE,FALSE,FALSE)","LDRH_LDRSH_STRH")

 PROCtest("FNcheck_ldr(FNldr_imm_post  ,TRUE,TRUE,FALSE)","")
 PROCtest("FNcheck_ldr(FNldrb_imm_post ,TRUE,TRUE,FALSE)","")
 PROCtest("FNcheck_ldr(FNldrh_imm_post ,TRUE,TRUE,FALSE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_ldr(FNldrd_imm_post ,TRUE,TRUE,FALSE)","LDRD_STRD")
 PROCtest("FNcheck_str(FNstr_imm_post  ,TRUE,TRUE,FALSE)","")
 PROCtest("FNcheck_str(FNstrb_imm_post ,TRUE,TRUE,FALSE)","")
 PROCtest("FNcheck_str(FNstrh_imm_post ,TRUE,TRUE,FALSE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_str(FNstrd_imm_post ,TRUE,TRUE,FALSE)","LDRD_STRD")
 PROCtest("FNcheck_ldr(FNldrsb_imm_post,TRUE,TRUE,FALSE)","LDRSB")
 PROCtest("FNcheck_ldr(FNldrsh_imm_post,TRUE,TRUE,FALSE)","LDRH_LDRSH_STRH")

 PROCtest("FNcheck_ldr(FNldr_reg_p        ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_reg_n        ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_LSL_p        ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_LSL_n        ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_LSR_p        ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_LSR_n        ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_ASR_p        ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_ASR_n        ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_ROR_p        ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_ROR_n        ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_RRX_p        ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_RRX_n        ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstr_reg_p        ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstr_reg_n        ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstr_LSL_p        ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstr_LSL_n        ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstr_LSR_p        ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstr_LSR_n        ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstr_ASR_p        ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstr_ASR_n        ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstr_ROR_p        ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstr_ROR_n        ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstr_RRX_p        ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstr_RRX_n        ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_reg_p_wb     ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_reg_n_wb     ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_LSL_p_wb     ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_LSL_n_wb     ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_LSR_p_wb     ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_LSR_n_wb     ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_ASR_p_wb     ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_ASR_n_wb     ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_ROR_p_wb     ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_ROR_n_wb     ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_RRX_p_wb     ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_RRX_n_wb     ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstr_reg_p_wb     ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstr_reg_n_wb     ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstr_LSL_p_wb     ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstr_LSL_n_wb     ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstr_LSR_p_wb     ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstr_LSR_n_wb     ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstr_ASR_p_wb     ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstr_ASR_n_wb     ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstr_ROR_p_wb     ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstr_ROR_n_wb     ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstr_RRX_p_wb     ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstr_RRX_n_wb     ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_reg_p_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_reg_n_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_LSL_p_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_LSL_n_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_LSR_p_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_LSR_n_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_ASR_p_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_ASR_n_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_ROR_p_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_ROR_n_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_RRX_p_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldr_RRX_n_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstr_reg_p_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstr_reg_n_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstr_LSL_p_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstr_LSL_n_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstr_LSR_p_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstr_LSR_n_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstr_ASR_p_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstr_ASR_n_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstr_ROR_p_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstr_ROR_n_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstr_RRX_p_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstr_RRX_n_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_reg_p       ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_reg_n       ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_LSL_p       ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_LSL_n       ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_LSR_p       ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_LSR_n       ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_ASR_p       ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_ASR_n       ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_ROR_p       ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_ROR_n       ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_RRX_p       ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_RRX_n       ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_reg_p       ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_reg_n       ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_LSL_p       ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_LSL_n       ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_LSR_p       ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_LSR_n       ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_ASR_p       ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_ASR_n       ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_ROR_p       ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_ROR_n       ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_RRX_p       ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_RRX_n       ,FALSE,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_reg_p_wb    ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_reg_n_wb    ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_LSL_p_wb    ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_LSL_n_wb    ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_LSR_p_wb    ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_LSR_n_wb    ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_ASR_p_wb    ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_ASR_n_wb    ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_ROR_p_wb    ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_ROR_n_wb    ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_RRX_p_wb    ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_RRX_n_wb    ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_reg_p_wb    ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_reg_n_wb    ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_LSL_p_wb    ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_LSL_n_wb    ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_LSR_p_wb    ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_LSR_n_wb    ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_ASR_p_wb    ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_ASR_n_wb    ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_ROR_p_wb    ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_ROR_n_wb    ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_RRX_p_wb    ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_RRX_n_wb    ,TRUE ,FALSE,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_reg_p_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_reg_n_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_LSL_p_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_LSL_n_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_LSR_p_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_LSR_n_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_ASR_p_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_ASR_n_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_ROR_p_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_ROR_n_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_RRX_p_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrb_RRX_n_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_reg_p_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_reg_n_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_LSL_p_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_LSL_n_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_LSR_p_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_LSR_n_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_ASR_p_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_ASR_n_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_ROR_p_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_ROR_n_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_RRX_p_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrb_RRX_n_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrh_reg_p       ,FALSE,FALSE,TRUE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_ldr(FNldrh_reg_n       ,FALSE,FALSE,TRUE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_ldr(FNldrh_reg_p_wb    ,TRUE ,FALSE,TRUE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_ldr(FNldrh_reg_n_wb    ,TRUE ,FALSE,TRUE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_ldr(FNldrh_reg_p_post  ,TRUE ,TRUE ,TRUE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_ldr(FNldrh_reg_n_post  ,TRUE ,TRUE ,TRUE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_str(FNstrh_reg_p       ,FALSE,FALSE,TRUE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_str(FNstrh_reg_n       ,FALSE,FALSE,TRUE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_str(FNstrh_reg_p_wb    ,TRUE ,FALSE,TRUE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_str(FNstrh_reg_n_wb    ,TRUE ,FALSE,TRUE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_str(FNstrh_reg_p_post  ,TRUE ,TRUE ,TRUE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_str(FNstrh_reg_n_post  ,TRUE ,TRUE ,TRUE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_ldr(FNldrsb_reg_p      ,FALSE,FALSE,TRUE)","LDRSB")
 PROCtest("FNcheck_ldr(FNldrsb_reg_n      ,FALSE,FALSE,TRUE)","LDRSB")
 PROCtest("FNcheck_ldr(FNldrsb_reg_p_wb   ,TRUE ,FALSE,TRUE)","LDRSB")
 PROCtest("FNcheck_ldr(FNldrsb_reg_n_wb   ,TRUE ,FALSE,TRUE)","LDRSB")
 PROCtest("FNcheck_ldr(FNldrsb_reg_p_post ,TRUE ,TRUE ,TRUE)","LDRSB")
 PROCtest("FNcheck_ldr(FNldrsb_reg_n_post ,TRUE ,TRUE ,TRUE)","LDRSB")
 PROCtest("FNcheck_ldr(FNldrsh_reg_p      ,FALSE,FALSE,TRUE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_ldr(FNldrsh_reg_n      ,FALSE,FALSE,TRUE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_ldr(FNldrsh_reg_p_wb   ,TRUE ,FALSE,TRUE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_ldr(FNldrsh_reg_n_wb   ,TRUE ,FALSE,TRUE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_ldr(FNldrsh_reg_p_post ,TRUE ,TRUE ,TRUE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_ldr(FNldrsh_reg_n_post ,TRUE ,TRUE ,TRUE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_ldr(FNldrd_reg_p       ,FALSE,FALSE,TRUE)","LDRD_STRD")
 PROCtest("FNcheck_ldr(FNldrd_reg_n       ,FALSE,FALSE,TRUE)","LDRD_STRD")
 PROCtest("FNcheck_ldr(FNldrd_reg_p_wb    ,TRUE ,FALSE,TRUE)","LDRD_STRD")
 PROCtest("FNcheck_ldr(FNldrd_reg_n_wb    ,TRUE ,FALSE,TRUE)","LDRD_STRD")
 PROCtest("FNcheck_ldr(FNldrd_reg_p_post  ,TRUE ,TRUE ,TRUE)","LDRD_STRD")
 PROCtest("FNcheck_ldr(FNldrd_reg_n_post  ,TRUE ,TRUE ,TRUE)","LDRD_STRD")
 PROCtest("FNcheck_str(FNstrd_reg_p       ,FALSE,FALSE,TRUE)","LDRD_STRD")
 PROCtest("FNcheck_str(FNstrd_reg_n       ,FALSE,FALSE,TRUE)","LDRD_STRD")
 PROCtest("FNcheck_str(FNstrd_reg_p_wb    ,TRUE ,FALSE,TRUE)","LDRD_STRD")
 PROCtest("FNcheck_str(FNstrd_reg_n_wb    ,TRUE ,FALSE,TRUE)","LDRD_STRD")
 PROCtest("FNcheck_str(FNstrd_reg_p_post  ,TRUE ,TRUE ,TRUE)","LDRD_STRD")
 PROCtest("FNcheck_str(FNstrd_reg_n_post  ,TRUE ,TRUE ,TRUE)","LDRD_STRD")

 PROCtest("FNcheck_ldr(FNldr_lit  ,FALSE,FALSE,FALSE)","")
 PROCtest("FNcheck_str(FNstr_lit  ,FALSE,FALSE,FALSE)","")
 PROCtest("FNcheck_ldr(FNldrb_lit ,FALSE,FALSE,FALSE)","")
 PROCtest("FNcheck_str(FNstrb_lit ,FALSE,FALSE,FALSE)","")
 PROCtest("FNcheck_ldr(FNldrh_lit ,FALSE,FALSE,FALSE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_str(FNstrh_lit ,FALSE,FALSE,FALSE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_ldr(FNldrsb_lit,FALSE,FALSE,FALSE)","LDRSB")
 PROCtest("FNcheck_ldr(FNldrsh_lit,FALSE,FALSE,FALSE)","LDRH_LDRSH_STRH")
 PROCtest("FNcheck_ldr(FNldrd_lit ,FALSE,FALSE,FALSE)","LDRD_STRD")
 PROCtest("FNcheck_str(FNstrd_lit ,FALSE,FALSE,FALSE)","LDRD_STRD")

 REM                               Inc   After WBack
 PROCtest("FNcheck_ldm(FNldmia    ,TRUE ,TRUE ,FALSE)","")
 PROCtest("FNcheck_stm(FNstmia    ,TRUE ,TRUE ,FALSE)","")
 PROCtest("FNcheck_ldm(FNldmib    ,TRUE ,FALSE,FALSE)","")
 PROCtest("FNcheck_stm(FNstmib    ,TRUE ,FALSE,FALSE)","")
 PROCtest("FNcheck_ldm(FNldmda    ,FALSE,TRUE ,FALSE)","")
 PROCtest("FNcheck_stm(FNstmda    ,FALSE,TRUE ,FALSE)","")
 PROCtest("FNcheck_ldm(FNldmdb    ,FALSE,FALSE,FALSE)","")
 PROCtest("FNcheck_stm(FNstmdb    ,FALSE,FALSE,FALSE)","")
 PROCtest("FNcheck_ldm(FNldmia_wb ,TRUE ,TRUE ,TRUE )","")
 PROCtest("FNcheck_stm(FNstmia_wb ,TRUE ,TRUE ,TRUE )","")
 PROCtest("FNcheck_ldm(FNldmib_wb ,TRUE ,FALSE,TRUE )","")
 PROCtest("FNcheck_stm(FNstmib_wb ,TRUE ,FALSE,TRUE )","")
 PROCtest("FNcheck_ldm(FNldmda_wb ,FALSE,TRUE ,TRUE )","")
 PROCtest("FNcheck_stm(FNstmda_wb ,FALSE,TRUE ,TRUE )","")
 PROCtest("FNcheck_ldm(FNldmdb_wb ,FALSE,FALSE,TRUE )","")
 PROCtest("FNcheck_stm(FNstmdb_wb ,FALSE,FALSE,TRUE )","")
 PROCtest("FNcheck_ldm(FNldmia_usr,TRUE ,TRUE ,FALSE)","")
 PROCtest("FNcheck_stm(FNstmia_usr,TRUE ,TRUE ,FALSE)","")
 PROCtest("FNcheck_ldm(FNldmib_usr,TRUE ,FALSE,FALSE)","")
 PROCtest("FNcheck_stm(FNstmib_usr,TRUE ,FALSE,FALSE)","")
 PROCtest("FNcheck_ldm(FNldmda_usr,FALSE,TRUE ,FALSE)","")
 PROCtest("FNcheck_stm(FNstmda_usr,FALSE,TRUE ,FALSE)","")
 PROCtest("FNcheck_ldm(FNldmdb_usr,FALSE,FALSE,FALSE)","")
 PROCtest("FNcheck_stm(FNstmdb_usr,FALSE,FALSE,FALSE)","")

 PROCtest("FNcheck_vldr(FNvldrs_imm)","VFP")
 PROCtest("FNcheck_vldr(FNvldrd_imm)","VFP")
 PROCtest("FNcheck_vstr(FNvstrs_imm)","VFP")
 PROCtest("FNcheck_vstr(FNvstrd_imm)","VFP")
 PROCtest("FNcheck_vldr(FNvldrs_lit)","VFP")
 PROCtest("FNcheck_vldr(FNvldrd_lit)","VFP")
 PROCtest("FNcheck_vstr(FNvstrs_lit)","VFP")
 PROCtest("FNcheck_vstr(FNvstrd_lit)","VFP")

 REM                                  Inc   WBack
 PROCtest("FNcheck_vldm(FNvldmia_s   ,TRUE ,FALSE)","VFP")
 PROCtest("FNcheck_vldm(FNvldmia_d   ,TRUE ,FALSE)","VFP")
 PROCtest("FNcheck_vldm(FNfldmia_x   ,TRUE ,FALSE)","VFP")
 PROCtest("FNcheck_vldm(FNvldmia_s_wb,TRUE ,TRUE )","VFP")
 PROCtest("FNcheck_vldm(FNvldmia_d_wb,TRUE ,TRUE )","VFP")
 PROCtest("FNcheck_vldm(FNfldmia_x_wb,TRUE ,TRUE )","VFP")
 PROCtest("FNcheck_vldm(FNvldmdb_s_wb,FALSE,TRUE )","VFP")
 PROCtest("FNcheck_vldm(FNvldmdb_d_wb,FALSE,TRUE )","VFP")
 PROCtest("FNcheck_vldm(FNfldmdb_x_wb,FALSE,TRUE )","VFP")
 PROCtest("FNcheck_vstm(FNvstmia_s   ,TRUE ,FALSE)","VFP")
 PROCtest("FNcheck_vstm(FNvstmia_d   ,TRUE ,FALSE)","VFP")
 PROCtest("FNcheck_vstm(FNfstmia_x   ,TRUE ,FALSE)","VFP")
 PROCtest("FNcheck_vstm(FNvstmia_s_wb,TRUE ,TRUE )","VFP")
 PROCtest("FNcheck_vstm(FNvstmia_d_wb,TRUE ,TRUE )","VFP")
 PROCtest("FNcheck_vstm(FNfstmia_x_wb,TRUE ,TRUE )","VFP")
 PROCtest("FNcheck_vstm(FNvstmdb_s_wb,FALSE,TRUE )","VFP")
 PROCtest("FNcheck_vstm(FNvstmdb_d_wb,FALSE,TRUE )","VFP")
 PROCtest("FNcheck_vstm(FNfstmdb_x_wb,FALSE,TRUE )","VFP")

 PROCtest("FNcheck_vldst(""FNvld1_mult_08_1_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_1_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_1_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_1_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_1_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_1_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_2_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_2_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_2_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_2_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_2_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_2_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_3_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_3_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_3_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_3_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_3_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_3_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_4_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_4_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_4_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_4_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_4_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_4_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_4_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_4_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_08_4_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_1_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_1_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_1_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_1_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_1_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_1_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_2_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_2_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_2_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_2_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_2_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_2_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_3_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_3_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_3_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_3_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_3_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_3_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_4_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_4_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_4_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_4_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_4_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_4_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_4_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_4_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_16_4_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_1_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_1_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_1_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_1_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_1_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_1_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_2_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_2_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_2_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_2_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_2_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_2_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_3_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_3_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_3_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_3_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_3_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_3_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_4_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_4_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_4_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_4_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_4_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_4_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_4_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_4_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_32_4_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_1_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_1_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_1_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_1_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_1_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_1_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_2_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_2_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_2_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_2_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_2_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_2_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_3_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_3_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_3_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_3_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_3_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_3_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_4_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_4_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_4_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_4_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_4_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_4_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_4_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_4_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_mult_64_4_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_1_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_1_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_1_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_1_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_1_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_1_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_2_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_2_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_2_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_2_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_2_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_2_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_3_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_3_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_3_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_3_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_3_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_3_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_4_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_4_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_4_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_4_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_4_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_4_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_4_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_4_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_08_4_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_1_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_1_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_1_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_1_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_1_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_1_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_2_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_2_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_2_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_2_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_2_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_2_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_3_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_3_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_3_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_3_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_3_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_3_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_4_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_4_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_4_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_4_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_4_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_4_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_4_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_4_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_16_4_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_1_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_1_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_1_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_1_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_1_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_1_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_2_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_2_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_2_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_2_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_2_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_2_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_3_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_3_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_3_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_3_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_3_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_3_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_4_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_4_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_4_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_4_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_4_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_4_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_4_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_4_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_32_4_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_1_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_1_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_1_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_1_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_1_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_1_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_2_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_2_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_2_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_2_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_2_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_2_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_3_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_3_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_3_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_3_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_3_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_3_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_4_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_4_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_4_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_4_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_4_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_4_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_4_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_4_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_mult_64_4_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_2_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_2_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_2_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_2_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_2_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_2_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_d_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_d_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_d_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_4_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_4_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_4_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_4_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_4_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_4_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_4_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_4_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_08_4_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_2_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_2_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_2_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_2_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_2_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_2_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_d_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_d_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_d_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_4_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_4_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_4_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_4_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_4_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_4_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_4_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_4_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_16_4_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_2_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_2_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_2_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_2_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_2_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_2_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_d_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_d_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_d_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_4_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_4_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_4_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_4_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_4_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_4_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_4_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_4_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_mult_32_4_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_2_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_2_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_2_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_2_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_2_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_2_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_d_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_d_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_d_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_4_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_4_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_4_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_4_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_4_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_4_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_4_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_4_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_08_4_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_2_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_2_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_2_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_2_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_2_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_2_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_d_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_d_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_d_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_4_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_4_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_4_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_4_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_4_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_4_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_4_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_4_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_16_4_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_2_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_2_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_2_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_2_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_2_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_2_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_d_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_d_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_d_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_4_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_4_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_4_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_4_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_4_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_4_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_4_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_4_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_mult_32_4_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_08_3_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_08_3_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_08_3_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_08_3_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_08_3_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_08_3_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_08_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_08_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_08_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_08_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_08_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_08_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_16_3_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_16_3_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_16_3_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_16_3_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_16_3_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_16_3_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_16_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_16_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_16_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_16_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_16_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_16_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_32_3_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_32_3_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_32_3_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_32_3_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_32_3_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_32_3_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_32_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_32_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_32_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_32_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_32_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_mult_32_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_08_3_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_08_3_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_08_3_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_08_3_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_08_3_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_08_3_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_08_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_08_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_08_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_08_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_08_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_08_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_16_3_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_16_3_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_16_3_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_16_3_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_16_3_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_16_3_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_16_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_16_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_16_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_16_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_16_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_16_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_32_3_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_32_3_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_32_3_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_32_3_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_32_3_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_32_3_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_32_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_32_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_32_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_32_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_32_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_mult_32_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_08_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_08_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_08_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_08_4_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_08_4_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_08_4_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_08_4_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_08_4_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_08_4_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_08_4_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_08_4_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_08_4_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_08_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_08_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_08_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_08_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_08_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_08_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_08_d_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_08_d_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_08_d_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_08_d_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_08_d_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_08_d_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_16_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_16_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_16_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_16_4_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_16_4_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_16_4_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_16_4_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_16_4_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_16_4_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_16_4_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_16_4_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_16_4_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_16_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_16_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_16_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_16_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_16_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_16_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_16_d_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_16_d_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_16_d_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_16_d_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_16_d_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_16_d_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_32_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_32_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_32_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_32_4_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_32_4_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_32_4_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_32_4_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_32_4_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_32_4_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_32_4_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_32_4_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_32_4_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_32_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_32_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_32_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_32_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_32_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_32_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_32_d_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_32_d_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_32_d_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_32_d_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_32_d_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_mult_32_d_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_08_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_08_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_08_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_08_4_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_08_4_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_08_4_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_08_4_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_08_4_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_08_4_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_08_4_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_08_4_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_08_4_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_08_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_08_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_08_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_08_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_08_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_08_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_08_d_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_08_d_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_08_d_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_08_d_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_08_d_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_08_d_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_16_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_16_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_16_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_16_4_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_16_4_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_16_4_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_16_4_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_16_4_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_16_4_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_16_4_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_16_4_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_16_4_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_16_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_16_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_16_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_16_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_16_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_16_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_16_d_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_16_d_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_16_d_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_16_d_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_16_d_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_16_d_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_32_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_32_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_32_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_32_4_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_32_4_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_32_4_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_32_4_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_32_4_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_32_4_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_32_4_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_32_4_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_32_4_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_32_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_32_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_32_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_32_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_32_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_32_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_32_d_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_32_d_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_32_d_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_32_d_256   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_32_d_256_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_mult_32_d_256_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_lane_08_1_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_lane_08_1_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_lane_08_1_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_lane_16_1_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_lane_16_1_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_lane_16_1_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_lane_16_1_016   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_lane_16_1_016_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_lane_16_1_016_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_lane_32_1_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_lane_32_1_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_lane_32_1_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_lane_32_1_032   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_lane_32_1_032_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_lane_32_1_032_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_lane_08_1_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_lane_08_1_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_lane_08_1_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_lane_16_1_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_lane_16_1_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_lane_16_1_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_lane_16_1_016   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_lane_16_1_016_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_lane_16_1_016_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_lane_32_1_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_lane_32_1_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_lane_32_1_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_lane_32_1_032   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_lane_32_1_032_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst1_lane_32_1_032_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_08_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_08_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_08_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_08_2_016   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_08_2_016_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_08_2_016_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_16_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_16_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_16_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_16_2_032   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_16_2_032_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_16_2_032_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_32_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_32_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_32_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_32_2_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_32_2_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_32_2_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_16_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_16_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_16_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_16_d_032   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_16_d_032_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_16_d_032_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_32_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_32_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_32_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_32_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_32_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_lane_32_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_08_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_08_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_08_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_08_2_016   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_08_2_016_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_08_2_016_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_16_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_16_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_16_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_16_2_032   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_16_2_032_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_16_2_032_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_32_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_32_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_32_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_32_2_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_32_2_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_32_2_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_16_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_16_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_16_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_16_d_032   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_16_d_032_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_16_d_032_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_32_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_32_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_32_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_32_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_32_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst2_lane_32_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_lane_08_3_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_lane_08_3_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_lane_08_3_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_lane_16_3_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_lane_16_3_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_lane_16_3_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_lane_16_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_lane_16_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_lane_16_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_lane_32_3_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_lane_32_3_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_lane_32_3_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_lane_32_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_lane_32_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_lane_32_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_lane_08_3_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_lane_08_3_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_lane_08_3_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_lane_16_3_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_lane_16_3_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_lane_16_3_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_lane_16_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_lane_16_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_lane_16_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_lane_32_3_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_lane_32_3_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_lane_32_3_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_lane_32_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_lane_32_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst3_lane_32_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_08_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_08_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_08_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_08_4_032   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_08_4_032_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_08_4_032_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_16_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_16_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_16_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_16_4_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_16_4_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_16_4_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_16_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_16_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_16_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_16_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_16_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_16_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_32_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_32_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_32_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_32_4_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_32_4_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_32_4_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_32_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_32_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_32_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_32_d_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_32_d_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_lane_32_d_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_08_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_08_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_08_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_08_4_032   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_08_4_032_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_08_4_032_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_16_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_16_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_16_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_16_4_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_16_4_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_16_4_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_16_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_16_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_16_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_16_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_16_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_16_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_32_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_32_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_32_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_32_4_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_32_4_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_32_4_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_32_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_32_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_32_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_32_d_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_32_d_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvst4_lane_32_d_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_08_1_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_08_1_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_08_1_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_08_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_08_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_08_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_16_1_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_16_1_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_16_1_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_16_1_016   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_16_1_016_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_16_1_016_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_16_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_16_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_16_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_16_2_016   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_16_2_016_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_16_2_016_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_32_1_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_32_1_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_32_1_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_32_1_032   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_32_1_032_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_32_1_032_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_32_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_32_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_32_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_32_2_032   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_32_2_032_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld1_repl_32_2_032_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_08_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_08_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_08_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_08_2_016   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_08_2_016_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_08_2_016_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_08_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_08_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_08_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_08_d_016   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_08_d_016_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_08_d_016_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_16_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_16_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_16_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_16_2_032   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_16_2_032_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_16_2_032_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_16_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_16_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_16_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_16_d_032   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_16_d_032_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_16_d_032_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_32_2_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_32_2_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_32_2_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_32_2_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_32_2_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_32_2_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_32_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_32_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_32_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_32_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_32_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld2_repl_32_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_repl_08_3_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_repl_08_3_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_repl_08_3_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_repl_08_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_repl_08_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_repl_08_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_repl_16_3_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_repl_16_3_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_repl_16_3_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_repl_16_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_repl_16_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_repl_16_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_repl_32_3_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_repl_32_3_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_repl_32_3_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_repl_32_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_repl_32_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld3_repl_32_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_08_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_08_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_08_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_08_4_032   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_08_4_032_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_08_4_032_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_08_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_08_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_08_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_08_d_032   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_08_d_032_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_08_d_032_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_16_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_16_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_16_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_16_4_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_16_4_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_16_4_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_16_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_16_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_16_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_16_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_16_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_16_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_32_4_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_32_4_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_32_4_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_32_4_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_32_4_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_32_4_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_32_4_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_32_4_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_32_4_128_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_32_d_xxx   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_32_d_xxx_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_32_d_xxx_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_32_d_064   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_32_d_064_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_32_d_064_rm"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_32_d_128   "")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_32_d_128_wb"")","NEON")
 PROCtest("FNcheck_vldst(""FNvld4_repl_32_d_128_rm"")","NEON")

 PROCtest("FNcheck_swp(FNswp)","SWP_SWPB")
 PROCtest("FNcheck_swp(FNswpb)","SWP_SWPB")

 REM                                  Inc   After WBack
 PROCtest("FNcheck_srs(FNsrsia_usr   ,TRUE ,TRUE ,FALSE)","SRS_RFE_CPS")
 PROCtest("FNcheck_srs(FNsrsib_usr   ,TRUE ,FALSE,FALSE)","SRS_RFE_CPS")
 PROCtest("FNcheck_srs(FNsrsda_usr   ,FALSE,TRUE ,FALSE)","SRS_RFE_CPS")
 PROCtest("FNcheck_srs(FNsrsdb_usr   ,FALSE,FALSE,FALSE)","SRS_RFE_CPS")
 PROCtest("FNcheck_srs(FNsrsia_usr_wb,TRUE ,TRUE ,TRUE )","SRS_RFE_CPS")
 PROCtest("FNcheck_srs(FNsrsib_usr_wb,TRUE ,FALSE,TRUE )","SRS_RFE_CPS")
 PROCtest("FNcheck_srs(FNsrsda_usr_wb,FALSE,TRUE ,TRUE )","SRS_RFE_CPS")
 PROCtest("FNcheck_srs(FNsrsdb_usr_wb,FALSE,FALSE,TRUE )","SRS_RFE_CPS")

 REM For exception return LDM we can just use the regular LDM check function (our exception return test code is relatively tame)
 REM                                  Inc   After WBack
 PROCtest("FNcheck_ldm(FNldmia_exc   ,TRUE ,TRUE ,FALSE)","")
 PROCtest("FNcheck_ldm(FNldmib_exc   ,TRUE ,FALSE,FALSE)","")
 PROCtest("FNcheck_ldm(FNldmda_exc   ,FALSE,TRUE ,FALSE)","")
 PROCtest("FNcheck_ldm(FNldmdb_exc   ,FALSE,FALSE,FALSE)","")
 PROCtest("FNcheck_ldm(FNldmia_exc_wb,TRUE ,TRUE ,TRUE )","")
 PROCtest("FNcheck_ldm(FNldmib_exc_wb,TRUE ,FALSE,TRUE )","")
 PROCtest("FNcheck_ldm(FNldmda_exc_wb,FALSE,TRUE ,TRUE )","")
 PROCtest("FNcheck_ldm(FNldmdb_exc_wb,FALSE,FALSE,TRUE )","")

 REM                                  Inc   After WBack
 PROCtest("FNcheck_rfe(FNrfeia_sys   ,TRUE ,TRUE ,FALSE)","SRS_RFE_CPS")
 PROCtest("FNcheck_rfe(FNrfeib_sys   ,TRUE ,FALSE,FALSE)","SRS_RFE_CPS")
 PROCtest("FNcheck_rfe(FNrfeda_sys   ,FALSE,TRUE ,FALSE)","SRS_RFE_CPS")
 PROCtest("FNcheck_rfe(FNrfedb_sys   ,FALSE,FALSE,FALSE)","SRS_RFE_CPS")
 PROCtest("FNcheck_rfe(FNrfeia_sys_wb,TRUE ,TRUE ,TRUE )","SRS_RFE_CPS")
 PROCtest("FNcheck_rfe(FNrfeib_sys_wb,TRUE ,FALSE,TRUE )","SRS_RFE_CPS")
 PROCtest("FNcheck_rfe(FNrfeda_sys_wb,FALSE,TRUE ,TRUE )","SRS_RFE_CPS")
 PROCtest("FNcheck_rfe(FNrfedb_sys_wb,FALSE,FALSE,TRUE )","SRS_RFE_CPS")

 PROCtest("FNcheck_ldr(FNldrt_imm_post  ,TRUE,TRUE,FALSE)","")
 PROCtest("FNcheck_ldr(FNldrbt_imm_post ,TRUE,TRUE,FALSE)","")
 PROCtest("FNcheck_ldr(FNldrht_imm_post ,TRUE,TRUE,FALSE)","LDRHT_LDRSBT_LDRSHT_STRHT")
 PROCtest("FNcheck_str(FNstrt_imm_post  ,TRUE,TRUE,FALSE)","")
 PROCtest("FNcheck_str(FNstrbt_imm_post ,TRUE,TRUE,FALSE)","")
 PROCtest("FNcheck_str(FNstrht_imm_post ,TRUE,TRUE,FALSE)","LDRHT_LDRSBT_LDRSHT_STRHT")
 PROCtest("FNcheck_ldr(FNldrsbt_imm_post,TRUE,TRUE,FALSE)","LDRHT_LDRSBT_LDRSHT_STRHT")
 PROCtest("FNcheck_ldr(FNldrsht_imm_post,TRUE,TRUE,FALSE)","LDRHT_LDRSBT_LDRSHT_STRHT")

 PROCtest("FNcheck_ldr(FNldrt_reg_p_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrt_reg_n_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrt_LSL_p_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrt_LSL_n_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrt_LSR_p_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrt_LSR_n_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrt_ASR_p_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrt_ASR_n_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrt_ROR_p_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrt_ROR_n_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrt_RRX_p_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrt_RRX_n_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrt_reg_p_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrt_reg_n_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrt_LSL_p_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrt_LSL_n_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrt_LSR_p_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrt_LSR_n_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrt_ASR_p_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrt_ASR_n_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrt_ROR_p_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrt_ROR_n_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrt_RRX_p_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrt_RRX_n_post   ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrbt_reg_p_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrbt_reg_n_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrbt_LSL_p_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrbt_LSL_n_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrbt_LSR_p_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrbt_LSR_n_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrbt_ASR_p_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrbt_ASR_n_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrbt_ROR_p_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrbt_ROR_n_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrbt_RRX_p_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrbt_RRX_n_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrbt_reg_p_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrbt_reg_n_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrbt_LSL_p_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrbt_LSL_n_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrbt_LSR_p_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrbt_LSR_n_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrbt_ASR_p_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrbt_ASR_n_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrbt_ROR_p_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrbt_ROR_n_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrbt_RRX_p_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_str(FNstrbt_RRX_n_post  ,TRUE ,TRUE ,TRUE)","")
 PROCtest("FNcheck_ldr(FNldrht_reg_p_post  ,TRUE ,TRUE ,TRUE)","LDRHT_LDRSBT_LDRSHT_STRHT")
 PROCtest("FNcheck_ldr(FNldrht_reg_n_post  ,TRUE ,TRUE ,TRUE)","LDRHT_LDRSBT_LDRSHT_STRHT")
 PROCtest("FNcheck_str(FNstrht_reg_p_post  ,TRUE ,TRUE ,TRUE)","LDRHT_LDRSBT_LDRSHT_STRHT")
 PROCtest("FNcheck_str(FNstrht_reg_n_post  ,TRUE ,TRUE ,TRUE)","LDRHT_LDRSBT_LDRSHT_STRHT")
 PROCtest("FNcheck_ldr(FNldrsbt_reg_p_post ,TRUE ,TRUE ,TRUE)","LDRHT_LDRSBT_LDRSHT_STRHT")
 PROCtest("FNcheck_ldr(FNldrsbt_reg_n_post ,TRUE ,TRUE ,TRUE)","LDRHT_LDRSBT_LDRSHT_STRHT")
 PROCtest("FNcheck_ldr(FNldrsht_reg_p_post ,TRUE ,TRUE ,TRUE)","LDRHT_LDRSBT_LDRSHT_STRHT")
 PROCtest("FNcheck_ldr(FNldrsht_reg_n_post ,TRUE ,TRUE ,TRUE)","LDRHT_LDRSBT_LDRSHT_STRHT")

 PROCtest("FNcheck_ldrex(FNldrexU ,%000110)","LDREX_STREX")
 PROCtest("FNcheck_ldrex(FNldrexUb,%000110)","CLREX_LDREXB_LDREXH_STREXB_STREXH")
 PROCtest("FNcheck_ldrex(FNldrexUd,%000110)","LDREXD_STREXD")
 PROCtest("FNcheck_ldrex(FNldrexUh,%000110)","CLREX_LDREXB_LDREXH_STREXB_STREXH")
 PROCtest("FNcheck_strex(FNstrexU ,%000110)","LDREX_STREX")
 PROCtest("FNcheck_strex(FNstrexUb,%000110)","CLREX_LDREXB_LDREXH_STREXB_STREXH")
 PROCtest("FNcheck_strex(FNstrexUd,%000110)","LDREXD_STREXD")
 PROCtest("FNcheck_strex(FNstrexUh,%000110)","CLREX_LDREXB_LDREXH_STREXB_STREXH")
 PROCtest("FNcheck_ldrex(FNldrexP ,%110000)","LDREX_STREX")
 PROCtest("FNcheck_ldrex(FNldrexPb,%110000)","CLREX_LDREXB_LDREXH_STREXB_STREXH")
 PROCtest("FNcheck_ldrex(FNldrexPd,%110000)","LDREXD_STREXD")
 PROCtest("FNcheck_ldrex(FNldrexPh,%110000)","CLREX_LDREXB_LDREXH_STREXB_STREXH")
 PROCtest("FNcheck_strex(FNstrexP ,%110000)","LDREX_STREX")
 PROCtest("FNcheck_strex(FNstrexPb,%110000)","CLREX_LDREXB_LDREXH_STREXB_STREXH")
 PROCtest("FNcheck_strex(FNstrexPd,%110000)","LDREXD_STREXD")
 PROCtest("FNcheck_strex(FNstrexPh,%110000)","CLREX_LDREXB_LDREXH_STREXB_STREXH")

 PROCtest("FNcheck_ldrex(FNldaexU ,%000110)","LDAx_STLx")
 PROCtest("FNcheck_ldrex(FNldaexUb,%000110)","LDAx_STLx")
 PROCtest("FNcheck_ldrex(FNldaexUd,%000110)","LDAx_STLx")
 PROCtest("FNcheck_ldrex(FNldaexUh,%000110)","LDAx_STLx")
 PROCtest("FNcheck_strex(FNstlexU ,%000110)","LDAx_STLx")
 PROCtest("FNcheck_strex(FNstlexUb,%000110)","LDAx_STLx")
 PROCtest("FNcheck_strex(FNstlexUd,%000110)","LDAx_STLx")
 PROCtest("FNcheck_strex(FNstlexUh,%000110)","LDAx_STLx")
 PROCtest("FNcheck_ldrex(FNldaexP ,%110000)","LDAx_STLx")
 PROCtest("FNcheck_ldrex(FNldaexPb,%110000)","LDAx_STLx")
 PROCtest("FNcheck_ldrex(FNldaexPd,%110000)","LDAx_STLx")
 PROCtest("FNcheck_ldrex(FNldaexPh,%110000)","LDAx_STLx")
 PROCtest("FNcheck_strex(FNstlexP ,%110000)","LDAx_STLx")
 PROCtest("FNcheck_strex(FNstlexPb,%110000)","LDAx_STLx")
 PROCtest("FNcheck_strex(FNstlexPd,%110000)","LDAx_STLx")
 PROCtest("FNcheck_strex(FNstlexPh,%110000)","LDAx_STLx")

 PROCtest("FNcheck_ldrex(FNldaU ,  %000100)","LDAx_STLx")
 PROCtest("FNcheck_ldrex(FNldaUb,  %000100)","LDAx_STLx")
 PROCtest("FNcheck_ldrex(FNldaUh,  %000100)","LDAx_STLx")
 PROCtest("FNcheck_stl(  FNstlU ,  %000010)","LDAx_STLx")
 PROCtest("FNcheck_stl(  FNstlUb,  %000010)","LDAx_STLx")
 PROCtest("FNcheck_stl(  FNstlUh,  %000010)","LDAx_STLx")
 PROCtest("FNcheck_ldrex(FNldaP ,  %100000)","LDAx_STLx")
 PROCtest("FNcheck_ldrex(FNldaPb,  %100000)","LDAx_STLx")
 PROCtest("FNcheck_ldrex(FNldaPh,  %100000)","LDAx_STLx")
 PROCtest("FNcheck_stl(  FNstlP ,  %010000)","LDAx_STLx")
 PROCtest("FNcheck_stl(  FNstlPb,  %010000)","LDAx_STLx")
 PROCtest("FNcheck_stl(  FNstlPh,  %010000)","LDAx_STLx")

 REM                               WBack Post
 PROCtest("FNcheck_fpa(FNldfs_pre ,FALSE,FALSE,%000100)","")
 PROCtest("FNcheck_fpa(FNldfd_pre ,FALSE,FALSE,%000100)","")
 PROCtest("FNcheck_fpa(FNldfe_pre ,FALSE,FALSE,%000100)","")
 PROCtest("FNcheck_fpa(FNldfp_pre ,FALSE,FALSE,%000100)","FPE438") : REM Avoid FPEmulator LDFP infinite loop bug on pre-4.38
 PROCtest("FNcheck_fpa(FNldfs_wb  ,TRUE ,FALSE,%000100)","")
 PROCtest("FNcheck_fpa(FNldfd_wb  ,TRUE ,FALSE,%000100)","")
 PROCtest("FNcheck_fpa(FNldfe_wb  ,TRUE ,FALSE,%000100)","")
 PROCtest("FNcheck_fpa(FNldfp_wb  ,TRUE ,FALSE,%000100)","FPE438")
 PROCtest("FNcheck_fpa(FNldfs_post,TRUE ,TRUE ,%000100)","")
 PROCtest("FNcheck_fpa(FNldfd_post,TRUE ,TRUE ,%000100)","")
 PROCtest("FNcheck_fpa(FNldfe_post,TRUE ,TRUE ,%000100)","")
 PROCtest("FNcheck_fpa(FNldfp_post,TRUE ,TRUE ,%000100)","FPE438")
 PROCtest("FNcheck_fpa(FNstfs_pre ,FALSE,FALSE,%000010)","")
 PROCtest("FNcheck_fpa(FNstfd_pre ,FALSE,FALSE,%000010)","")
 PROCtest("FNcheck_fpa(FNstfe_pre ,FALSE,FALSE,%000010)","")
 PROCtest("FNcheck_fpa(FNstfp_pre ,FALSE,FALSE,%000010)","")
 PROCtest("FNcheck_fpa(FNstfs_wb  ,TRUE ,FALSE,%000010)","")
 PROCtest("FNcheck_fpa(FNstfd_wb  ,TRUE ,FALSE,%000010)","")
 PROCtest("FNcheck_fpa(FNstfe_wb  ,TRUE ,FALSE,%000010)","")
 PROCtest("FNcheck_fpa(FNstfp_wb  ,TRUE ,FALSE,%000010)","")
 PROCtest("FNcheck_fpa(FNstfs_post,TRUE ,TRUE ,%000010)","")
 PROCtest("FNcheck_fpa(FNstfd_post,TRUE ,TRUE ,%000010)","")
 PROCtest("FNcheck_fpa(FNstfe_post,TRUE ,TRUE ,%000010)","")
 PROCtest("FNcheck_fpa(FNstfp_post,TRUE ,TRUE ,%000010)","")
 PROCtest("FNcheck_fpa(FNlfm_pre  ,FALSE,FALSE,%000100)","")
 PROCtest("FNcheck_fpa(FNlfm_wb   ,TRUE ,FALSE,%000100)","")
 PROCtest("FNcheck_fpa(FNlfm_post ,TRUE ,TRUE ,%000100)","")
 PROCtest("FNcheck_fpa(FNsfm_pre  ,FALSE,FALSE,%000010)","")
 PROCtest("FNcheck_fpa(FNsfm_wb   ,TRUE ,FALSE,%000010)","")
 PROCtest("FNcheck_fpa(FNsfm_post ,TRUE ,TRUE ,%000010)","")
ENDPROC

DEF PROCtest(test$,feature$)
 CASE feature$ OF
 WHEN "": REM Nothing
 WHEN "VFP": IF have_vfp%=FALSE THEN ENDPROC
 WHEN "NEON": IF have_neon%=FALSE THEN ENDPROC
 WHEN "FPE438" : SYS "FPEmulator_Version" TO V% : IF V%<438 THEN ENDPROC
 OTHERWISE: IF FNfeature(feature$)=0 THEN ENDPROC
 ENDCASE
 IF counting% THEN test_count%+=1 : ENDPROC
 test_idx%+=1
 PRINT phase$;" ";test_idx%;"/";test_count%;": ";test$
 sctlr%=USR read_sctlr%
 FOR try=0 TO 255
  PROCat(testcode_normal%)
  ret%=EVAL(test$)
 NEXT try
ENDPROC

REM Load/store immediate

DEF FNldr_imm        : PROCregs1 : [ OPT 2 : LDR   (Rt%),[(Rn%) ,#FNimm(-4095,4095)]  : B aftertest% : ] : =4
DEF FNstr_imm        : PROCregs1 : [ OPT 2 : STR   (Rt%),[(Rn%) ,#FNimm(-4095,4095)]  : B aftertest% : ] : =4
DEF FNldr_imm_wb     : PROCregs2 : [ OPT 2 : LDR   (Rt%),[(Rn%) ,#FNimm(-4095,4095)]! : B aftertest% : ] : =4
DEF FNstr_imm_wb     : PROCregs2 : [ OPT 2 : STR   (Rt%),[(Rn%) ,#FNimm(-4095,4095)]! : B aftertest% : ] : =4
DEF FNldr_imm_post   : PROCregs2 : [ OPT 2 : LDR   (Rt%),[(Rn%)],#FNimm(-4095,4095)   : B aftertest% : ] : =4
DEF FNstr_imm_post   : PROCregs2 : [ OPT 2 : STR   (Rt%),[(Rn%)],#FNimm(-4095,4095)   : B aftertest% : ] : =4

DEF FNldrb_imm       : PROCregs3 : [ OPT 2 : LDRB  (Rt%),[(Rn%) ,#FNimm(-4095,4095)]  : B aftertest% : ] : =1
DEF FNstrb_imm       : PROCregs3 : [ OPT 2 : STRB  (Rt%),[(Rn%) ,#FNimm(-4095,4095)]  : B aftertest% : ] : =1
DEF FNldrb_imm_wb    : PROCregs4 : [ OPT 2 : LDRB  (Rt%),[(Rn%) ,#FNimm(-4095,4095)]! : B aftertest% : ] : =1
DEF FNstrb_imm_wb    : PROCregs4 : [ OPT 2 : STRB  (Rt%),[(Rn%) ,#FNimm(-4095,4095)]! : B aftertest% : ] : =1
DEF FNldrb_imm_post  : PROCregs4 : [ OPT 2 : LDRB  (Rt%),[(Rn%)],#FNimm(-4095,4095)   : B aftertest% : ] : =1
DEF FNstrb_imm_post  : PROCregs4 : [ OPT 2 : STRB  (Rt%),[(Rn%)],#FNimm(-4095,4095)   : B aftertest% : ] : =1

DEF FNldrh_imm       : PROCregs3 : [ OPT 2 : LDRH  (Rt%),[(Rn%) ,#FNimm(-255,255)]    : B aftertest% : ] : =2
DEF FNstrh_imm       : PROCregs3 : [ OPT 2 : STRH  (Rt%),[(Rn%) ,#FNimm(-255,255)]    : B aftertest% : ] : =2
DEF FNldrh_imm_wb    : PROCregs4 : [ OPT 2 : LDRH  (Rt%),[(Rn%) ,#FNimm(-255,255)]!   : B aftertest% : ] : =2
DEF FNstrh_imm_wb    : PROCregs4 : [ OPT 2 : STRH  (Rt%),[(Rn%) ,#FNimm(-255,255)]!   : B aftertest% : ] : =2
DEF FNldrh_imm_post  : PROCregs4 : [ OPT 2 : LDRH  (Rt%),[(Rn%)],#FNimm(-255,255)     : B aftertest% : ] : =2
DEF FNstrh_imm_post  : PROCregs4 : [ OPT 2 : STRH  (Rt%),[(Rn%)],#FNimm(-255,255)     : B aftertest% : ] : =2

DEF FNldrsb_imm      : PROCregs3 : [ OPT 2 : LDRSB (Rt%),[(Rn%) ,#FNimm(-255,255)]    : B aftertest% : ] : =-1
DEF FNldrsh_imm      : PROCregs3 : [ OPT 2 : LDRSH (Rt%),[(Rn%) ,#FNimm(-255,255)]    : B aftertest% : ] : =-2
DEF FNldrsb_imm_wb   : PROCregs4 : [ OPT 2 : LDRSB (Rt%),[(Rn%) ,#FNimm(-255,255)]!   : B aftertest% : ] : =-1
DEF FNldrsh_imm_wb   : PROCregs4 : [ OPT 2 : LDRSH (Rt%),[(Rn%) ,#FNimm(-255,255)]!   : B aftertest% : ] : =-2
DEF FNldrsb_imm_post : PROCregs4 : [ OPT 2 : LDRSB (Rt%),[(Rn%)],#FNimm(-255,255)     : B aftertest% : ] : =-1
DEF FNldrsh_imm_post : PROCregs4 : [ OPT 2 : LDRSH (Rt%),[(Rn%)],#FNimm(-255,255)     : B aftertest% : ] : =-2

DEF FNldrd_imm       : PROCregs5 : [ OPT 2 : LDRD  (Rt%),[(Rn%) ,#FNimm(-255,255)]    : B aftertest% : ] : =8
DEF FNstrd_imm       : PROCregs5 : [ OPT 2 : STRD  (Rt%),[(Rn%) ,#FNimm(-255,255)]    : B aftertest% : ] : =8
DEF FNldrd_imm_wb    : PROCregs6 : [ OPT 2 : LDRD  (Rt%),[(Rn%) ,#FNimm(-255,255)]!   : B aftertest% : ] : =8
DEF FNstrd_imm_wb    : PROCregs6 : [ OPT 2 : STRD  (Rt%),[(Rn%) ,#FNimm(-255,255)]!   : B aftertest% : ] : =8
DEF FNldrd_imm_post  : PROCregs6 : [ OPT 2 : LDRD  (Rt%),[(Rn%)],#FNimm(-255,255)     : B aftertest% : ] : =8
DEF FNstrd_imm_post  : PROCregs6 : [ OPT 2 : STRD  (Rt%),[(Rn%)],#FNimm(-255,255)     : B aftertest% : ] : =8

REM Load/store literal

DEF FNldr_lit   : PROCregs9(4,4095) : [ OPT 2 : LDR   (Rt%),[PC,#imm%] : B aftertest% : ] : =4
DEF FNstr_lit   : PROCregs9(4,4095) : [ OPT 2 : STR   (Rt%),[PC,#imm%] : B aftertest% : ] : =4
DEF FNldrb_lit  : PROCregs9(1,4095) : [ OPT 2 : LDRB  (Rt%),[PC,#imm%] : B aftertest% : ] : =1
DEF FNstrb_lit  : PROCregs9(1,4095) : [ OPT 2 : STRB  (Rt%),[PC,#imm%] : B aftertest% : ] : =1
DEF FNldrh_lit  : PROCregs9(2, 255) : [ OPT 2 : LDRH  (Rt%),[PC,#imm%] : B aftertest% : ] : =2
DEF FNstrh_lit  : PROCregs9(2, 255) : [ OPT 2 : STRH  (Rt%),[PC,#imm%] : B aftertest% : ] : =2
DEF FNldrsb_lit : PROCregs9(1, 255) : [ OPT 2 : LDRSB (Rt%),[PC,#imm%] : B aftertest% : ] : =-1
DEF FNldrsh_lit : PROCregs9(2, 255) : [ OPT 2 : LDRSH (Rt%),[PC,#imm%] : B aftertest% : ] : =-2
DEF FNldrd_lit  : PROCregs9(8, 255) : [ OPT 2 : LDRD  (Rt%),[PC,#imm%] : B aftertest% : ] : =8
DEF FNstrd_lit  : PROCregs9(8, 255) : [ OPT 2 : STRD  (Rt%),[PC,#imm%] : B aftertest% : ] : =8

REM Load/store register

DEF FNldr_reg_p        : PROCregs11("p")    : [ OPT 2 : LDR   (Rt%),[(Rn%),  (Rm%)            ]  : B aftertest% : ] : =4
DEF FNldr_reg_n        : PROCregs11("n")    : [ OPT 2 : LDR   (Rt%),[(Rn%), -(Rm%)            ]  : B aftertest% : ] : =4
DEF FNldr_LSL_p        : PROCregs11("pLSL") : [ OPT 2 : LDR   (Rt%),[(Rn%),  (Rm%),LSL #shift%]  : B aftertest% : ] : =4
DEF FNldr_LSL_n        : PROCregs11("nLSL") : [ OPT 2 : LDR   (Rt%),[(Rn%), -(Rm%),LSL #shift%]  : B aftertest% : ] : =4
DEF FNldr_LSR_p        : PROCregs11("pLSR") : [ OPT 2 : LDR   (Rt%),[(Rn%),  (Rm%),LSR #shift%]  : B aftertest% : ] : =4
DEF FNldr_LSR_n        : PROCregs11("nLSR") : [ OPT 2 : LDR   (Rt%),[(Rn%), -(Rm%),LSR #shift%]  : B aftertest% : ] : =4
DEF FNldr_ASR_p        : PROCregs11("pASR") : [ OPT 2 : LDR   (Rt%),[(Rn%),  (Rm%),ASR #shift%]  : B aftertest% : ] : =4
DEF FNldr_ASR_n        : PROCregs11("nASR") : [ OPT 2 : LDR   (Rt%),[(Rn%), -(Rm%),ASR #shift%]  : B aftertest% : ] : =4
DEF FNldr_ROR_p        : PROCregs11("pROR") : [ OPT 2 : LDR   (Rt%),[(Rn%),  (Rm%),ROR #shift%]  : B aftertest% : ] : =4
DEF FNldr_ROR_n        : PROCregs11("nROR") : [ OPT 2 : LDR   (Rt%),[(Rn%), -(Rm%),ROR #shift%]  : B aftertest% : ] : =4
DEF FNldr_RRX_p        : PROCregs11("pRRX") : [ OPT 2 : LDR   (Rt%),[(Rn%),  (Rm%),RRX        ]  : B aftertest% : ] : =4
DEF FNldr_RRX_n        : PROCregs11("nRRX") : [ OPT 2 : LDR   (Rt%),[(Rn%), -(Rm%),RRX        ]  : B aftertest% : ] : =4
DEF FNstr_reg_p        : PROCregs11("p")    : [ OPT 2 : STR   (Rt%),[(Rn%),  (Rm%)            ]  : B aftertest% : ] : =4
DEF FNstr_reg_n        : PROCregs11("n")    : [ OPT 2 : STR   (Rt%),[(Rn%), -(Rm%)            ]  : B aftertest% : ] : =4
DEF FNstr_LSL_p        : PROCregs11("pLSL") : [ OPT 2 : STR   (Rt%),[(Rn%),  (Rm%),LSL #shift%]  : B aftertest% : ] : =4
DEF FNstr_LSL_n        : PROCregs11("nLSL") : [ OPT 2 : STR   (Rt%),[(Rn%), -(Rm%),LSL #shift%]  : B aftertest% : ] : =4
DEF FNstr_LSR_p        : PROCregs11("pLSR") : [ OPT 2 : STR   (Rt%),[(Rn%),  (Rm%),LSR #shift%]  : B aftertest% : ] : =4
DEF FNstr_LSR_n        : PROCregs11("nLSR") : [ OPT 2 : STR   (Rt%),[(Rn%), -(Rm%),LSR #shift%]  : B aftertest% : ] : =4
DEF FNstr_ASR_p        : PROCregs11("pASR") : [ OPT 2 : STR   (Rt%),[(Rn%),  (Rm%),ASR #shift%]  : B aftertest% : ] : =4
DEF FNstr_ASR_n        : PROCregs11("nASR") : [ OPT 2 : STR   (Rt%),[(Rn%), -(Rm%),ASR #shift%]  : B aftertest% : ] : =4
DEF FNstr_ROR_p        : PROCregs11("pROR") : [ OPT 2 : STR   (Rt%),[(Rn%),  (Rm%),ROR #shift%]  : B aftertest% : ] : =4
DEF FNstr_ROR_n        : PROCregs11("nROR") : [ OPT 2 : STR   (Rt%),[(Rn%), -(Rm%),ROR #shift%]  : B aftertest% : ] : =4
DEF FNstr_RRX_p        : PROCregs11("pRRX") : [ OPT 2 : STR   (Rt%),[(Rn%),  (Rm%),RRX        ]  : B aftertest% : ] : =4
DEF FNstr_RRX_n        : PROCregs11("nRRX") : [ OPT 2 : STR   (Rt%),[(Rn%), -(Rm%),RRX        ]  : B aftertest% : ] : =4
DEF FNldr_reg_p_wb     : PROCregs12("p")    : [ OPT 2 : LDR   (Rt%),[(Rn%),  (Rm%)            ]! : B aftertest% : ] : =4
DEF FNldr_reg_n_wb     : PROCregs12("n")    : [ OPT 2 : LDR   (Rt%),[(Rn%), -(Rm%)            ]! : B aftertest% : ] : =4
DEF FNldr_LSL_p_wb     : PROCregs12("pLSL") : [ OPT 2 : LDR   (Rt%),[(Rn%),  (Rm%),LSL #shift%]! : B aftertest% : ] : =4
DEF FNldr_LSL_n_wb     : PROCregs12("nLSL") : [ OPT 2 : LDR   (Rt%),[(Rn%), -(Rm%),LSL #shift%]! : B aftertest% : ] : =4
DEF FNldr_LSR_p_wb     : PROCregs12("pLSR") : [ OPT 2 : LDR   (Rt%),[(Rn%),  (Rm%),LSR #shift%]! : B aftertest% : ] : =4
DEF FNldr_LSR_n_wb     : PROCregs12("nLSR") : [ OPT 2 : LDR   (Rt%),[(Rn%), -(Rm%),LSR #shift%]! : B aftertest% : ] : =4
DEF FNldr_ASR_p_wb     : PROCregs12("pASR") : [ OPT 2 : LDR   (Rt%),[(Rn%),  (Rm%),ASR #shift%]! : B aftertest% : ] : =4
DEF FNldr_ASR_n_wb     : PROCregs12("nASR") : [ OPT 2 : LDR   (Rt%),[(Rn%), -(Rm%),ASR #shift%]! : B aftertest% : ] : =4
DEF FNldr_ROR_p_wb     : PROCregs12("pROR") : [ OPT 2 : LDR   (Rt%),[(Rn%),  (Rm%),ROR #shift%]! : B aftertest% : ] : =4
DEF FNldr_ROR_n_wb     : PROCregs12("nROR") : [ OPT 2 : LDR   (Rt%),[(Rn%), -(Rm%),ROR #shift%]! : B aftertest% : ] : =4
DEF FNldr_RRX_p_wb     : PROCregs12("pRRX") : [ OPT 2 : LDR   (Rt%),[(Rn%),  (Rm%),RRX        ]! : B aftertest% : ] : =4
DEF FNldr_RRX_n_wb     : PROCregs12("nRRX") : [ OPT 2 : LDR   (Rt%),[(Rn%), -(Rm%),RRX        ]! : B aftertest% : ] : =4
DEF FNstr_reg_p_wb     : PROCregs12("p")    : [ OPT 2 : STR   (Rt%),[(Rn%),  (Rm%)            ]! : B aftertest% : ] : =4
DEF FNstr_reg_n_wb     : PROCregs12("n")    : [ OPT 2 : STR   (Rt%),[(Rn%), -(Rm%)            ]! : B aftertest% : ] : =4
DEF FNstr_LSL_p_wb     : PROCregs12("pLSL") : [ OPT 2 : STR   (Rt%),[(Rn%),  (Rm%),LSL #shift%]! : B aftertest% : ] : =4
DEF FNstr_LSL_n_wb     : PROCregs12("nLSL") : [ OPT 2 : STR   (Rt%),[(Rn%), -(Rm%),LSL #shift%]! : B aftertest% : ] : =4
DEF FNstr_LSR_p_wb     : PROCregs12("pLSR") : [ OPT 2 : STR   (Rt%),[(Rn%),  (Rm%),LSR #shift%]! : B aftertest% : ] : =4
DEF FNstr_LSR_n_wb     : PROCregs12("nLSR") : [ OPT 2 : STR   (Rt%),[(Rn%), -(Rm%),LSR #shift%]! : B aftertest% : ] : =4
DEF FNstr_ASR_p_wb     : PROCregs12("pASR") : [ OPT 2 : STR   (Rt%),[(Rn%),  (Rm%),ASR #shift%]! : B aftertest% : ] : =4
DEF FNstr_ASR_n_wb     : PROCregs12("nASR") : [ OPT 2 : STR   (Rt%),[(Rn%), -(Rm%),ASR #shift%]! : B aftertest% : ] : =4
DEF FNstr_ROR_p_wb     : PROCregs12("pROR") : [ OPT 2 : STR   (Rt%),[(Rn%),  (Rm%),ROR #shift%]! : B aftertest% : ] : =4
DEF FNstr_ROR_n_wb     : PROCregs12("nROR") : [ OPT 2 : STR   (Rt%),[(Rn%), -(Rm%),ROR #shift%]! : B aftertest% : ] : =4
DEF FNstr_RRX_p_wb     : PROCregs12("pRRX") : [ OPT 2 : STR   (Rt%),[(Rn%),  (Rm%),RRX        ]! : B aftertest% : ] : =4
DEF FNstr_RRX_n_wb     : PROCregs12("nRRX") : [ OPT 2 : STR   (Rt%),[(Rn%), -(Rm%),RRX        ]! : B aftertest% : ] : =4
DEF FNldr_reg_p_post   : PROCregs12("p")    : [ OPT 2 : LDR   (Rt%),[(Rn%)], (Rm%)               : B aftertest% : ] : =4
DEF FNldr_reg_n_post   : PROCregs12("n")    : [ OPT 2 : LDR   (Rt%),[(Rn%)],-(Rm%)               : B aftertest% : ] : =4
DEF FNldr_LSL_p_post   : PROCregs12("pLSL") : [ OPT 2 : LDR   (Rt%),[(Rn%)], (Rm%),LSL #shift%   : B aftertest% : ] : =4
DEF FNldr_LSL_n_post   : PROCregs12("nLSL") : [ OPT 2 : LDR   (Rt%),[(Rn%)],-(Rm%),LSL #shift%   : B aftertest% : ] : =4
DEF FNldr_LSR_p_post   : PROCregs12("pLSR") : [ OPT 2 : LDR   (Rt%),[(Rn%)], (Rm%),LSR #shift%   : B aftertest% : ] : =4
DEF FNldr_LSR_n_post   : PROCregs12("nLSR") : [ OPT 2 : LDR   (Rt%),[(Rn%)],-(Rm%),LSR #shift%   : B aftertest% : ] : =4
DEF FNldr_ASR_p_post   : PROCregs12("pASR") : [ OPT 2 : LDR   (Rt%),[(Rn%)], (Rm%),ASR #shift%   : B aftertest% : ] : =4
DEF FNldr_ASR_n_post   : PROCregs12("nASR") : [ OPT 2 : LDR   (Rt%),[(Rn%)],-(Rm%),ASR #shift%   : B aftertest% : ] : =4
DEF FNldr_ROR_p_post   : PROCregs12("pROR") : [ OPT 2 : LDR   (Rt%),[(Rn%)], (Rm%),ROR #shift%   : B aftertest% : ] : =4
DEF FNldr_ROR_n_post   : PROCregs12("nROR") : [ OPT 2 : LDR   (Rt%),[(Rn%)],-(Rm%),ROR #shift%   : B aftertest% : ] : =4
DEF FNldr_RRX_p_post   : PROCregs12("pRRX") : [ OPT 2 : LDR   (Rt%),[(Rn%)], (Rm%),RRX           : B aftertest% : ] : =4
DEF FNldr_RRX_n_post   : PROCregs12("nRRX") : [ OPT 2 : LDR   (Rt%),[(Rn%)],-(Rm%),RRX           : B aftertest% : ] : =4
DEF FNstr_reg_p_post   : PROCregs12("p")    : [ OPT 2 : STR   (Rt%),[(Rn%)], (Rm%)               : B aftertest% : ] : =4
DEF FNstr_reg_n_post   : PROCregs12("n")    : [ OPT 2 : STR   (Rt%),[(Rn%)],-(Rm%)               : B aftertest% : ] : =4
DEF FNstr_LSL_p_post   : PROCregs12("pLSL") : [ OPT 2 : STR   (Rt%),[(Rn%)], (Rm%),LSL #shift%   : B aftertest% : ] : =4
DEF FNstr_LSL_n_post   : PROCregs12("nLSL") : [ OPT 2 : STR   (Rt%),[(Rn%)],-(Rm%),LSL #shift%   : B aftertest% : ] : =4
DEF FNstr_LSR_p_post   : PROCregs12("pLSR") : [ OPT 2 : STR   (Rt%),[(Rn%)], (Rm%),LSR #shift%   : B aftertest% : ] : =4
DEF FNstr_LSR_n_post   : PROCregs12("nLSR") : [ OPT 2 : STR   (Rt%),[(Rn%)],-(Rm%),LSR #shift%   : B aftertest% : ] : =4
DEF FNstr_ASR_p_post   : PROCregs12("pASR") : [ OPT 2 : STR   (Rt%),[(Rn%)], (Rm%),ASR #shift%   : B aftertest% : ] : =4
DEF FNstr_ASR_n_post   : PROCregs12("nASR") : [ OPT 2 : STR   (Rt%),[(Rn%)],-(Rm%),ASR #shift%   : B aftertest% : ] : =4
DEF FNstr_ROR_p_post   : PROCregs12("pROR") : [ OPT 2 : STR   (Rt%),[(Rn%)], (Rm%),ROR #shift%   : B aftertest% : ] : =4
DEF FNstr_ROR_n_post   : PROCregs12("nROR") : [ OPT 2 : STR   (Rt%),[(Rn%)],-(Rm%),ROR #shift%   : B aftertest% : ] : =4
DEF FNstr_RRX_p_post   : PROCregs12("pRRX") : [ OPT 2 : STR   (Rt%),[(Rn%)], (Rm%),RRX           : B aftertest% : ] : =4
DEF FNstr_RRX_n_post   : PROCregs12("nRRX") : [ OPT 2 : STR   (Rt%),[(Rn%)],-(Rm%),RRX           : B aftertest% : ] : =4

DEF FNldrb_reg_p       : PROCregs13("p")    : [ OPT 2 : LDRB  (Rt%),[(Rn%),  (Rm%)            ]  : B aftertest% : ] : =1
DEF FNldrb_reg_n       : PROCregs13("n")    : [ OPT 2 : LDRB  (Rt%),[(Rn%), -(Rm%)            ]  : B aftertest% : ] : =1
DEF FNldrb_LSL_p       : PROCregs13("pLSL") : [ OPT 2 : LDRB  (Rt%),[(Rn%),  (Rm%),LSL #shift%]  : B aftertest% : ] : =1
DEF FNldrb_LSL_n       : PROCregs13("nLSL") : [ OPT 2 : LDRB  (Rt%),[(Rn%), -(Rm%),LSL #shift%]  : B aftertest% : ] : =1
DEF FNldrb_LSR_p       : PROCregs13("pLSR") : [ OPT 2 : LDRB  (Rt%),[(Rn%),  (Rm%),LSR #shift%]  : B aftertest% : ] : =1
DEF FNldrb_LSR_n       : PROCregs13("nLSR") : [ OPT 2 : LDRB  (Rt%),[(Rn%), -(Rm%),LSR #shift%]  : B aftertest% : ] : =1
DEF FNldrb_ASR_p       : PROCregs13("pASR") : [ OPT 2 : LDRB  (Rt%),[(Rn%),  (Rm%),ASR #shift%]  : B aftertest% : ] : =1
DEF FNldrb_ASR_n       : PROCregs13("nASR") : [ OPT 2 : LDRB  (Rt%),[(Rn%), -(Rm%),ASR #shift%]  : B aftertest% : ] : =1
DEF FNldrb_ROR_p       : PROCregs13("pROR") : [ OPT 2 : LDRB  (Rt%),[(Rn%),  (Rm%),ROR #shift%]  : B aftertest% : ] : =1
DEF FNldrb_ROR_n       : PROCregs13("nROR") : [ OPT 2 : LDRB  (Rt%),[(Rn%), -(Rm%),ROR #shift%]  : B aftertest% : ] : =1
DEF FNldrb_RRX_p       : PROCregs13("pRRX") : [ OPT 2 : LDRB  (Rt%),[(Rn%),  (Rm%),RRX        ]  : B aftertest% : ] : =1
DEF FNldrb_RRX_n       : PROCregs13("nRRX") : [ OPT 2 : LDRB  (Rt%),[(Rn%), -(Rm%),RRX        ]  : B aftertest% : ] : =1
DEF FNstrb_reg_p       : PROCregs13("p")    : [ OPT 2 : STRB  (Rt%),[(Rn%),  (Rm%)            ]  : B aftertest% : ] : =1
DEF FNstrb_reg_n       : PROCregs13("n")    : [ OPT 2 : STRB  (Rt%),[(Rn%), -(Rm%)            ]  : B aftertest% : ] : =1
DEF FNstrb_LSL_p       : PROCregs13("pLSL") : [ OPT 2 : STRB  (Rt%),[(Rn%),  (Rm%),LSL #shift%]  : B aftertest% : ] : =1
DEF FNstrb_LSL_n       : PROCregs13("nLSL") : [ OPT 2 : STRB  (Rt%),[(Rn%), -(Rm%),LSL #shift%]  : B aftertest% : ] : =1
DEF FNstrb_LSR_p       : PROCregs13("pLSR") : [ OPT 2 : STRB  (Rt%),[(Rn%),  (Rm%),LSR #shift%]  : B aftertest% : ] : =1
DEF FNstrb_LSR_n       : PROCregs13("nLSR") : [ OPT 2 : STRB  (Rt%),[(Rn%), -(Rm%),LSR #shift%]  : B aftertest% : ] : =1
DEF FNstrb_ASR_p       : PROCregs13("pASR") : [ OPT 2 : STRB  (Rt%),[(Rn%),  (Rm%),ASR #shift%]  : B aftertest% : ] : =1
DEF FNstrb_ASR_n       : PROCregs13("nASR") : [ OPT 2 : STRB  (Rt%),[(Rn%), -(Rm%),ASR #shift%]  : B aftertest% : ] : =1
DEF FNstrb_ROR_p       : PROCregs13("pROR") : [ OPT 2 : STRB  (Rt%),[(Rn%),  (Rm%),ROR #shift%]  : B aftertest% : ] : =1
DEF FNstrb_ROR_n       : PROCregs13("nROR") : [ OPT 2 : STRB  (Rt%),[(Rn%), -(Rm%),ROR #shift%]  : B aftertest% : ] : =1
DEF FNstrb_RRX_p       : PROCregs13("pRRX") : [ OPT 2 : STRB  (Rt%),[(Rn%),  (Rm%),RRX        ]  : B aftertest% : ] : =1
DEF FNstrb_RRX_n       : PROCregs13("nRRX") : [ OPT 2 : STRB  (Rt%),[(Rn%), -(Rm%),RRX        ]  : B aftertest% : ] : =1
DEF FNldrb_reg_p_wb    : PROCregs14("p")    : [ OPT 2 : LDRB  (Rt%),[(Rn%),  (Rm%)            ]! : B aftertest% : ] : =1
DEF FNldrb_reg_n_wb    : PROCregs14("n")    : [ OPT 2 : LDRB  (Rt%),[(Rn%), -(Rm%)            ]! : B aftertest% : ] : =1
DEF FNldrb_LSL_p_wb    : PROCregs14("pLSL") : [ OPT 2 : LDRB  (Rt%),[(Rn%),  (Rm%),LSL #shift%]! : B aftertest% : ] : =1
DEF FNldrb_LSL_n_wb    : PROCregs14("nLSL") : [ OPT 2 : LDRB  (Rt%),[(Rn%), -(Rm%),LSL #shift%]! : B aftertest% : ] : =1
DEF FNldrb_LSR_p_wb    : PROCregs14("pLSR") : [ OPT 2 : LDRB  (Rt%),[(Rn%),  (Rm%),LSR #shift%]! : B aftertest% : ] : =1
DEF FNldrb_LSR_n_wb    : PROCregs14("nLSR") : [ OPT 2 : LDRB  (Rt%),[(Rn%), -(Rm%),LSR #shift%]! : B aftertest% : ] : =1
DEF FNldrb_ASR_p_wb    : PROCregs14("pASR") : [ OPT 2 : LDRB  (Rt%),[(Rn%),  (Rm%),ASR #shift%]! : B aftertest% : ] : =1
DEF FNldrb_ASR_n_wb    : PROCregs14("nASR") : [ OPT 2 : LDRB  (Rt%),[(Rn%), -(Rm%),ASR #shift%]! : B aftertest% : ] : =1
DEF FNldrb_ROR_p_wb    : PROCregs14("pROR") : [ OPT 2 : LDRB  (Rt%),[(Rn%),  (Rm%),ROR #shift%]! : B aftertest% : ] : =1
DEF FNldrb_ROR_n_wb    : PROCregs14("nROR") : [ OPT 2 : LDRB  (Rt%),[(Rn%), -(Rm%),ROR #shift%]! : B aftertest% : ] : =1
DEF FNldrb_RRX_p_wb    : PROCregs14("pRRX") : [ OPT 2 : LDRB  (Rt%),[(Rn%),  (Rm%),RRX        ]! : B aftertest% : ] : =1
DEF FNldrb_RRX_n_wb    : PROCregs14("nRRX") : [ OPT 2 : LDRB  (Rt%),[(Rn%), -(Rm%),RRX        ]! : B aftertest% : ] : =1
DEF FNstrb_reg_p_wb    : PROCregs14("p")    : [ OPT 2 : STRB  (Rt%),[(Rn%),  (Rm%)            ]! : B aftertest% : ] : =1
DEF FNstrb_reg_n_wb    : PROCregs14("n")    : [ OPT 2 : STRB  (Rt%),[(Rn%), -(Rm%)            ]! : B aftertest% : ] : =1
DEF FNstrb_LSL_p_wb    : PROCregs14("pLSL") : [ OPT 2 : STRB  (Rt%),[(Rn%),  (Rm%),LSL #shift%]! : B aftertest% : ] : =1
DEF FNstrb_LSL_n_wb    : PROCregs14("nLSL") : [ OPT 2 : STRB  (Rt%),[(Rn%), -(Rm%),LSL #shift%]! : B aftertest% : ] : =1
DEF FNstrb_LSR_p_wb    : PROCregs14("pLSR") : [ OPT 2 : STRB  (Rt%),[(Rn%),  (Rm%),LSR #shift%]! : B aftertest% : ] : =1
DEF FNstrb_LSR_n_wb    : PROCregs14("nLSR") : [ OPT 2 : STRB  (Rt%),[(Rn%), -(Rm%),LSR #shift%]! : B aftertest% : ] : =1
DEF FNstrb_ASR_p_wb    : PROCregs14("pASR") : [ OPT 2 : STRB  (Rt%),[(Rn%),  (Rm%),ASR #shift%]! : B aftertest% : ] : =1
DEF FNstrb_ASR_n_wb    : PROCregs14("nASR") : [ OPT 2 : STRB  (Rt%),[(Rn%), -(Rm%),ASR #shift%]! : B aftertest% : ] : =1
DEF FNstrb_ROR_p_wb    : PROCregs14("pROR") : [ OPT 2 : STRB  (Rt%),[(Rn%),  (Rm%),ROR #shift%]! : B aftertest% : ] : =1
DEF FNstrb_ROR_n_wb    : PROCregs14("nROR") : [ OPT 2 : STRB  (Rt%),[(Rn%), -(Rm%),ROR #shift%]! : B aftertest% : ] : =1
DEF FNstrb_RRX_p_wb    : PROCregs14("pRRX") : [ OPT 2 : STRB  (Rt%),[(Rn%),  (Rm%),RRX        ]! : B aftertest% : ] : =1
DEF FNstrb_RRX_n_wb    : PROCregs14("nRRX") : [ OPT 2 : STRB  (Rt%),[(Rn%), -(Rm%),RRX        ]! : B aftertest% : ] : =1
DEF FNldrb_reg_p_post  : PROCregs14("p")    : [ OPT 2 : LDRB  (Rt%),[(Rn%)], (Rm%)               : B aftertest% : ] : =1
DEF FNldrb_reg_n_post  : PROCregs14("n")    : [ OPT 2 : LDRB  (Rt%),[(Rn%)],-(Rm%)               : B aftertest% : ] : =1
DEF FNldrb_LSL_p_post  : PROCregs14("pLSL") : [ OPT 2 : LDRB  (Rt%),[(Rn%)], (Rm%),LSL #shift%   : B aftertest% : ] : =1
DEF FNldrb_LSL_n_post  : PROCregs14("nLSL") : [ OPT 2 : LDRB  (Rt%),[(Rn%)],-(Rm%),LSL #shift%   : B aftertest% : ] : =1
DEF FNldrb_LSR_p_post  : PROCregs14("pLSR") : [ OPT 2 : LDRB  (Rt%),[(Rn%)], (Rm%),LSR #shift%   : B aftertest% : ] : =1
DEF FNldrb_LSR_n_post  : PROCregs14("nLSR") : [ OPT 2 : LDRB  (Rt%),[(Rn%)],-(Rm%),LSR #shift%   : B aftertest% : ] : =1
DEF FNldrb_ASR_p_post  : PROCregs14("pASR") : [ OPT 2 : LDRB  (Rt%),[(Rn%)], (Rm%),ASR #shift%   : B aftertest% : ] : =1
DEF FNldrb_ASR_n_post  : PROCregs14("nASR") : [ OPT 2 : LDRB  (Rt%),[(Rn%)],-(Rm%),ASR #shift%   : B aftertest% : ] : =1
DEF FNldrb_ROR_p_post  : PROCregs14("pROR") : [ OPT 2 : LDRB  (Rt%),[(Rn%)], (Rm%),ROR #shift%   : B aftertest% : ] : =1
DEF FNldrb_ROR_n_post  : PROCregs14("nROR") : [ OPT 2 : LDRB  (Rt%),[(Rn%)],-(Rm%),ROR #shift%   : B aftertest% : ] : =1
DEF FNldrb_RRX_p_post  : PROCregs14("pRRX") : [ OPT 2 : LDRB  (Rt%),[(Rn%)], (Rm%),RRX           : B aftertest% : ] : =1
DEF FNldrb_RRX_n_post  : PROCregs14("nRRX") : [ OPT 2 : LDRB  (Rt%),[(Rn%)],-(Rm%),RRX           : B aftertest% : ] : =1
DEF FNstrb_reg_p_post  : PROCregs14("p")    : [ OPT 2 : STRB  (Rt%),[(Rn%)], (Rm%)               : B aftertest% : ] : =1
DEF FNstrb_reg_n_post  : PROCregs14("n")    : [ OPT 2 : STRB  (Rt%),[(Rn%)],-(Rm%)               : B aftertest% : ] : =1
DEF FNstrb_LSL_p_post  : PROCregs14("pLSL") : [ OPT 2 : STRB  (Rt%),[(Rn%)], (Rm%),LSL #shift%   : B aftertest% : ] : =1
DEF FNstrb_LSL_n_post  : PROCregs14("nLSL") : [ OPT 2 : STRB  (Rt%),[(Rn%)],-(Rm%),LSL #shift%   : B aftertest% : ] : =1
DEF FNstrb_LSR_p_post  : PROCregs14("pLSR") : [ OPT 2 : STRB  (Rt%),[(Rn%)], (Rm%),LSR #shift%   : B aftertest% : ] : =1
DEF FNstrb_LSR_n_post  : PROCregs14("nLSR") : [ OPT 2 : STRB  (Rt%),[(Rn%)],-(Rm%),LSR #shift%   : B aftertest% : ] : =1
DEF FNstrb_ASR_p_post  : PROCregs14("pASR") : [ OPT 2 : STRB  (Rt%),[(Rn%)], (Rm%),ASR #shift%   : B aftertest% : ] : =1
DEF FNstrb_ASR_n_post  : PROCregs14("nASR") : [ OPT 2 : STRB  (Rt%),[(Rn%)],-(Rm%),ASR #shift%   : B aftertest% : ] : =1
DEF FNstrb_ROR_p_post  : PROCregs14("pROR") : [ OPT 2 : STRB  (Rt%),[(Rn%)], (Rm%),ROR #shift%   : B aftertest% : ] : =1
DEF FNstrb_ROR_n_post  : PROCregs14("nROR") : [ OPT 2 : STRB  (Rt%),[(Rn%)],-(Rm%),ROR #shift%   : B aftertest% : ] : =1
DEF FNstrb_RRX_p_post  : PROCregs14("pRRX") : [ OPT 2 : STRB  (Rt%),[(Rn%)], (Rm%),RRX           : B aftertest% : ] : =1
DEF FNstrb_RRX_n_post  : PROCregs14("nRRX") : [ OPT 2 : STRB  (Rt%),[(Rn%)],-(Rm%),RRX           : B aftertest% : ] : =1

DEF FNldrh_reg_p       : PROCregs13("p")    : [ OPT 2 : LDRH  (Rt%),[(Rn%),  (Rm%)]  : B aftertest% : ] : =2
DEF FNldrh_reg_n       : PROCregs13("n")    : [ OPT 2 : LDRH  (Rt%),[(Rn%), -(Rm%)]  : B aftertest% : ] : =2
DEF FNldrh_reg_p_wb    : PROCregs14("p")    : [ OPT 2 : LDRH  (Rt%),[(Rn%),  (Rm%)]! : B aftertest% : ] : =2
DEF FNldrh_reg_n_wb    : PROCregs14("n")    : [ OPT 2 : LDRH  (Rt%),[(Rn%), -(Rm%)]! : B aftertest% : ] : =2
DEF FNldrh_reg_p_post  : PROCregs14("p")    : [ OPT 2 : LDRH  (Rt%),[(Rn%)], (Rm%)   : B aftertest% : ] : =2
DEF FNldrh_reg_n_post  : PROCregs14("n")    : [ OPT 2 : LDRH  (Rt%),[(Rn%)],-(Rm%)   : B aftertest% : ] : =2
DEF FNstrh_reg_p       : PROCregs13("p")    : [ OPT 2 : STRH  (Rt%),[(Rn%),  (Rm%)]  : B aftertest% : ] : =2
DEF FNstrh_reg_n       : PROCregs13("n")    : [ OPT 2 : STRH  (Rt%),[(Rn%), -(Rm%)]  : B aftertest% : ] : =2
DEF FNstrh_reg_p_wb    : PROCregs14("p")    : [ OPT 2 : STRH  (Rt%),[(Rn%),  (Rm%)]! : B aftertest% : ] : =2
DEF FNstrh_reg_n_wb    : PROCregs14("n")    : [ OPT 2 : STRH  (Rt%),[(Rn%), -(Rm%)]! : B aftertest% : ] : =2
DEF FNstrh_reg_p_post  : PROCregs14("p")    : [ OPT 2 : STRH  (Rt%),[(Rn%)], (Rm%)   : B aftertest% : ] : =2
DEF FNstrh_reg_n_post  : PROCregs14("n")    : [ OPT 2 : STRH  (Rt%),[(Rn%)],-(Rm%)   : B aftertest% : ] : =2

DEF FNldrsb_reg_p      : PROCregs13("p")    : [ OPT 2 : LDRSB (Rt%),[(Rn%),  (Rm%)]  : B aftertest% : ] : =-1
DEF FNldrsb_reg_n      : PROCregs13("n")    : [ OPT 2 : LDRSB (Rt%),[(Rn%), -(Rm%)]  : B aftertest% : ] : =-1
DEF FNldrsb_reg_p_wb   : PROCregs14("p")    : [ OPT 2 : LDRSB (Rt%),[(Rn%),  (Rm%)]! : B aftertest% : ] : =-1
DEF FNldrsb_reg_n_wb   : PROCregs14("n")    : [ OPT 2 : LDRSB (Rt%),[(Rn%), -(Rm%)]! : B aftertest% : ] : =-1
DEF FNldrsb_reg_p_post : PROCregs14("p")    : [ OPT 2 : LDRSB (Rt%),[(Rn%)], (Rm%)   : B aftertest% : ] : =-1
DEF FNldrsb_reg_n_post : PROCregs14("n")    : [ OPT 2 : LDRSB (Rt%),[(Rn%)],-(Rm%)   : B aftertest% : ] : =-1

DEF FNldrsh_reg_p      : PROCregs13("p")    : [ OPT 2 : LDRSH (Rt%),[(Rn%),  (Rm%)]  : B aftertest% : ] : =-2
DEF FNldrsh_reg_n      : PROCregs13("n")    : [ OPT 2 : LDRSH (Rt%),[(Rn%), -(Rm%)]  : B aftertest% : ] : =-2
DEF FNldrsh_reg_p_wb   : PROCregs14("p")    : [ OPT 2 : LDRSH (Rt%),[(Rn%),  (Rm%)]! : B aftertest% : ] : =-2
DEF FNldrsh_reg_n_wb   : PROCregs14("n")    : [ OPT 2 : LDRSH (Rt%),[(Rn%), -(Rm%)]! : B aftertest% : ] : =-2
DEF FNldrsh_reg_p_post : PROCregs14("p")    : [ OPT 2 : LDRSH (Rt%),[(Rn%)], (Rm%)   : B aftertest% : ] : =-2
DEF FNldrsh_reg_n_post : PROCregs14("n")    : [ OPT 2 : LDRSH (Rt%),[(Rn%)],-(Rm%)   : B aftertest% : ] : =-2

DEF FNldrd_reg_p       : PROCregs15("p")    : [ OPT 2 : LDRD  (Rt%),[(Rn%),  (Rm%)]  : B aftertest% : ] : =8
DEF FNldrd_reg_n       : PROCregs15("n")    : [ OPT 2 : LDRD  (Rt%),[(Rn%), -(Rm%)]  : B aftertest% : ] : =8
DEF FNldrd_reg_p_wb    : PROCregs16("p")    : [ OPT 2 : LDRD  (Rt%),[(Rn%),  (Rm%)]! : B aftertest% : ] : =8
DEF FNldrd_reg_n_wb    : PROCregs16("n")    : [ OPT 2 : LDRD  (Rt%),[(Rn%), -(Rm%)]! : B aftertest% : ] : =8
DEF FNldrd_reg_p_post  : PROCregs16("p")    : [ OPT 2 : LDRD  (Rt%),[(Rn%)], (Rm%)   : B aftertest% : ] : =8
DEF FNldrd_reg_n_post  : PROCregs16("n")    : [ OPT 2 : LDRD  (Rt%),[(Rn%)],-(Rm%)   : B aftertest% : ] : =8
DEF FNstrd_reg_p       : PROCregs17("p")    : [ OPT 2 : STRD  (Rt%),[(Rn%),  (Rm%)]  : B aftertest% : ] : =8
DEF FNstrd_reg_n       : PROCregs17("n")    : [ OPT 2 : STRD  (Rt%),[(Rn%), -(Rm%)]  : B aftertest% : ] : =8
DEF FNstrd_reg_p_wb    : PROCregs18("p")    : [ OPT 2 : STRD  (Rt%),[(Rn%),  (Rm%)]! : B aftertest% : ] : =8
DEF FNstrd_reg_n_wb    : PROCregs18("n")    : [ OPT 2 : STRD  (Rt%),[(Rn%), -(Rm%)]! : B aftertest% : ] : =8
DEF FNstrd_reg_p_post  : PROCregs18("p")    : [ OPT 2 : STRD  (Rt%),[(Rn%)], (Rm%)   : B aftertest% : ] : =8
DEF FNstrd_reg_n_post  : PROCregs18("n")    : [ OPT 2 : STRD  (Rt%),[(Rn%)],-(Rm%)   : B aftertest% : ] : =8

REM Normal LDM/STM

DEF FNldmia    : PROCregs7 : X%=P% : [ OPT 2 : LDMIA (Rn%) ,{R0-R15} : B aftertest% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =0
DEF FNstmia    : PROCregs7 : X%=P% : [ OPT 2 : STMIA (Rn%) ,{R0-R15} : B aftertest% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =0
DEF FNldmib    : PROCregs7 : X%=P% : [ OPT 2 : LDMIB (Rn%) ,{R0-R15} : B aftertest% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =0
DEF FNstmib    : PROCregs7 : X%=P% : [ OPT 2 : STMIB (Rn%) ,{R0-R15} : B aftertest% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =0
DEF FNldmda    : PROCregs7 : X%=P% : [ OPT 2 : LDMDA (Rn%) ,{R0-R15} : B aftertest% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =0
DEF FNstmda    : PROCregs7 : X%=P% : [ OPT 2 : STMDA (Rn%) ,{R0-R15} : B aftertest% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =0
DEF FNldmdb    : PROCregs7 : X%=P% : [ OPT 2 : LDMDB (Rn%) ,{R0-R15} : B aftertest% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =0
DEF FNstmdb    : PROCregs7 : X%=P% : [ OPT 2 : STMDB (Rn%) ,{R0-R15} : B aftertest% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =0
DEF FNldmia_wb : PROCregs8 : X%=P% : [ OPT 2 : LDMIA (Rn%)!,{R0-R15} : B aftertest% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =0
DEF FNstmia_wb : PROCregs8 : X%=P% : [ OPT 2 : STMIA (Rn%)!,{R0-R15} : B aftertest% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =0
DEF FNldmib_wb : PROCregs8 : X%=P% : [ OPT 2 : LDMIB (Rn%)!,{R0-R15} : B aftertest% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =0
DEF FNstmib_wb : PROCregs8 : X%=P% : [ OPT 2 : STMIB (Rn%)!,{R0-R15} : B aftertest% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =0
DEF FNldmda_wb : PROCregs8 : X%=P% : [ OPT 2 : LDMDA (Rn%)!,{R0-R15} : B aftertest% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =0
DEF FNstmda_wb : PROCregs8 : X%=P% : [ OPT 2 : STMDA (Rn%)!,{R0-R15} : B aftertest% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =0
DEF FNldmdb_wb : PROCregs8 : X%=P% : [ OPT 2 : LDMDB (Rn%)!,{R0-R15} : B aftertest% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =0
DEF FNstmdb_wb : PROCregs8 : X%=P% : [ OPT 2 : STMDB (Rn%)!,{R0-R15} : B aftertest% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =0

REM Usermode LDM/STM

DEF FNldmia_usr : PROCregs10(14) : X%=P%+12 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #testpsr% : LDR (Rn%),in_regs%+(Rn%*4) : LDMIA (Rn%),{R0-R15}^ : B aftertest_priv% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =16
DEF FNstmia_usr : PROCregs10(15) : X%=P%+12 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #testpsr% : LDR (Rn%),in_regs%+(Rn%*4) : STMIA (Rn%),{R0-R15}^ : B aftertest_priv% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =16
DEF FNldmib_usr : PROCregs10(14) : X%=P%+12 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #testpsr% : LDR (Rn%),in_regs%+(Rn%*4) : LDMIB (Rn%),{R0-R15}^ : B aftertest_priv% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =16
DEF FNstmib_usr : PROCregs10(15) : X%=P%+12 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #testpsr% : LDR (Rn%),in_regs%+(Rn%*4) : STMIB (Rn%),{R0-R15}^ : B aftertest_priv% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =16
DEF FNldmda_usr : PROCregs10(14) : X%=P%+12 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #testpsr% : LDR (Rn%),in_regs%+(Rn%*4) : LDMDA (Rn%),{R0-R15}^ : B aftertest_priv% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =16
DEF FNstmda_usr : PROCregs10(15) : X%=P%+12 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #testpsr% : LDR (Rn%),in_regs%+(Rn%*4) : STMDA (Rn%),{R0-R15}^ : B aftertest_priv% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =16
DEF FNldmdb_usr : PROCregs10(14) : X%=P%+12 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #testpsr% : LDR (Rn%),in_regs%+(Rn%*4) : LDMDB (Rn%),{R0-R15}^ : B aftertest_priv% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =16
DEF FNstmdb_usr : PROCregs10(15) : X%=P%+12 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #testpsr% : LDR (Rn%),in_regs%+(Rn%*4) : STMDB (Rn%),{R0-R15}^ : B aftertest_priv% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =16

REM VLDR/VSTR

DEF FNvldrs_imm : Rn%=FNrnd(0,14) : Vd%=FNrnd(0,max_dregs%-1) : imm%=FNrnd(-255,255)<<2 : [ OPT 2 : VLDR S#Vd%,[(Rn%),#imm%] : B aftertest% : ] : =4
DEF FNvldrd_imm : Rn%=FNrnd(0,14) : Vd%=FNrnd(0,max_dregs%-1) : imm%=FNrnd(-255,255)<<2 : [ OPT 2 : VLDR D#Vd%,[(Rn%),#imm%] : B aftertest% : ] : =8
DEF FNvstrs_imm : Rn%=FNrnd(0,14) : Vd%=FNrnd(0,max_dregs%-1) : imm%=FNrnd(-255,255)<<2 : [ OPT 2 : VSTR S#Vd%,[(Rn%),#imm%] : B aftertest% : ] : =4
DEF FNvstrd_imm : Rn%=FNrnd(0,14) : Vd%=FNrnd(0,max_dregs%-1) : imm%=FNrnd(-255,255)<<2 : [ OPT 2 : VSTR D#Vd%,[(Rn%),#imm%] : B aftertest% : ] : =8

DEF FNvldrs_lit : PROCregs19(4,255) : [ OPT 2 : VLDR S#Vd%,[PC,#imm%] : B aftertest% : ] : =4
DEF FNvldrd_lit : PROCregs19(8,255) : [ OPT 2 : VLDR D#Vd%,[PC,#imm%] : B aftertest% : ] : =8
DEF FNvstrs_lit : PROCregs19(4,255) : [ OPT 2 : VSTR S#Vd%,[PC,#imm%] : B aftertest% : ] : =4
DEF FNvstrd_lit : PROCregs19(8,255) : [ OPT 2 : VSTR D#Vd%,[PC,#imm%] : B aftertest% : ] : =8

REM VLDM/VSTM

DEF FNvldmia_s    : PROCregs20(FALSE) : X%=P% : [ OPT 2 : VLDMIA (Rn%) ,{S0} : B aftertest% : ] : !X%=Vx%+!X%   : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =4
DEF FNvldmia_d    : PROCregs20(TRUE ) : X%=P% : [ OPT 2 : VLDMIA (Rn%) ,{D0} : B aftertest% : ] : !X%=Vx%+!X%   : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =8
DEF FNfldmia_x    : PROCregs20(TRUE ) : X%=P% : [ OPT 2 : VLDMIA (Rn%) ,{D0} : B aftertest% : ] : !X%=Vx%+!X%+1 : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =9
DEF FNvldmia_s_wb : PROCregs20(FALSE) : X%=P% : [ OPT 2 : VLDMIA (Rn%)!,{S0} : B aftertest% : ] : !X%=Vx%+!X%   : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =4
DEF FNvldmia_d_wb : PROCregs20(TRUE ) : X%=P% : [ OPT 2 : VLDMIA (Rn%)!,{D0} : B aftertest% : ] : !X%=Vx%+!X%   : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =8
DEF FNfldmia_x_wb : PROCregs20(TRUE ) : X%=P% : [ OPT 2 : VLDMIA (Rn%)!,{D0} : B aftertest% : ] : !X%=Vx%+!X%+1 : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =9
DEF FNvldmdb_s_wb : PROCregs20(FALSE) : X%=P% : [ OPT 2 : VLDMDB (Rn%)!,{S0} : B aftertest% : ] : !X%=Vx%+!X%   : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =4
DEF FNvldmdb_d_wb : PROCregs20(TRUE ) : X%=P% : [ OPT 2 : VLDMDB (Rn%)!,{D0} : B aftertest% : ] : !X%=Vx%+!X%   : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =8
DEF FNfldmdb_x_wb : PROCregs20(TRUE ) : X%=P% : [ OPT 2 : VLDMDB (Rn%)!,{D0} : B aftertest% : ] : !X%=Vx%+!X%+1 : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =9
DEF FNvstmia_s    : PROCregs20(FALSE) : X%=P% : [ OPT 2 : VSTMIA (Rn%) ,{S0} : B aftertest% : ] : !X%=Vx%+!X%   : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =4
DEF FNvstmia_d    : PROCregs20(TRUE ) : X%=P% : [ OPT 2 : VSTMIA (Rn%) ,{D0} : B aftertest% : ] : !X%=Vx%+!X%   : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =8
DEF FNfstmia_x    : PROCregs20(TRUE ) : X%=P% : [ OPT 2 : VSTMIA (Rn%) ,{D0} : B aftertest% : ] : !X%=Vx%+!X%+1 : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =9
DEF FNvstmia_s_wb : PROCregs20(FALSE) : X%=P% : [ OPT 2 : VSTMIA (Rn%)!,{S0} : B aftertest% : ] : !X%=Vx%+!X%   : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =4
DEF FNvstmia_d_wb : PROCregs20(TRUE ) : X%=P% : [ OPT 2 : VSTMIA (Rn%)!,{D0} : B aftertest% : ] : !X%=Vx%+!X%   : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =8
DEF FNfstmia_x_wb : PROCregs20(TRUE ) : X%=P% : [ OPT 2 : VSTMIA (Rn%)!,{D0} : B aftertest% : ] : !X%=Vx%+!X%+1 : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =9
DEF FNvstmdb_s_wb : PROCregs20(FALSE) : X%=P% : [ OPT 2 : VSTMDB (Rn%)!,{S0} : B aftertest% : ] : !X%=Vx%+!X%   : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =4
DEF FNvstmdb_d_wb : PROCregs20(TRUE ) : X%=P% : [ OPT 2 : VSTMDB (Rn%)!,{D0} : B aftertest% : ] : !X%=Vx%+!X%   : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =8
DEF FNfstmdb_x_wb : PROCregs20(TRUE ) : X%=P% : [ OPT 2 : VSTMDB (Rn%)!,{D0} : B aftertest% : ] : !X%=Vx%+!X%+1 : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =9

REM VLD/VST multiple single elements

DEF FNvld1_mult_08_1_xxx    : PROCregs21(1) : [ OPT 2 : VLD1.8  {D#Vd%                              },[Rn%    ]     : B aftertest% : ] : =8
DEF FNvld1_mult_08_1_xxx_wb : PROCregs21(1) : [ OPT 2 : VLD1.8  {D#Vd%                              },[Rn%    ]!    : B aftertest% : ] : =8
DEF FNvld1_mult_08_1_xxx_rm : PROCregs21(1) : [ OPT 2 : VLD1.8  {D#Vd%                              },[Rn%    ],Rm% : B aftertest% : ] : =8
DEF FNvld1_mult_08_1_064    : PROCregs21(1) : [ OPT 2 : VLD1.8  {D#Vd%                              },[Rn%@64 ]     : B aftertest% : ] : =8
DEF FNvld1_mult_08_1_064_wb : PROCregs21(1) : [ OPT 2 : VLD1.8  {D#Vd%                              },[Rn%@64 ]!    : B aftertest% : ] : =8
DEF FNvld1_mult_08_1_064_rm : PROCregs21(1) : [ OPT 2 : VLD1.8  {D#Vd%                              },[Rn%@64 ],Rm% : B aftertest% : ] : =8
DEF FNvld1_mult_08_2_xxx    : PROCregs21(2) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1)                    },[Rn%    ]     : B aftertest% : ] : =16
DEF FNvld1_mult_08_2_xxx_wb : PROCregs21(2) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1)                    },[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvld1_mult_08_2_xxx_rm : PROCregs21(2) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1)                    },[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvld1_mult_08_2_064    : PROCregs21(2) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]     : B aftertest% : ] : =16
DEF FNvld1_mult_08_2_064_wb : PROCregs21(2) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]!    : B aftertest% : ] : =16
DEF FNvld1_mult_08_2_064_rm : PROCregs21(2) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ],Rm% : B aftertest% : ] : =16
DEF FNvld1_mult_08_2_128    : PROCregs21(2) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1)                    },[Rn%@128]     : B aftertest% : ] : =16
DEF FNvld1_mult_08_2_128_wb : PROCregs21(2) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1)                    },[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvld1_mult_08_2_128_rm : PROCregs21(2) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1)                    },[Rn%@128],Rm% : B aftertest% : ] : =16
DEF FNvld1_mult_08_3_xxx    : PROCregs21(3) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]     : B aftertest% : ] : =24
DEF FNvld1_mult_08_3_xxx_wb : PROCregs21(3) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]!    : B aftertest% : ] : =24
DEF FNvld1_mult_08_3_xxx_rm : PROCregs21(3) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ],Rm% : B aftertest% : ] : =24
DEF FNvld1_mult_08_3_064    : PROCregs21(3) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]     : B aftertest% : ] : =24
DEF FNvld1_mult_08_3_064_wb : PROCregs21(3) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]!    : B aftertest% : ] : =24
DEF FNvld1_mult_08_3_064_rm : PROCregs21(3) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ],Rm% : B aftertest% : ] : =24
DEF FNvld1_mult_08_4_xxx    : PROCregs21(4) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvld1_mult_08_4_xxx_wb : PROCregs21(4) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvld1_mult_08_4_xxx_rm : PROCregs21(4) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvld1_mult_08_4_064    : PROCregs21(4) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvld1_mult_08_4_064_wb : PROCregs21(4) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvld1_mult_08_4_064_rm : PROCregs21(4) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvld1_mult_08_4_128    : PROCregs21(4) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvld1_mult_08_4_128_wb : PROCregs21(4) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvld1_mult_08_4_128_rm : PROCregs21(4) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvld1_mult_08_4_256    : PROCregs21(4) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvld1_mult_08_4_256_wb : PROCregs21(4) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvld1_mult_08_4_256_rm : PROCregs21(4) : [ OPT 2 : VLD1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256],Rm% : B aftertest% : ] : =32
DEF FNvld1_mult_16_1_xxx    : PROCregs21(1) : [ OPT 2 : VLD1.16 {D#Vd%                              },[Rn%    ]     : B aftertest% : ] : =8
DEF FNvld1_mult_16_1_xxx_wb : PROCregs21(1) : [ OPT 2 : VLD1.16 {D#Vd%                              },[Rn%    ]!    : B aftertest% : ] : =8
DEF FNvld1_mult_16_1_xxx_rm : PROCregs21(1) : [ OPT 2 : VLD1.16 {D#Vd%                              },[Rn%    ],Rm% : B aftertest% : ] : =8
DEF FNvld1_mult_16_1_064    : PROCregs21(1) : [ OPT 2 : VLD1.16 {D#Vd%                              },[Rn%@64 ]     : B aftertest% : ] : =8
DEF FNvld1_mult_16_1_064_wb : PROCregs21(1) : [ OPT 2 : VLD1.16 {D#Vd%                              },[Rn%@64 ]!    : B aftertest% : ] : =8
DEF FNvld1_mult_16_1_064_rm : PROCregs21(1) : [ OPT 2 : VLD1.16 {D#Vd%                              },[Rn%@64 ],Rm% : B aftertest% : ] : =8
DEF FNvld1_mult_16_2_xxx    : PROCregs21(2) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1)                    },[Rn%    ]     : B aftertest% : ] : =16
DEF FNvld1_mult_16_2_xxx_wb : PROCregs21(2) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1)                    },[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvld1_mult_16_2_xxx_rm : PROCregs21(2) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1)                    },[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvld1_mult_16_2_064    : PROCregs21(2) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]     : B aftertest% : ] : =16
DEF FNvld1_mult_16_2_064_wb : PROCregs21(2) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]!    : B aftertest% : ] : =16
DEF FNvld1_mult_16_2_064_rm : PROCregs21(2) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ],Rm% : B aftertest% : ] : =16
DEF FNvld1_mult_16_2_128    : PROCregs21(2) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1)                    },[Rn%@128]     : B aftertest% : ] : =16
DEF FNvld1_mult_16_2_128_wb : PROCregs21(2) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1)                    },[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvld1_mult_16_2_128_rm : PROCregs21(2) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1)                    },[Rn%@128],Rm% : B aftertest% : ] : =16
DEF FNvld1_mult_16_3_xxx    : PROCregs21(3) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]     : B aftertest% : ] : =24
DEF FNvld1_mult_16_3_xxx_wb : PROCregs21(3) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]!    : B aftertest% : ] : =24
DEF FNvld1_mult_16_3_xxx_rm : PROCregs21(3) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ],Rm% : B aftertest% : ] : =24
DEF FNvld1_mult_16_3_064    : PROCregs21(3) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]     : B aftertest% : ] : =24
DEF FNvld1_mult_16_3_064_wb : PROCregs21(3) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]!    : B aftertest% : ] : =24
DEF FNvld1_mult_16_3_064_rm : PROCregs21(3) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ],Rm% : B aftertest% : ] : =24
DEF FNvld1_mult_16_4_xxx    : PROCregs21(4) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvld1_mult_16_4_xxx_wb : PROCregs21(4) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvld1_mult_16_4_xxx_rm : PROCregs21(4) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvld1_mult_16_4_064    : PROCregs21(4) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvld1_mult_16_4_064_wb : PROCregs21(4) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvld1_mult_16_4_064_rm : PROCregs21(4) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvld1_mult_16_4_128    : PROCregs21(4) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvld1_mult_16_4_128_wb : PROCregs21(4) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvld1_mult_16_4_128_rm : PROCregs21(4) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvld1_mult_16_4_256    : PROCregs21(4) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvld1_mult_16_4_256_wb : PROCregs21(4) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvld1_mult_16_4_256_rm : PROCregs21(4) : [ OPT 2 : VLD1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256],Rm% : B aftertest% : ] : =32
DEF FNvld1_mult_32_1_xxx    : PROCregs21(1) : [ OPT 2 : VLD1.32 {D#Vd%                              },[Rn%    ]     : B aftertest% : ] : =8
DEF FNvld1_mult_32_1_xxx_wb : PROCregs21(1) : [ OPT 2 : VLD1.32 {D#Vd%                              },[Rn%    ]!    : B aftertest% : ] : =8
DEF FNvld1_mult_32_1_xxx_rm : PROCregs21(1) : [ OPT 2 : VLD1.32 {D#Vd%                              },[Rn%    ],Rm% : B aftertest% : ] : =8
DEF FNvld1_mult_32_1_064    : PROCregs21(1) : [ OPT 2 : VLD1.32 {D#Vd%                              },[Rn%@64 ]     : B aftertest% : ] : =8
DEF FNvld1_mult_32_1_064_wb : PROCregs21(1) : [ OPT 2 : VLD1.32 {D#Vd%                              },[Rn%@64 ]!    : B aftertest% : ] : =8
DEF FNvld1_mult_32_1_064_rm : PROCregs21(1) : [ OPT 2 : VLD1.32 {D#Vd%                              },[Rn%@64 ],Rm% : B aftertest% : ] : =8
DEF FNvld1_mult_32_2_xxx    : PROCregs21(2) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1)                    },[Rn%    ]     : B aftertest% : ] : =16
DEF FNvld1_mult_32_2_xxx_wb : PROCregs21(2) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1)                    },[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvld1_mult_32_2_xxx_rm : PROCregs21(2) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1)                    },[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvld1_mult_32_2_064    : PROCregs21(2) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]     : B aftertest% : ] : =16
DEF FNvld1_mult_32_2_064_wb : PROCregs21(2) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]!    : B aftertest% : ] : =16
DEF FNvld1_mult_32_2_064_rm : PROCregs21(2) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ],Rm% : B aftertest% : ] : =16
DEF FNvld1_mult_32_2_128    : PROCregs21(2) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1)                    },[Rn%@128]     : B aftertest% : ] : =16
DEF FNvld1_mult_32_2_128_wb : PROCregs21(2) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1)                    },[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvld1_mult_32_2_128_rm : PROCregs21(2) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1)                    },[Rn%@128],Rm% : B aftertest% : ] : =16
DEF FNvld1_mult_32_3_xxx    : PROCregs21(3) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]     : B aftertest% : ] : =24
DEF FNvld1_mult_32_3_xxx_wb : PROCregs21(3) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]!    : B aftertest% : ] : =24
DEF FNvld1_mult_32_3_xxx_rm : PROCregs21(3) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ],Rm% : B aftertest% : ] : =24
DEF FNvld1_mult_32_3_064    : PROCregs21(3) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]     : B aftertest% : ] : =24
DEF FNvld1_mult_32_3_064_wb : PROCregs21(3) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]!    : B aftertest% : ] : =24
DEF FNvld1_mult_32_3_064_rm : PROCregs21(3) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ],Rm% : B aftertest% : ] : =24
DEF FNvld1_mult_32_4_xxx    : PROCregs21(4) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvld1_mult_32_4_xxx_wb : PROCregs21(4) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvld1_mult_32_4_xxx_rm : PROCregs21(4) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvld1_mult_32_4_064    : PROCregs21(4) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvld1_mult_32_4_064_wb : PROCregs21(4) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvld1_mult_32_4_064_rm : PROCregs21(4) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvld1_mult_32_4_128    : PROCregs21(4) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvld1_mult_32_4_128_wb : PROCregs21(4) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvld1_mult_32_4_128_rm : PROCregs21(4) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvld1_mult_32_4_256    : PROCregs21(4) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvld1_mult_32_4_256_wb : PROCregs21(4) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvld1_mult_32_4_256_rm : PROCregs21(4) : [ OPT 2 : VLD1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256],Rm% : B aftertest% : ] : =32
DEF FNvld1_mult_64_1_xxx    : PROCregs21(1) : [ OPT 2 : VLD1.64 {D#Vd%                              },[Rn%    ]     : B aftertest% : ] : =8
DEF FNvld1_mult_64_1_xxx_wb : PROCregs21(1) : [ OPT 2 : VLD1.64 {D#Vd%                              },[Rn%    ]!    : B aftertest% : ] : =8
DEF FNvld1_mult_64_1_xxx_rm : PROCregs21(1) : [ OPT 2 : VLD1.64 {D#Vd%                              },[Rn%    ],Rm% : B aftertest% : ] : =8
DEF FNvld1_mult_64_1_064    : PROCregs21(1) : [ OPT 2 : VLD1.64 {D#Vd%                              },[Rn%@64 ]     : B aftertest% : ] : =8
DEF FNvld1_mult_64_1_064_wb : PROCregs21(1) : [ OPT 2 : VLD1.64 {D#Vd%                              },[Rn%@64 ]!    : B aftertest% : ] : =8
DEF FNvld1_mult_64_1_064_rm : PROCregs21(1) : [ OPT 2 : VLD1.64 {D#Vd%                              },[Rn%@64 ],Rm% : B aftertest% : ] : =8
DEF FNvld1_mult_64_2_xxx    : PROCregs21(2) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1)                    },[Rn%    ]     : B aftertest% : ] : =16
DEF FNvld1_mult_64_2_xxx_wb : PROCregs21(2) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1)                    },[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvld1_mult_64_2_xxx_rm : PROCregs21(2) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1)                    },[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvld1_mult_64_2_064    : PROCregs21(2) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]     : B aftertest% : ] : =16
DEF FNvld1_mult_64_2_064_wb : PROCregs21(2) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]!    : B aftertest% : ] : =16
DEF FNvld1_mult_64_2_064_rm : PROCregs21(2) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ],Rm% : B aftertest% : ] : =16
DEF FNvld1_mult_64_2_128    : PROCregs21(2) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1)                    },[Rn%@128]     : B aftertest% : ] : =16
DEF FNvld1_mult_64_2_128_wb : PROCregs21(2) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1)                    },[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvld1_mult_64_2_128_rm : PROCregs21(2) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1)                    },[Rn%@128],Rm% : B aftertest% : ] : =16
DEF FNvld1_mult_64_3_xxx    : PROCregs21(3) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]     : B aftertest% : ] : =24
DEF FNvld1_mult_64_3_xxx_wb : PROCregs21(3) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]!    : B aftertest% : ] : =24
DEF FNvld1_mult_64_3_xxx_rm : PROCregs21(3) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ],Rm% : B aftertest% : ] : =24
DEF FNvld1_mult_64_3_064    : PROCregs21(3) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]     : B aftertest% : ] : =24
DEF FNvld1_mult_64_3_064_wb : PROCregs21(3) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]!    : B aftertest% : ] : =24
DEF FNvld1_mult_64_3_064_rm : PROCregs21(3) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ],Rm% : B aftertest% : ] : =24
DEF FNvld1_mult_64_4_xxx    : PROCregs21(4) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvld1_mult_64_4_xxx_wb : PROCregs21(4) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvld1_mult_64_4_xxx_rm : PROCregs21(4) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvld1_mult_64_4_064    : PROCregs21(4) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvld1_mult_64_4_064_wb : PROCregs21(4) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvld1_mult_64_4_064_rm : PROCregs21(4) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvld1_mult_64_4_128    : PROCregs21(4) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvld1_mult_64_4_128_wb : PROCregs21(4) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvld1_mult_64_4_128_rm : PROCregs21(4) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvld1_mult_64_4_256    : PROCregs21(4) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvld1_mult_64_4_256_wb : PROCregs21(4) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvld1_mult_64_4_256_rm : PROCregs21(4) : [ OPT 2 : VLD1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256],Rm% : B aftertest% : ] : =32

DEF FNvst1_mult_08_1_xxx    : PROCregs21(1) : [ OPT 2 : VST1.8  {D#Vd%                              },[Rn%    ]     : B aftertest% : ] : =8
DEF FNvst1_mult_08_1_xxx_wb : PROCregs21(1) : [ OPT 2 : VST1.8  {D#Vd%                              },[Rn%    ]!    : B aftertest% : ] : =8
DEF FNvst1_mult_08_1_xxx_rm : PROCregs21(1) : [ OPT 2 : VST1.8  {D#Vd%                              },[Rn%    ],Rm% : B aftertest% : ] : =8
DEF FNvst1_mult_08_1_064    : PROCregs21(1) : [ OPT 2 : VST1.8  {D#Vd%                              },[Rn%@64 ]     : B aftertest% : ] : =8
DEF FNvst1_mult_08_1_064_wb : PROCregs21(1) : [ OPT 2 : VST1.8  {D#Vd%                              },[Rn%@64 ]!    : B aftertest% : ] : =8
DEF FNvst1_mult_08_1_064_rm : PROCregs21(1) : [ OPT 2 : VST1.8  {D#Vd%                              },[Rn%@64 ],Rm% : B aftertest% : ] : =8
DEF FNvst1_mult_08_2_xxx    : PROCregs21(2) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1)                    },[Rn%    ]     : B aftertest% : ] : =16
DEF FNvst1_mult_08_2_xxx_wb : PROCregs21(2) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1)                    },[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvst1_mult_08_2_xxx_rm : PROCregs21(2) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1)                    },[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvst1_mult_08_2_064    : PROCregs21(2) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]     : B aftertest% : ] : =16
DEF FNvst1_mult_08_2_064_wb : PROCregs21(2) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]!    : B aftertest% : ] : =16
DEF FNvst1_mult_08_2_064_rm : PROCregs21(2) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ],Rm% : B aftertest% : ] : =16
DEF FNvst1_mult_08_2_128    : PROCregs21(2) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1)                    },[Rn%@128]     : B aftertest% : ] : =16
DEF FNvst1_mult_08_2_128_wb : PROCregs21(2) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1)                    },[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvst1_mult_08_2_128_rm : PROCregs21(2) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1)                    },[Rn%@128],Rm% : B aftertest% : ] : =16
DEF FNvst1_mult_08_3_xxx    : PROCregs21(3) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]     : B aftertest% : ] : =24
DEF FNvst1_mult_08_3_xxx_wb : PROCregs21(3) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]!    : B aftertest% : ] : =24
DEF FNvst1_mult_08_3_xxx_rm : PROCregs21(3) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ],Rm% : B aftertest% : ] : =24
DEF FNvst1_mult_08_3_064    : PROCregs21(3) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]     : B aftertest% : ] : =24
DEF FNvst1_mult_08_3_064_wb : PROCregs21(3) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]!    : B aftertest% : ] : =24
DEF FNvst1_mult_08_3_064_rm : PROCregs21(3) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ],Rm% : B aftertest% : ] : =24
DEF FNvst1_mult_08_4_xxx    : PROCregs21(4) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvst1_mult_08_4_xxx_wb : PROCregs21(4) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvst1_mult_08_4_xxx_rm : PROCregs21(4) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvst1_mult_08_4_064    : PROCregs21(4) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvst1_mult_08_4_064_wb : PROCregs21(4) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvst1_mult_08_4_064_rm : PROCregs21(4) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvst1_mult_08_4_128    : PROCregs21(4) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvst1_mult_08_4_128_wb : PROCregs21(4) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvst1_mult_08_4_128_rm : PROCregs21(4) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvst1_mult_08_4_256    : PROCregs21(4) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvst1_mult_08_4_256_wb : PROCregs21(4) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvst1_mult_08_4_256_rm : PROCregs21(4) : [ OPT 2 : VST1.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256],Rm% : B aftertest% : ] : =32
DEF FNvst1_mult_16_1_xxx    : PROCregs21(1) : [ OPT 2 : VST1.16 {D#Vd%                              },[Rn%    ]     : B aftertest% : ] : =8
DEF FNvst1_mult_16_1_xxx_wb : PROCregs21(1) : [ OPT 2 : VST1.16 {D#Vd%                              },[Rn%    ]!    : B aftertest% : ] : =8
DEF FNvst1_mult_16_1_xxx_rm : PROCregs21(1) : [ OPT 2 : VST1.16 {D#Vd%                              },[Rn%    ],Rm% : B aftertest% : ] : =8
DEF FNvst1_mult_16_1_064    : PROCregs21(1) : [ OPT 2 : VST1.16 {D#Vd%                              },[Rn%@64 ]     : B aftertest% : ] : =8
DEF FNvst1_mult_16_1_064_wb : PROCregs21(1) : [ OPT 2 : VST1.16 {D#Vd%                              },[Rn%@64 ]!    : B aftertest% : ] : =8
DEF FNvst1_mult_16_1_064_rm : PROCregs21(1) : [ OPT 2 : VST1.16 {D#Vd%                              },[Rn%@64 ],Rm% : B aftertest% : ] : =8
DEF FNvst1_mult_16_2_xxx    : PROCregs21(2) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1)                    },[Rn%    ]     : B aftertest% : ] : =16
DEF FNvst1_mult_16_2_xxx_wb : PROCregs21(2) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1)                    },[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvst1_mult_16_2_xxx_rm : PROCregs21(2) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1)                    },[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvst1_mult_16_2_064    : PROCregs21(2) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]     : B aftertest% : ] : =16
DEF FNvst1_mult_16_2_064_wb : PROCregs21(2) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]!    : B aftertest% : ] : =16
DEF FNvst1_mult_16_2_064_rm : PROCregs21(2) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ],Rm% : B aftertest% : ] : =16
DEF FNvst1_mult_16_2_128    : PROCregs21(2) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1)                    },[Rn%@128]     : B aftertest% : ] : =16
DEF FNvst1_mult_16_2_128_wb : PROCregs21(2) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1)                    },[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvst1_mult_16_2_128_rm : PROCregs21(2) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1)                    },[Rn%@128],Rm% : B aftertest% : ] : =16
DEF FNvst1_mult_16_3_xxx    : PROCregs21(3) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]     : B aftertest% : ] : =24
DEF FNvst1_mult_16_3_xxx_wb : PROCregs21(3) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]!    : B aftertest% : ] : =24
DEF FNvst1_mult_16_3_xxx_rm : PROCregs21(3) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ],Rm% : B aftertest% : ] : =24
DEF FNvst1_mult_16_3_064    : PROCregs21(3) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]     : B aftertest% : ] : =24
DEF FNvst1_mult_16_3_064_wb : PROCregs21(3) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]!    : B aftertest% : ] : =24
DEF FNvst1_mult_16_3_064_rm : PROCregs21(3) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ],Rm% : B aftertest% : ] : =24
DEF FNvst1_mult_16_4_xxx    : PROCregs21(4) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvst1_mult_16_4_xxx_wb : PROCregs21(4) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvst1_mult_16_4_xxx_rm : PROCregs21(4) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvst1_mult_16_4_064    : PROCregs21(4) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvst1_mult_16_4_064_wb : PROCregs21(4) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvst1_mult_16_4_064_rm : PROCregs21(4) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvst1_mult_16_4_128    : PROCregs21(4) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvst1_mult_16_4_128_wb : PROCregs21(4) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvst1_mult_16_4_128_rm : PROCregs21(4) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvst1_mult_16_4_256    : PROCregs21(4) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvst1_mult_16_4_256_wb : PROCregs21(4) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvst1_mult_16_4_256_rm : PROCregs21(4) : [ OPT 2 : VST1.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256],Rm% : B aftertest% : ] : =32
DEF FNvst1_mult_32_1_xxx    : PROCregs21(1) : [ OPT 2 : VST1.32 {D#Vd%                              },[Rn%    ]     : B aftertest% : ] : =8
DEF FNvst1_mult_32_1_xxx_wb : PROCregs21(1) : [ OPT 2 : VST1.32 {D#Vd%                              },[Rn%    ]!    : B aftertest% : ] : =8
DEF FNvst1_mult_32_1_xxx_rm : PROCregs21(1) : [ OPT 2 : VST1.32 {D#Vd%                              },[Rn%    ],Rm% : B aftertest% : ] : =8
DEF FNvst1_mult_32_1_064    : PROCregs21(1) : [ OPT 2 : VST1.32 {D#Vd%                              },[Rn%@64 ]     : B aftertest% : ] : =8
DEF FNvst1_mult_32_1_064_wb : PROCregs21(1) : [ OPT 2 : VST1.32 {D#Vd%                              },[Rn%@64 ]!    : B aftertest% : ] : =8
DEF FNvst1_mult_32_1_064_rm : PROCregs21(1) : [ OPT 2 : VST1.32 {D#Vd%                              },[Rn%@64 ],Rm% : B aftertest% : ] : =8
DEF FNvst1_mult_32_2_xxx    : PROCregs21(2) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1)                    },[Rn%    ]     : B aftertest% : ] : =16
DEF FNvst1_mult_32_2_xxx_wb : PROCregs21(2) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1)                    },[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvst1_mult_32_2_xxx_rm : PROCregs21(2) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1)                    },[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvst1_mult_32_2_064    : PROCregs21(2) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]     : B aftertest% : ] : =16
DEF FNvst1_mult_32_2_064_wb : PROCregs21(2) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]!    : B aftertest% : ] : =16
DEF FNvst1_mult_32_2_064_rm : PROCregs21(2) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ],Rm% : B aftertest% : ] : =16
DEF FNvst1_mult_32_2_128    : PROCregs21(2) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1)                    },[Rn%@128]     : B aftertest% : ] : =16
DEF FNvst1_mult_32_2_128_wb : PROCregs21(2) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1)                    },[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvst1_mult_32_2_128_rm : PROCregs21(2) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1)                    },[Rn%@128],Rm% : B aftertest% : ] : =16
DEF FNvst1_mult_32_3_xxx    : PROCregs21(3) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]     : B aftertest% : ] : =24
DEF FNvst1_mult_32_3_xxx_wb : PROCregs21(3) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]!    : B aftertest% : ] : =24
DEF FNvst1_mult_32_3_xxx_rm : PROCregs21(3) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ],Rm% : B aftertest% : ] : =24
DEF FNvst1_mult_32_3_064    : PROCregs21(3) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]     : B aftertest% : ] : =24
DEF FNvst1_mult_32_3_064_wb : PROCregs21(3) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]!    : B aftertest% : ] : =24
DEF FNvst1_mult_32_3_064_rm : PROCregs21(3) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ],Rm% : B aftertest% : ] : =24
DEF FNvst1_mult_32_4_xxx    : PROCregs21(4) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvst1_mult_32_4_xxx_wb : PROCregs21(4) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvst1_mult_32_4_xxx_rm : PROCregs21(4) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvst1_mult_32_4_064    : PROCregs21(4) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvst1_mult_32_4_064_wb : PROCregs21(4) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvst1_mult_32_4_064_rm : PROCregs21(4) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvst1_mult_32_4_128    : PROCregs21(4) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvst1_mult_32_4_128_wb : PROCregs21(4) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvst1_mult_32_4_128_rm : PROCregs21(4) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvst1_mult_32_4_256    : PROCregs21(4) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvst1_mult_32_4_256_wb : PROCregs21(4) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvst1_mult_32_4_256_rm : PROCregs21(4) : [ OPT 2 : VST1.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256],Rm% : B aftertest% : ] : =32
DEF FNvst1_mult_64_1_xxx    : PROCregs21(1) : [ OPT 2 : VST1.64 {D#Vd%                              },[Rn%    ]     : B aftertest% : ] : =8
DEF FNvst1_mult_64_1_xxx_wb : PROCregs21(1) : [ OPT 2 : VST1.64 {D#Vd%                              },[Rn%    ]!    : B aftertest% : ] : =8
DEF FNvst1_mult_64_1_xxx_rm : PROCregs21(1) : [ OPT 2 : VST1.64 {D#Vd%                              },[Rn%    ],Rm% : B aftertest% : ] : =8
DEF FNvst1_mult_64_1_064    : PROCregs21(1) : [ OPT 2 : VST1.64 {D#Vd%                              },[Rn%@64 ]     : B aftertest% : ] : =8
DEF FNvst1_mult_64_1_064_wb : PROCregs21(1) : [ OPT 2 : VST1.64 {D#Vd%                              },[Rn%@64 ]!    : B aftertest% : ] : =8
DEF FNvst1_mult_64_1_064_rm : PROCregs21(1) : [ OPT 2 : VST1.64 {D#Vd%                              },[Rn%@64 ],Rm% : B aftertest% : ] : =8
DEF FNvst1_mult_64_2_xxx    : PROCregs21(2) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1)                    },[Rn%    ]     : B aftertest% : ] : =16
DEF FNvst1_mult_64_2_xxx_wb : PROCregs21(2) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1)                    },[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvst1_mult_64_2_xxx_rm : PROCregs21(2) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1)                    },[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvst1_mult_64_2_064    : PROCregs21(2) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]     : B aftertest% : ] : =16
DEF FNvst1_mult_64_2_064_wb : PROCregs21(2) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]!    : B aftertest% : ] : =16
DEF FNvst1_mult_64_2_064_rm : PROCregs21(2) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ],Rm% : B aftertest% : ] : =16
DEF FNvst1_mult_64_2_128    : PROCregs21(2) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1)                    },[Rn%@128]     : B aftertest% : ] : =16
DEF FNvst1_mult_64_2_128_wb : PROCregs21(2) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1)                    },[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvst1_mult_64_2_128_rm : PROCregs21(2) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1)                    },[Rn%@128],Rm% : B aftertest% : ] : =16
DEF FNvst1_mult_64_3_xxx    : PROCregs21(3) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]     : B aftertest% : ] : =24
DEF FNvst1_mult_64_3_xxx_wb : PROCregs21(3) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]!    : B aftertest% : ] : =24
DEF FNvst1_mult_64_3_xxx_rm : PROCregs21(3) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ],Rm% : B aftertest% : ] : =24
DEF FNvst1_mult_64_3_064    : PROCregs21(3) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]     : B aftertest% : ] : =24
DEF FNvst1_mult_64_3_064_wb : PROCregs21(3) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]!    : B aftertest% : ] : =24
DEF FNvst1_mult_64_3_064_rm : PROCregs21(3) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ],Rm% : B aftertest% : ] : =24
DEF FNvst1_mult_64_4_xxx    : PROCregs21(4) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvst1_mult_64_4_xxx_wb : PROCregs21(4) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvst1_mult_64_4_xxx_rm : PROCregs21(4) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvst1_mult_64_4_064    : PROCregs21(4) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvst1_mult_64_4_064_wb : PROCregs21(4) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvst1_mult_64_4_064_rm : PROCregs21(4) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvst1_mult_64_4_128    : PROCregs21(4) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvst1_mult_64_4_128_wb : PROCregs21(4) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvst1_mult_64_4_128_rm : PROCregs21(4) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvst1_mult_64_4_256    : PROCregs21(4) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvst1_mult_64_4_256_wb : PROCregs21(4) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvst1_mult_64_4_256_rm : PROCregs21(4) : [ OPT 2 : VST1.64 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256],Rm% : B aftertest% : ] : =32

REM VLD/VST multiple 2-element structures

DEF FNvld2_mult_08_2_xxx    : PROCregs21(2) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+1)                    },[Rn%    ]     : B aftertest% : ] : =16
DEF FNvld2_mult_08_2_xxx_wb : PROCregs21(2) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+1)                    },[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvld2_mult_08_2_xxx_rm : PROCregs21(2) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+1)                    },[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvld2_mult_08_2_064    : PROCregs21(2) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]     : B aftertest% : ] : =16
DEF FNvld2_mult_08_2_064_wb : PROCregs21(2) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]!    : B aftertest% : ] : =16
DEF FNvld2_mult_08_2_064_rm : PROCregs21(2) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ],Rm% : B aftertest% : ] : =16
DEF FNvld2_mult_08_2_128    : PROCregs21(2) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+1)                    },[Rn%@128]     : B aftertest% : ] : =16
DEF FNvld2_mult_08_2_128_wb : PROCregs21(2) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+1)                    },[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvld2_mult_08_2_128_rm : PROCregs21(2) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+1)                    },[Rn%@128],Rm% : B aftertest% : ] : =16
DEF FNvld2_mult_08_d_xxx    : PROCregs21(3) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+2)                    },[Rn%    ]     : B aftertest% : ] : =16
DEF FNvld2_mult_08_d_xxx_wb : PROCregs21(3) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+2)                    },[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvld2_mult_08_d_xxx_rm : PROCregs21(3) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+2)                    },[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvld2_mult_08_d_064    : PROCregs21(3) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+2)                    },[Rn%@64 ]     : B aftertest% : ] : =16
DEF FNvld2_mult_08_d_064_wb : PROCregs21(3) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+2)                    },[Rn%@64 ]!    : B aftertest% : ] : =16
DEF FNvld2_mult_08_d_064_rm : PROCregs21(3) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+2)                    },[Rn%@64 ],Rm% : B aftertest% : ] : =16
DEF FNvld2_mult_08_d_128    : PROCregs21(3) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+2)                    },[Rn%@128]     : B aftertest% : ] : =16
DEF FNvld2_mult_08_d_128_wb : PROCregs21(3) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+2)                    },[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvld2_mult_08_d_128_rm : PROCregs21(3) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+2)                    },[Rn%@128],Rm% : B aftertest% : ] : =16
DEF FNvld2_mult_08_4_xxx    : PROCregs21(4) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvld2_mult_08_4_xxx_wb : PROCregs21(4) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvld2_mult_08_4_xxx_rm : PROCregs21(4) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvld2_mult_08_4_064    : PROCregs21(4) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvld2_mult_08_4_064_wb : PROCregs21(4) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvld2_mult_08_4_064_rm : PROCregs21(4) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvld2_mult_08_4_128    : PROCregs21(4) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvld2_mult_08_4_128_wb : PROCregs21(4) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvld2_mult_08_4_128_rm : PROCregs21(4) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvld2_mult_08_4_256    : PROCregs21(4) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvld2_mult_08_4_256_wb : PROCregs21(4) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvld2_mult_08_4_256_rm : PROCregs21(4) : [ OPT 2 : VLD2.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256],Rm% : B aftertest% : ] : =32
DEF FNvld2_mult_16_2_xxx    : PROCregs21(2) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+1)                    },[Rn%    ]     : B aftertest% : ] : =16
DEF FNvld2_mult_16_2_xxx_wb : PROCregs21(2) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+1)                    },[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvld2_mult_16_2_xxx_rm : PROCregs21(2) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+1)                    },[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvld2_mult_16_2_064    : PROCregs21(2) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]     : B aftertest% : ] : =16
DEF FNvld2_mult_16_2_064_wb : PROCregs21(2) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]!    : B aftertest% : ] : =16
DEF FNvld2_mult_16_2_064_rm : PROCregs21(2) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ],Rm% : B aftertest% : ] : =16
DEF FNvld2_mult_16_2_128    : PROCregs21(2) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+1)                    },[Rn%@128]     : B aftertest% : ] : =16
DEF FNvld2_mult_16_2_128_wb : PROCregs21(2) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+1)                    },[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvld2_mult_16_2_128_rm : PROCregs21(2) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+1)                    },[Rn%@128],Rm% : B aftertest% : ] : =16
DEF FNvld2_mult_16_d_xxx    : PROCregs21(3) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+2)                    },[Rn%    ]     : B aftertest% : ] : =16
DEF FNvld2_mult_16_d_xxx_wb : PROCregs21(3) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+2)                    },[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvld2_mult_16_d_xxx_rm : PROCregs21(3) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+2)                    },[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvld2_mult_16_d_064    : PROCregs21(3) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+2)                    },[Rn%@64 ]     : B aftertest% : ] : =16
DEF FNvld2_mult_16_d_064_wb : PROCregs21(3) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+2)                    },[Rn%@64 ]!    : B aftertest% : ] : =16
DEF FNvld2_mult_16_d_064_rm : PROCregs21(3) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+2)                    },[Rn%@64 ],Rm% : B aftertest% : ] : =16
DEF FNvld2_mult_16_d_128    : PROCregs21(3) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+2)                    },[Rn%@128]     : B aftertest% : ] : =16
DEF FNvld2_mult_16_d_128_wb : PROCregs21(3) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+2)                    },[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvld2_mult_16_d_128_rm : PROCregs21(3) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+2)                    },[Rn%@128],Rm% : B aftertest% : ] : =16
DEF FNvld2_mult_16_4_xxx    : PROCregs21(4) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvld2_mult_16_4_xxx_wb : PROCregs21(4) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvld2_mult_16_4_xxx_rm : PROCregs21(4) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvld2_mult_16_4_064    : PROCregs21(4) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvld2_mult_16_4_064_wb : PROCregs21(4) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvld2_mult_16_4_064_rm : PROCregs21(4) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvld2_mult_16_4_128    : PROCregs21(4) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvld2_mult_16_4_128_wb : PROCregs21(4) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvld2_mult_16_4_128_rm : PROCregs21(4) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvld2_mult_16_4_256    : PROCregs21(4) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvld2_mult_16_4_256_wb : PROCregs21(4) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvld2_mult_16_4_256_rm : PROCregs21(4) : [ OPT 2 : VLD2.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256],Rm% : B aftertest% : ] : =32
DEF FNvld2_mult_32_2_xxx    : PROCregs21(2) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+1)                    },[Rn%    ]     : B aftertest% : ] : =16
DEF FNvld2_mult_32_2_xxx_wb : PROCregs21(2) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+1)                    },[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvld2_mult_32_2_xxx_rm : PROCregs21(2) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+1)                    },[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvld2_mult_32_2_064    : PROCregs21(2) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]     : B aftertest% : ] : =16
DEF FNvld2_mult_32_2_064_wb : PROCregs21(2) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]!    : B aftertest% : ] : =16
DEF FNvld2_mult_32_2_064_rm : PROCregs21(2) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ],Rm% : B aftertest% : ] : =16
DEF FNvld2_mult_32_2_128    : PROCregs21(2) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+1)                    },[Rn%@128]     : B aftertest% : ] : =16
DEF FNvld2_mult_32_2_128_wb : PROCregs21(2) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+1)                    },[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvld2_mult_32_2_128_rm : PROCregs21(2) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+1)                    },[Rn%@128],Rm% : B aftertest% : ] : =16
DEF FNvld2_mult_32_d_xxx    : PROCregs21(3) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+2)                    },[Rn%    ]     : B aftertest% : ] : =16
DEF FNvld2_mult_32_d_xxx_wb : PROCregs21(3) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+2)                    },[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvld2_mult_32_d_xxx_rm : PROCregs21(3) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+2)                    },[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvld2_mult_32_d_064    : PROCregs21(3) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+2)                    },[Rn%@64 ]     : B aftertest% : ] : =16
DEF FNvld2_mult_32_d_064_wb : PROCregs21(3) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+2)                    },[Rn%@64 ]!    : B aftertest% : ] : =16
DEF FNvld2_mult_32_d_064_rm : PROCregs21(3) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+2)                    },[Rn%@64 ],Rm% : B aftertest% : ] : =16
DEF FNvld2_mult_32_d_128    : PROCregs21(3) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+2)                    },[Rn%@128]     : B aftertest% : ] : =16
DEF FNvld2_mult_32_d_128_wb : PROCregs21(3) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+2)                    },[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvld2_mult_32_d_128_rm : PROCregs21(3) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+2)                    },[Rn%@128],Rm% : B aftertest% : ] : =16
DEF FNvld2_mult_32_4_xxx    : PROCregs21(4) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvld2_mult_32_4_xxx_wb : PROCregs21(4) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvld2_mult_32_4_xxx_rm : PROCregs21(4) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvld2_mult_32_4_064    : PROCregs21(4) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvld2_mult_32_4_064_wb : PROCregs21(4) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvld2_mult_32_4_064_rm : PROCregs21(4) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvld2_mult_32_4_128    : PROCregs21(4) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvld2_mult_32_4_128_wb : PROCregs21(4) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvld2_mult_32_4_128_rm : PROCregs21(4) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvld2_mult_32_4_256    : PROCregs21(4) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvld2_mult_32_4_256_wb : PROCregs21(4) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvld2_mult_32_4_256_rm : PROCregs21(4) : [ OPT 2 : VLD2.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256],Rm% : B aftertest% : ] : =32

DEF FNvst2_mult_08_2_xxx    : PROCregs21(2) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+1)                    },[Rn%    ]     : B aftertest% : ] : =16
DEF FNvst2_mult_08_2_xxx_wb : PROCregs21(2) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+1)                    },[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvst2_mult_08_2_xxx_rm : PROCregs21(2) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+1)                    },[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvst2_mult_08_2_064    : PROCregs21(2) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]     : B aftertest% : ] : =16
DEF FNvst2_mult_08_2_064_wb : PROCregs21(2) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]!    : B aftertest% : ] : =16
DEF FNvst2_mult_08_2_064_rm : PROCregs21(2) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ],Rm% : B aftertest% : ] : =16
DEF FNvst2_mult_08_2_128    : PROCregs21(2) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+1)                    },[Rn%@128]     : B aftertest% : ] : =16
DEF FNvst2_mult_08_2_128_wb : PROCregs21(2) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+1)                    },[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvst2_mult_08_2_128_rm : PROCregs21(2) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+1)                    },[Rn%@128],Rm% : B aftertest% : ] : =16
DEF FNvst2_mult_08_d_xxx    : PROCregs21(3) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+2)                    },[Rn%    ]     : B aftertest% : ] : =16
DEF FNvst2_mult_08_d_xxx_wb : PROCregs21(3) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+2)                    },[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvst2_mult_08_d_xxx_rm : PROCregs21(3) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+2)                    },[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvst2_mult_08_d_064    : PROCregs21(3) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+2)                    },[Rn%@64 ]     : B aftertest% : ] : =16
DEF FNvst2_mult_08_d_064_wb : PROCregs21(3) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+2)                    },[Rn%@64 ]!    : B aftertest% : ] : =16
DEF FNvst2_mult_08_d_064_rm : PROCregs21(3) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+2)                    },[Rn%@64 ],Rm% : B aftertest% : ] : =16
DEF FNvst2_mult_08_d_128    : PROCregs21(3) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+2)                    },[Rn%@128]     : B aftertest% : ] : =16
DEF FNvst2_mult_08_d_128_wb : PROCregs21(3) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+2)                    },[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvst2_mult_08_d_128_rm : PROCregs21(3) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+2)                    },[Rn%@128],Rm% : B aftertest% : ] : =16
DEF FNvst2_mult_08_4_xxx    : PROCregs21(4) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvst2_mult_08_4_xxx_wb : PROCregs21(4) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvst2_mult_08_4_xxx_rm : PROCregs21(4) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvst2_mult_08_4_064    : PROCregs21(4) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvst2_mult_08_4_064_wb : PROCregs21(4) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvst2_mult_08_4_064_rm : PROCregs21(4) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvst2_mult_08_4_128    : PROCregs21(4) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvst2_mult_08_4_128_wb : PROCregs21(4) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvst2_mult_08_4_128_rm : PROCregs21(4) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvst2_mult_08_4_256    : PROCregs21(4) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvst2_mult_08_4_256_wb : PROCregs21(4) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvst2_mult_08_4_256_rm : PROCregs21(4) : [ OPT 2 : VST2.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256],Rm% : B aftertest% : ] : =32
DEF FNvst2_mult_16_2_xxx    : PROCregs21(2) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+1)                    },[Rn%    ]     : B aftertest% : ] : =16
DEF FNvst2_mult_16_2_xxx_wb : PROCregs21(2) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+1)                    },[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvst2_mult_16_2_xxx_rm : PROCregs21(2) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+1)                    },[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvst2_mult_16_2_064    : PROCregs21(2) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]     : B aftertest% : ] : =16
DEF FNvst2_mult_16_2_064_wb : PROCregs21(2) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]!    : B aftertest% : ] : =16
DEF FNvst2_mult_16_2_064_rm : PROCregs21(2) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ],Rm% : B aftertest% : ] : =16
DEF FNvst2_mult_16_2_128    : PROCregs21(2) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+1)                    },[Rn%@128]     : B aftertest% : ] : =16
DEF FNvst2_mult_16_2_128_wb : PROCregs21(2) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+1)                    },[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvst2_mult_16_2_128_rm : PROCregs21(2) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+1)                    },[Rn%@128],Rm% : B aftertest% : ] : =16
DEF FNvst2_mult_16_d_xxx    : PROCregs21(3) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+2)                    },[Rn%    ]     : B aftertest% : ] : =16
DEF FNvst2_mult_16_d_xxx_wb : PROCregs21(3) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+2)                    },[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvst2_mult_16_d_xxx_rm : PROCregs21(3) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+2)                    },[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvst2_mult_16_d_064    : PROCregs21(3) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+2)                    },[Rn%@64 ]     : B aftertest% : ] : =16
DEF FNvst2_mult_16_d_064_wb : PROCregs21(3) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+2)                    },[Rn%@64 ]!    : B aftertest% : ] : =16
DEF FNvst2_mult_16_d_064_rm : PROCregs21(3) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+2)                    },[Rn%@64 ],Rm% : B aftertest% : ] : =16
DEF FNvst2_mult_16_d_128    : PROCregs21(3) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+2)                    },[Rn%@128]     : B aftertest% : ] : =16
DEF FNvst2_mult_16_d_128_wb : PROCregs21(3) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+2)                    },[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvst2_mult_16_d_128_rm : PROCregs21(3) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+2)                    },[Rn%@128],Rm% : B aftertest% : ] : =16
DEF FNvst2_mult_16_4_xxx    : PROCregs21(4) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvst2_mult_16_4_xxx_wb : PROCregs21(4) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvst2_mult_16_4_xxx_rm : PROCregs21(4) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvst2_mult_16_4_064    : PROCregs21(4) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvst2_mult_16_4_064_wb : PROCregs21(4) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvst2_mult_16_4_064_rm : PROCregs21(4) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvst2_mult_16_4_128    : PROCregs21(4) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvst2_mult_16_4_128_wb : PROCregs21(4) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvst2_mult_16_4_128_rm : PROCregs21(4) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvst2_mult_16_4_256    : PROCregs21(4) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvst2_mult_16_4_256_wb : PROCregs21(4) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvst2_mult_16_4_256_rm : PROCregs21(4) : [ OPT 2 : VST2.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256],Rm% : B aftertest% : ] : =32
DEF FNvst2_mult_32_2_xxx    : PROCregs21(2) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+1)                    },[Rn%    ]     : B aftertest% : ] : =16
DEF FNvst2_mult_32_2_xxx_wb : PROCregs21(2) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+1)                    },[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvst2_mult_32_2_xxx_rm : PROCregs21(2) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+1)                    },[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvst2_mult_32_2_064    : PROCregs21(2) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]     : B aftertest% : ] : =16
DEF FNvst2_mult_32_2_064_wb : PROCregs21(2) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ]!    : B aftertest% : ] : =16
DEF FNvst2_mult_32_2_064_rm : PROCregs21(2) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+1)                    },[Rn%@64 ],Rm% : B aftertest% : ] : =16
DEF FNvst2_mult_32_2_128    : PROCregs21(2) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+1)                    },[Rn%@128]     : B aftertest% : ] : =16
DEF FNvst2_mult_32_2_128_wb : PROCregs21(2) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+1)                    },[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvst2_mult_32_2_128_rm : PROCregs21(2) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+1)                    },[Rn%@128],Rm% : B aftertest% : ] : =16
DEF FNvst2_mult_32_d_xxx    : PROCregs21(3) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+2)                    },[Rn%    ]     : B aftertest% : ] : =16
DEF FNvst2_mult_32_d_xxx_wb : PROCregs21(3) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+2)                    },[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvst2_mult_32_d_xxx_rm : PROCregs21(3) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+2)                    },[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvst2_mult_32_d_064    : PROCregs21(3) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+2)                    },[Rn%@64 ]     : B aftertest% : ] : =16
DEF FNvst2_mult_32_d_064_wb : PROCregs21(3) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+2)                    },[Rn%@64 ]!    : B aftertest% : ] : =16
DEF FNvst2_mult_32_d_064_rm : PROCregs21(3) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+2)                    },[Rn%@64 ],Rm% : B aftertest% : ] : =16
DEF FNvst2_mult_32_d_128    : PROCregs21(3) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+2)                    },[Rn%@128]     : B aftertest% : ] : =16
DEF FNvst2_mult_32_d_128_wb : PROCregs21(3) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+2)                    },[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvst2_mult_32_d_128_rm : PROCregs21(3) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+2)                    },[Rn%@128],Rm% : B aftertest% : ] : =16
DEF FNvst2_mult_32_4_xxx    : PROCregs21(4) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvst2_mult_32_4_xxx_wb : PROCregs21(4) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvst2_mult_32_4_xxx_rm : PROCregs21(4) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvst2_mult_32_4_064    : PROCregs21(4) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvst2_mult_32_4_064_wb : PROCregs21(4) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvst2_mult_32_4_064_rm : PROCregs21(4) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvst2_mult_32_4_128    : PROCregs21(4) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvst2_mult_32_4_128_wb : PROCregs21(4) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvst2_mult_32_4_128_rm : PROCregs21(4) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvst2_mult_32_4_256    : PROCregs21(4) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvst2_mult_32_4_256_wb : PROCregs21(4) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvst2_mult_32_4_256_rm : PROCregs21(4) : [ OPT 2 : VST2.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256],Rm% : B aftertest% : ] : =32

REM VLD/VST multiple 3-element structures

DEF FNvld3_mult_08_3_xxx    : PROCregs21(3) : [ OPT 2 : VLD3.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]     : B aftertest% : ] : =24
DEF FNvld3_mult_08_3_xxx_wb : PROCregs21(3) : [ OPT 2 : VLD3.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]!    : B aftertest% : ] : =24
DEF FNvld3_mult_08_3_xxx_rm : PROCregs21(3) : [ OPT 2 : VLD3.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ],Rm% : B aftertest% : ] : =24
DEF FNvld3_mult_08_3_064    : PROCregs21(3) : [ OPT 2 : VLD3.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]     : B aftertest% : ] : =24
DEF FNvld3_mult_08_3_064_wb : PROCregs21(3) : [ OPT 2 : VLD3.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]!    : B aftertest% : ] : =24
DEF FNvld3_mult_08_3_064_rm : PROCregs21(3) : [ OPT 2 : VLD3.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ],Rm% : B aftertest% : ] : =24
DEF FNvld3_mult_08_d_xxx    : PROCregs21(5) : [ OPT 2 : VLD3.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%    ]     : B aftertest% : ] : =24
DEF FNvld3_mult_08_d_xxx_wb : PROCregs21(5) : [ OPT 2 : VLD3.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%    ]!    : B aftertest% : ] : =24
DEF FNvld3_mult_08_d_xxx_rm : PROCregs21(5) : [ OPT 2 : VLD3.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%    ],Rm% : B aftertest% : ] : =24
DEF FNvld3_mult_08_d_064    : PROCregs21(5) : [ OPT 2 : VLD3.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%@64 ]     : B aftertest% : ] : =24
DEF FNvld3_mult_08_d_064_wb : PROCregs21(5) : [ OPT 2 : VLD3.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%@64 ]!    : B aftertest% : ] : =24
DEF FNvld3_mult_08_d_064_rm : PROCregs21(5) : [ OPT 2 : VLD3.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%@64 ],Rm% : B aftertest% : ] : =24
DEF FNvld3_mult_16_3_xxx    : PROCregs21(3) : [ OPT 2 : VLD3.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]     : B aftertest% : ] : =24
DEF FNvld3_mult_16_3_xxx_wb : PROCregs21(3) : [ OPT 2 : VLD3.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]!    : B aftertest% : ] : =24
DEF FNvld3_mult_16_3_xxx_rm : PROCregs21(3) : [ OPT 2 : VLD3.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ],Rm% : B aftertest% : ] : =24
DEF FNvld3_mult_16_3_064    : PROCregs21(3) : [ OPT 2 : VLD3.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]     : B aftertest% : ] : =24
DEF FNvld3_mult_16_3_064_wb : PROCregs21(3) : [ OPT 2 : VLD3.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]!    : B aftertest% : ] : =24
DEF FNvld3_mult_16_3_064_rm : PROCregs21(3) : [ OPT 2 : VLD3.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ],Rm% : B aftertest% : ] : =24
DEF FNvld3_mult_16_d_xxx    : PROCregs21(5) : [ OPT 2 : VLD3.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%    ]     : B aftertest% : ] : =24
DEF FNvld3_mult_16_d_xxx_wb : PROCregs21(5) : [ OPT 2 : VLD3.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%    ]!    : B aftertest% : ] : =24
DEF FNvld3_mult_16_d_xxx_rm : PROCregs21(5) : [ OPT 2 : VLD3.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%    ],Rm% : B aftertest% : ] : =24
DEF FNvld3_mult_16_d_064    : PROCregs21(5) : [ OPT 2 : VLD3.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%@64 ]     : B aftertest% : ] : =24
DEF FNvld3_mult_16_d_064_wb : PROCregs21(5) : [ OPT 2 : VLD3.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%@64 ]!    : B aftertest% : ] : =24
DEF FNvld3_mult_16_d_064_rm : PROCregs21(5) : [ OPT 2 : VLD3.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%@64 ],Rm% : B aftertest% : ] : =24
DEF FNvld3_mult_32_3_xxx    : PROCregs21(3) : [ OPT 2 : VLD3.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]     : B aftertest% : ] : =24
DEF FNvld3_mult_32_3_xxx_wb : PROCregs21(3) : [ OPT 2 : VLD3.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]!    : B aftertest% : ] : =24
DEF FNvld3_mult_32_3_xxx_rm : PROCregs21(3) : [ OPT 2 : VLD3.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ],Rm% : B aftertest% : ] : =24
DEF FNvld3_mult_32_3_064    : PROCregs21(3) : [ OPT 2 : VLD3.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]     : B aftertest% : ] : =24
DEF FNvld3_mult_32_3_064_wb : PROCregs21(3) : [ OPT 2 : VLD3.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]!    : B aftertest% : ] : =24
DEF FNvld3_mult_32_3_064_rm : PROCregs21(3) : [ OPT 2 : VLD3.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ],Rm% : B aftertest% : ] : =24
DEF FNvld3_mult_32_d_xxx    : PROCregs21(5) : [ OPT 2 : VLD3.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%    ]     : B aftertest% : ] : =24
DEF FNvld3_mult_32_d_xxx_wb : PROCregs21(5) : [ OPT 2 : VLD3.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%    ]!    : B aftertest% : ] : =24
DEF FNvld3_mult_32_d_xxx_rm : PROCregs21(5) : [ OPT 2 : VLD3.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%    ],Rm% : B aftertest% : ] : =24
DEF FNvld3_mult_32_d_064    : PROCregs21(5) : [ OPT 2 : VLD3.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%@64 ]     : B aftertest% : ] : =24
DEF FNvld3_mult_32_d_064_wb : PROCregs21(5) : [ OPT 2 : VLD3.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%@64 ]!    : B aftertest% : ] : =24
DEF FNvld3_mult_32_d_064_rm : PROCregs21(5) : [ OPT 2 : VLD3.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%@64 ],Rm% : B aftertest% : ] : =24

DEF FNvst3_mult_08_3_xxx    : PROCregs21(3) : [ OPT 2 : VST3.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]     : B aftertest% : ] : =24
DEF FNvst3_mult_08_3_xxx_wb : PROCregs21(3) : [ OPT 2 : VST3.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]!    : B aftertest% : ] : =24
DEF FNvst3_mult_08_3_xxx_rm : PROCregs21(3) : [ OPT 2 : VST3.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ],Rm% : B aftertest% : ] : =24
DEF FNvst3_mult_08_3_064    : PROCregs21(3) : [ OPT 2 : VST3.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]     : B aftertest% : ] : =24
DEF FNvst3_mult_08_3_064_wb : PROCregs21(3) : [ OPT 2 : VST3.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]!    : B aftertest% : ] : =24
DEF FNvst3_mult_08_3_064_rm : PROCregs21(3) : [ OPT 2 : VST3.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ],Rm% : B aftertest% : ] : =24
DEF FNvst3_mult_08_d_xxx    : PROCregs21(5) : [ OPT 2 : VST3.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%    ]     : B aftertest% : ] : =24
DEF FNvst3_mult_08_d_xxx_wb : PROCregs21(5) : [ OPT 2 : VST3.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%    ]!    : B aftertest% : ] : =24
DEF FNvst3_mult_08_d_xxx_rm : PROCregs21(5) : [ OPT 2 : VST3.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%    ],Rm% : B aftertest% : ] : =24
DEF FNvst3_mult_08_d_064    : PROCregs21(5) : [ OPT 2 : VST3.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%@64 ]     : B aftertest% : ] : =24
DEF FNvst3_mult_08_d_064_wb : PROCregs21(5) : [ OPT 2 : VST3.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%@64 ]!    : B aftertest% : ] : =24
DEF FNvst3_mult_08_d_064_rm : PROCregs21(5) : [ OPT 2 : VST3.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%@64 ],Rm% : B aftertest% : ] : =24
DEF FNvst3_mult_16_3_xxx    : PROCregs21(3) : [ OPT 2 : VST3.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]     : B aftertest% : ] : =24
DEF FNvst3_mult_16_3_xxx_wb : PROCregs21(3) : [ OPT 2 : VST3.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]!    : B aftertest% : ] : =24
DEF FNvst3_mult_16_3_xxx_rm : PROCregs21(3) : [ OPT 2 : VST3.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ],Rm% : B aftertest% : ] : =24
DEF FNvst3_mult_16_3_064    : PROCregs21(3) : [ OPT 2 : VST3.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]     : B aftertest% : ] : =24
DEF FNvst3_mult_16_3_064_wb : PROCregs21(3) : [ OPT 2 : VST3.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]!    : B aftertest% : ] : =24
DEF FNvst3_mult_16_3_064_rm : PROCregs21(3) : [ OPT 2 : VST3.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ],Rm% : B aftertest% : ] : =24
DEF FNvst3_mult_16_d_xxx    : PROCregs21(5) : [ OPT 2 : VST3.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%    ]     : B aftertest% : ] : =24
DEF FNvst3_mult_16_d_xxx_wb : PROCregs21(5) : [ OPT 2 : VST3.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%    ]!    : B aftertest% : ] : =24
DEF FNvst3_mult_16_d_xxx_rm : PROCregs21(5) : [ OPT 2 : VST3.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%    ],Rm% : B aftertest% : ] : =24
DEF FNvst3_mult_16_d_064    : PROCregs21(5) : [ OPT 2 : VST3.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%@64 ]     : B aftertest% : ] : =24
DEF FNvst3_mult_16_d_064_wb : PROCregs21(5) : [ OPT 2 : VST3.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%@64 ]!    : B aftertest% : ] : =24
DEF FNvst3_mult_16_d_064_rm : PROCregs21(5) : [ OPT 2 : VST3.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%@64 ],Rm% : B aftertest% : ] : =24
DEF FNvst3_mult_32_3_xxx    : PROCregs21(3) : [ OPT 2 : VST3.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]     : B aftertest% : ] : =24
DEF FNvst3_mult_32_3_xxx_wb : PROCregs21(3) : [ OPT 2 : VST3.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ]!    : B aftertest% : ] : =24
DEF FNvst3_mult_32_3_xxx_rm : PROCregs21(3) : [ OPT 2 : VST3.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%    ],Rm% : B aftertest% : ] : =24
DEF FNvst3_mult_32_3_064    : PROCregs21(3) : [ OPT 2 : VST3.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]     : B aftertest% : ] : =24
DEF FNvst3_mult_32_3_064_wb : PROCregs21(3) : [ OPT 2 : VST3.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ]!    : B aftertest% : ] : =24
DEF FNvst3_mult_32_3_064_rm : PROCregs21(3) : [ OPT 2 : VST3.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2)          },[Rn%@64 ],Rm% : B aftertest% : ] : =24
DEF FNvst3_mult_32_d_xxx    : PROCregs21(5) : [ OPT 2 : VST3.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%    ]     : B aftertest% : ] : =24
DEF FNvst3_mult_32_d_xxx_wb : PROCregs21(5) : [ OPT 2 : VST3.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%    ]!    : B aftertest% : ] : =24
DEF FNvst3_mult_32_d_xxx_rm : PROCregs21(5) : [ OPT 2 : VST3.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%    ],Rm% : B aftertest% : ] : =24
DEF FNvst3_mult_32_d_064    : PROCregs21(5) : [ OPT 2 : VST3.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%@64 ]     : B aftertest% : ] : =24
DEF FNvst3_mult_32_d_064_wb : PROCregs21(5) : [ OPT 2 : VST3.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%@64 ]!    : B aftertest% : ] : =24
DEF FNvst3_mult_32_d_064_rm : PROCregs21(5) : [ OPT 2 : VST3.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4)          },[Rn%@64 ],Rm% : B aftertest% : ] : =24

REM VLD/VST multiple 4-element structures

DEF FNvld4_mult_08_4_xxx    : PROCregs21(4) : [ OPT 2 : VLD4.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvld4_mult_08_4_xxx_wb : PROCregs21(4) : [ OPT 2 : VLD4.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvld4_mult_08_4_xxx_rm : PROCregs21(4) : [ OPT 2 : VLD4.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvld4_mult_08_4_064    : PROCregs21(4) : [ OPT 2 : VLD4.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvld4_mult_08_4_064_wb : PROCregs21(4) : [ OPT 2 : VLD4.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvld4_mult_08_4_064_rm : PROCregs21(4) : [ OPT 2 : VLD4.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvld4_mult_08_4_128    : PROCregs21(4) : [ OPT 2 : VLD4.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvld4_mult_08_4_128_wb : PROCregs21(4) : [ OPT 2 : VLD4.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvld4_mult_08_4_128_rm : PROCregs21(4) : [ OPT 2 : VLD4.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvld4_mult_08_4_256    : PROCregs21(4) : [ OPT 2 : VLD4.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvld4_mult_08_4_256_wb : PROCregs21(4) : [ OPT 2 : VLD4.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvld4_mult_08_4_256_rm : PROCregs21(4) : [ OPT 2 : VLD4.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256],Rm% : B aftertest% : ] : =32
DEF FNvld4_mult_08_d_xxx    : PROCregs21(7) : [ OPT 2 : VLD4.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvld4_mult_08_d_xxx_wb : PROCregs21(7) : [ OPT 2 : VLD4.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvld4_mult_08_d_xxx_rm : PROCregs21(7) : [ OPT 2 : VLD4.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvld4_mult_08_d_064    : PROCregs21(7) : [ OPT 2 : VLD4.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvld4_mult_08_d_064_wb : PROCregs21(7) : [ OPT 2 : VLD4.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvld4_mult_08_d_064_rm : PROCregs21(7) : [ OPT 2 : VLD4.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvld4_mult_08_d_128    : PROCregs21(7) : [ OPT 2 : VLD4.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvld4_mult_08_d_128_wb : PROCregs21(7) : [ OPT 2 : VLD4.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvld4_mult_08_d_128_rm : PROCregs21(7) : [ OPT 2 : VLD4.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvld4_mult_08_d_256    : PROCregs21(7) : [ OPT 2 : VLD4.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvld4_mult_08_d_256_wb : PROCregs21(7) : [ OPT 2 : VLD4.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvld4_mult_08_d_256_rm : PROCregs21(7) : [ OPT 2 : VLD4.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@256],Rm% : B aftertest% : ] : =32
DEF FNvld4_mult_16_4_xxx    : PROCregs21(4) : [ OPT 2 : VLD4.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvld4_mult_16_4_xxx_wb : PROCregs21(4) : [ OPT 2 : VLD4.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvld4_mult_16_4_xxx_rm : PROCregs21(4) : [ OPT 2 : VLD4.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvld4_mult_16_4_064    : PROCregs21(4) : [ OPT 2 : VLD4.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvld4_mult_16_4_064_wb : PROCregs21(4) : [ OPT 2 : VLD4.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvld4_mult_16_4_064_rm : PROCregs21(4) : [ OPT 2 : VLD4.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvld4_mult_16_4_128    : PROCregs21(4) : [ OPT 2 : VLD4.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvld4_mult_16_4_128_wb : PROCregs21(4) : [ OPT 2 : VLD4.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvld4_mult_16_4_128_rm : PROCregs21(4) : [ OPT 2 : VLD4.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvld4_mult_16_4_256    : PROCregs21(4) : [ OPT 2 : VLD4.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvld4_mult_16_4_256_wb : PROCregs21(4) : [ OPT 2 : VLD4.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvld4_mult_16_4_256_rm : PROCregs21(4) : [ OPT 2 : VLD4.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256],Rm% : B aftertest% : ] : =32
DEF FNvld4_mult_16_d_xxx    : PROCregs21(7) : [ OPT 2 : VLD4.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvld4_mult_16_d_xxx_wb : PROCregs21(7) : [ OPT 2 : VLD4.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvld4_mult_16_d_xxx_rm : PROCregs21(7) : [ OPT 2 : VLD4.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvld4_mult_16_d_064    : PROCregs21(7) : [ OPT 2 : VLD4.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvld4_mult_16_d_064_wb : PROCregs21(7) : [ OPT 2 : VLD4.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvld4_mult_16_d_064_rm : PROCregs21(7) : [ OPT 2 : VLD4.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvld4_mult_16_d_128    : PROCregs21(7) : [ OPT 2 : VLD4.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvld4_mult_16_d_128_wb : PROCregs21(7) : [ OPT 2 : VLD4.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvld4_mult_16_d_128_rm : PROCregs21(7) : [ OPT 2 : VLD4.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvld4_mult_16_d_256    : PROCregs21(7) : [ OPT 2 : VLD4.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvld4_mult_16_d_256_wb : PROCregs21(7) : [ OPT 2 : VLD4.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvld4_mult_16_d_256_rm : PROCregs21(7) : [ OPT 2 : VLD4.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@256],Rm% : B aftertest% : ] : =32
DEF FNvld4_mult_32_4_xxx    : PROCregs21(4) : [ OPT 2 : VLD4.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvld4_mult_32_4_xxx_wb : PROCregs21(4) : [ OPT 2 : VLD4.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvld4_mult_32_4_xxx_rm : PROCregs21(4) : [ OPT 2 : VLD4.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvld4_mult_32_4_064    : PROCregs21(4) : [ OPT 2 : VLD4.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvld4_mult_32_4_064_wb : PROCregs21(4) : [ OPT 2 : VLD4.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvld4_mult_32_4_064_rm : PROCregs21(4) : [ OPT 2 : VLD4.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvld4_mult_32_4_128    : PROCregs21(4) : [ OPT 2 : VLD4.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvld4_mult_32_4_128_wb : PROCregs21(4) : [ OPT 2 : VLD4.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvld4_mult_32_4_128_rm : PROCregs21(4) : [ OPT 2 : VLD4.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvld4_mult_32_4_256    : PROCregs21(4) : [ OPT 2 : VLD4.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvld4_mult_32_4_256_wb : PROCregs21(4) : [ OPT 2 : VLD4.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvld4_mult_32_4_256_rm : PROCregs21(4) : [ OPT 2 : VLD4.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256],Rm% : B aftertest% : ] : =32
DEF FNvld4_mult_32_d_xxx    : PROCregs21(7) : [ OPT 2 : VLD4.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvld4_mult_32_d_xxx_wb : PROCregs21(7) : [ OPT 2 : VLD4.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvld4_mult_32_d_xxx_rm : PROCregs21(7) : [ OPT 2 : VLD4.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvld4_mult_32_d_064    : PROCregs21(7) : [ OPT 2 : VLD4.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvld4_mult_32_d_064_wb : PROCregs21(7) : [ OPT 2 : VLD4.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvld4_mult_32_d_064_rm : PROCregs21(7) : [ OPT 2 : VLD4.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvld4_mult_32_d_128    : PROCregs21(7) : [ OPT 2 : VLD4.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvld4_mult_32_d_128_wb : PROCregs21(7) : [ OPT 2 : VLD4.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvld4_mult_32_d_128_rm : PROCregs21(7) : [ OPT 2 : VLD4.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvld4_mult_32_d_256    : PROCregs21(7) : [ OPT 2 : VLD4.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvld4_mult_32_d_256_wb : PROCregs21(7) : [ OPT 2 : VLD4.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvld4_mult_32_d_256_rm : PROCregs21(7) : [ OPT 2 : VLD4.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@256],Rm% : B aftertest% : ] : =32

DEF FNvst4_mult_08_4_xxx    : PROCregs21(4) : [ OPT 2 : VST4.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvst4_mult_08_4_xxx_wb : PROCregs21(4) : [ OPT 2 : VST4.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvst4_mult_08_4_xxx_rm : PROCregs21(4) : [ OPT 2 : VST4.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvst4_mult_08_4_064    : PROCregs21(4) : [ OPT 2 : VST4.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvst4_mult_08_4_064_wb : PROCregs21(4) : [ OPT 2 : VST4.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvst4_mult_08_4_064_rm : PROCregs21(4) : [ OPT 2 : VST4.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvst4_mult_08_4_128    : PROCregs21(4) : [ OPT 2 : VST4.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvst4_mult_08_4_128_wb : PROCregs21(4) : [ OPT 2 : VST4.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvst4_mult_08_4_128_rm : PROCregs21(4) : [ OPT 2 : VST4.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvst4_mult_08_4_256    : PROCregs21(4) : [ OPT 2 : VST4.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvst4_mult_08_4_256_wb : PROCregs21(4) : [ OPT 2 : VST4.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvst4_mult_08_4_256_rm : PROCregs21(4) : [ OPT 2 : VST4.8  {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256],Rm% : B aftertest% : ] : =32
DEF FNvst4_mult_08_d_xxx    : PROCregs21(7) : [ OPT 2 : VST4.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvst4_mult_08_d_xxx_wb : PROCregs21(7) : [ OPT 2 : VST4.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvst4_mult_08_d_xxx_rm : PROCregs21(7) : [ OPT 2 : VST4.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvst4_mult_08_d_064    : PROCregs21(7) : [ OPT 2 : VST4.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvst4_mult_08_d_064_wb : PROCregs21(7) : [ OPT 2 : VST4.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvst4_mult_08_d_064_rm : PROCregs21(7) : [ OPT 2 : VST4.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvst4_mult_08_d_128    : PROCregs21(7) : [ OPT 2 : VST4.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvst4_mult_08_d_128_wb : PROCregs21(7) : [ OPT 2 : VST4.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvst4_mult_08_d_128_rm : PROCregs21(7) : [ OPT 2 : VST4.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvst4_mult_08_d_256    : PROCregs21(7) : [ OPT 2 : VST4.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvst4_mult_08_d_256_wb : PROCregs21(7) : [ OPT 2 : VST4.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvst4_mult_08_d_256_rm : PROCregs21(7) : [ OPT 2 : VST4.8  {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@256],Rm% : B aftertest% : ] : =32
DEF FNvst4_mult_16_4_xxx    : PROCregs21(4) : [ OPT 2 : VST4.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvst4_mult_16_4_xxx_wb : PROCregs21(4) : [ OPT 2 : VST4.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvst4_mult_16_4_xxx_rm : PROCregs21(4) : [ OPT 2 : VST4.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvst4_mult_16_4_064    : PROCregs21(4) : [ OPT 2 : VST4.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvst4_mult_16_4_064_wb : PROCregs21(4) : [ OPT 2 : VST4.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvst4_mult_16_4_064_rm : PROCregs21(4) : [ OPT 2 : VST4.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvst4_mult_16_4_128    : PROCregs21(4) : [ OPT 2 : VST4.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvst4_mult_16_4_128_wb : PROCregs21(4) : [ OPT 2 : VST4.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvst4_mult_16_4_128_rm : PROCregs21(4) : [ OPT 2 : VST4.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvst4_mult_16_4_256    : PROCregs21(4) : [ OPT 2 : VST4.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvst4_mult_16_4_256_wb : PROCregs21(4) : [ OPT 2 : VST4.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvst4_mult_16_4_256_rm : PROCregs21(4) : [ OPT 2 : VST4.16 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256],Rm% : B aftertest% : ] : =32
DEF FNvst4_mult_16_d_xxx    : PROCregs21(7) : [ OPT 2 : VST4.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvst4_mult_16_d_xxx_wb : PROCregs21(7) : [ OPT 2 : VST4.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvst4_mult_16_d_xxx_rm : PROCregs21(7) : [ OPT 2 : VST4.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvst4_mult_16_d_064    : PROCregs21(7) : [ OPT 2 : VST4.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvst4_mult_16_d_064_wb : PROCregs21(7) : [ OPT 2 : VST4.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvst4_mult_16_d_064_rm : PROCregs21(7) : [ OPT 2 : VST4.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvst4_mult_16_d_128    : PROCregs21(7) : [ OPT 2 : VST4.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvst4_mult_16_d_128_wb : PROCregs21(7) : [ OPT 2 : VST4.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvst4_mult_16_d_128_rm : PROCregs21(7) : [ OPT 2 : VST4.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvst4_mult_16_d_256    : PROCregs21(7) : [ OPT 2 : VST4.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvst4_mult_16_d_256_wb : PROCregs21(7) : [ OPT 2 : VST4.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvst4_mult_16_d_256_rm : PROCregs21(7) : [ OPT 2 : VST4.16 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@256],Rm% : B aftertest% : ] : =32
DEF FNvst4_mult_32_4_xxx    : PROCregs21(4) : [ OPT 2 : VST4.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvst4_mult_32_4_xxx_wb : PROCregs21(4) : [ OPT 2 : VST4.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvst4_mult_32_4_xxx_rm : PROCregs21(4) : [ OPT 2 : VST4.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvst4_mult_32_4_064    : PROCregs21(4) : [ OPT 2 : VST4.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvst4_mult_32_4_064_wb : PROCregs21(4) : [ OPT 2 : VST4.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvst4_mult_32_4_064_rm : PROCregs21(4) : [ OPT 2 : VST4.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvst4_mult_32_4_128    : PROCregs21(4) : [ OPT 2 : VST4.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvst4_mult_32_4_128_wb : PROCregs21(4) : [ OPT 2 : VST4.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvst4_mult_32_4_128_rm : PROCregs21(4) : [ OPT 2 : VST4.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvst4_mult_32_4_256    : PROCregs21(4) : [ OPT 2 : VST4.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvst4_mult_32_4_256_wb : PROCregs21(4) : [ OPT 2 : VST4.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvst4_mult_32_4_256_rm : PROCregs21(4) : [ OPT 2 : VST4.32 {D#Vd%,D#(Vd%+1),D#(Vd%+2),D#(Vd%+3)},[Rn%@256],Rm% : B aftertest% : ] : =32
DEF FNvst4_mult_32_d_xxx    : PROCregs21(7) : [ OPT 2 : VST4.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%    ]     : B aftertest% : ] : =32
DEF FNvst4_mult_32_d_xxx_wb : PROCregs21(7) : [ OPT 2 : VST4.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%    ]!    : B aftertest% : ] : =32
DEF FNvst4_mult_32_d_xxx_rm : PROCregs21(7) : [ OPT 2 : VST4.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%    ],Rm% : B aftertest% : ] : =32
DEF FNvst4_mult_32_d_064    : PROCregs21(7) : [ OPT 2 : VST4.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@64 ]     : B aftertest% : ] : =32
DEF FNvst4_mult_32_d_064_wb : PROCregs21(7) : [ OPT 2 : VST4.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@64 ]!    : B aftertest% : ] : =32
DEF FNvst4_mult_32_d_064_rm : PROCregs21(7) : [ OPT 2 : VST4.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@64 ],Rm% : B aftertest% : ] : =32
DEF FNvst4_mult_32_d_128    : PROCregs21(7) : [ OPT 2 : VST4.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@128]     : B aftertest% : ] : =32
DEF FNvst4_mult_32_d_128_wb : PROCregs21(7) : [ OPT 2 : VST4.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@128]!    : B aftertest% : ] : =32
DEF FNvst4_mult_32_d_128_rm : PROCregs21(7) : [ OPT 2 : VST4.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@128],Rm% : B aftertest% : ] : =32
DEF FNvst4_mult_32_d_256    : PROCregs21(7) : [ OPT 2 : VST4.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@256]     : B aftertest% : ] : =32
DEF FNvst4_mult_32_d_256_wb : PROCregs21(7) : [ OPT 2 : VST4.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@256]!    : B aftertest% : ] : =32
DEF FNvst4_mult_32_d_256_rm : PROCregs21(7) : [ OPT 2 : VST4.32 {D#Vd%,D#(Vd%+2),D#(Vd%+4),D#(Vd%+6)},[Rn%@256],Rm% : B aftertest% : ] : =32

REM VLD/VST single element to one lane

DEF FNvld1_lane_08_1_xxx    : PROCregs22(1,7) : [ OPT 2 : VLD1.8  {D#Vd%[imm%]                        },[Rn%    ]     : B aftertest% : ] : =1
DEF FNvld1_lane_08_1_xxx_wb : PROCregs22(1,7) : [ OPT 2 : VLD1.8  {D#Vd%[imm%]                        },[Rn%    ]!    : B aftertest% : ] : =1
DEF FNvld1_lane_08_1_xxx_rm : PROCregs22(1,7) : [ OPT 2 : VLD1.8  {D#Vd%[imm%]                        },[Rn%    ],Rm% : B aftertest% : ] : =1
DEF FNvld1_lane_16_1_xxx    : PROCregs22(1,3) : [ OPT 2 : VLD1.16 {D#Vd%[imm%]                        },[Rn%    ]     : B aftertest% : ] : =2
DEF FNvld1_lane_16_1_xxx_wb : PROCregs22(1,3) : [ OPT 2 : VLD1.16 {D#Vd%[imm%]                        },[Rn%    ]!    : B aftertest% : ] : =2
DEF FNvld1_lane_16_1_xxx_rm : PROCregs22(1,3) : [ OPT 2 : VLD1.16 {D#Vd%[imm%]                        },[Rn%    ],Rm% : B aftertest% : ] : =2
DEF FNvld1_lane_16_1_016    : PROCregs22(1,3) : [ OPT 2 : VLD1.16 {D#Vd%[imm%]                        },[Rn%@16 ]     : B aftertest% : ] : =2
DEF FNvld1_lane_16_1_016_wb : PROCregs22(1,3) : [ OPT 2 : VLD1.16 {D#Vd%[imm%]                        },[Rn%@16 ]!    : B aftertest% : ] : =2
DEF FNvld1_lane_16_1_016_rm : PROCregs22(1,3) : [ OPT 2 : VLD1.16 {D#Vd%[imm%]                        },[Rn%@16 ],Rm% : B aftertest% : ] : =2
DEF FNvld1_lane_32_1_xxx    : PROCregs22(1,1) : [ OPT 2 : VLD1.32 {D#Vd%[imm%]                        },[Rn%    ]     : B aftertest% : ] : =4
DEF FNvld1_lane_32_1_xxx_wb : PROCregs22(1,1) : [ OPT 2 : VLD1.32 {D#Vd%[imm%]                        },[Rn%    ]!    : B aftertest% : ] : =4
DEF FNvld1_lane_32_1_xxx_rm : PROCregs22(1,1) : [ OPT 2 : VLD1.32 {D#Vd%[imm%]                        },[Rn%    ],Rm% : B aftertest% : ] : =4
DEF FNvld1_lane_32_1_032    : PROCregs22(1,1) : [ OPT 2 : VLD1.32 {D#Vd%[imm%]                        },[Rn%@32 ]     : B aftertest% : ] : =4
DEF FNvld1_lane_32_1_032_wb : PROCregs22(1,1) : [ OPT 2 : VLD1.32 {D#Vd%[imm%]                        },[Rn%@32 ]!    : B aftertest% : ] : =4
DEF FNvld1_lane_32_1_032_rm : PROCregs22(1,1) : [ OPT 2 : VLD1.32 {D#Vd%[imm%]                        },[Rn%@32 ],Rm% : B aftertest% : ] : =4

DEF FNvst1_lane_08_1_xxx    : PROCregs22(1,7) : [ OPT 2 : VST1.8  {D#Vd%[imm%]                        },[Rn%    ]     : B aftertest% : ] : =1
DEF FNvst1_lane_08_1_xxx_wb : PROCregs22(1,7) : [ OPT 2 : VST1.8  {D#Vd%[imm%]                        },[Rn%    ]!    : B aftertest% : ] : =1
DEF FNvst1_lane_08_1_xxx_rm : PROCregs22(1,7) : [ OPT 2 : VST1.8  {D#Vd%[imm%]                        },[Rn%    ],Rm% : B aftertest% : ] : =1
DEF FNvst1_lane_16_1_xxx    : PROCregs22(1,3) : [ OPT 2 : VST1.16 {D#Vd%[imm%]                        },[Rn%    ]     : B aftertest% : ] : =2
DEF FNvst1_lane_16_1_xxx_wb : PROCregs22(1,3) : [ OPT 2 : VST1.16 {D#Vd%[imm%]                        },[Rn%    ]!    : B aftertest% : ] : =2
DEF FNvst1_lane_16_1_xxx_rm : PROCregs22(1,3) : [ OPT 2 : VST1.16 {D#Vd%[imm%]                        },[Rn%    ],Rm% : B aftertest% : ] : =2
DEF FNvst1_lane_16_1_016    : PROCregs22(1,3) : [ OPT 2 : VST1.16 {D#Vd%[imm%]                        },[Rn%@16 ]     : B aftertest% : ] : =2
DEF FNvst1_lane_16_1_016_wb : PROCregs22(1,3) : [ OPT 2 : VST1.16 {D#Vd%[imm%]                        },[Rn%@16 ]!    : B aftertest% : ] : =2
DEF FNvst1_lane_16_1_016_rm : PROCregs22(1,3) : [ OPT 2 : VST1.16 {D#Vd%[imm%]                        },[Rn%@16 ],Rm% : B aftertest% : ] : =2
DEF FNvst1_lane_32_1_xxx    : PROCregs22(1,1) : [ OPT 2 : VST1.32 {D#Vd%[imm%]                        },[Rn%    ]     : B aftertest% : ] : =4
DEF FNvst1_lane_32_1_xxx_wb : PROCregs22(1,1) : [ OPT 2 : VST1.32 {D#Vd%[imm%]                        },[Rn%    ]!    : B aftertest% : ] : =4
DEF FNvst1_lane_32_1_xxx_rm : PROCregs22(1,1) : [ OPT 2 : VST1.32 {D#Vd%[imm%]                        },[Rn%    ],Rm% : B aftertest% : ] : =4
DEF FNvst1_lane_32_1_032    : PROCregs22(1,1) : [ OPT 2 : VST1.32 {D#Vd%[imm%]                        },[Rn%@32 ]     : B aftertest% : ] : =4
DEF FNvst1_lane_32_1_032_wb : PROCregs22(1,1) : [ OPT 2 : VST1.32 {D#Vd%[imm%]                        },[Rn%@32 ]!    : B aftertest% : ] : =4
DEF FNvst1_lane_32_1_032_rm : PROCregs22(1,1) : [ OPT 2 : VST1.32 {D#Vd%[imm%]                        },[Rn%@32 ],Rm% : B aftertest% : ] : =4

REM VLD/VST single 2-element structure to one lane

DEF FNvld2_lane_08_2_xxx    : PROCregs22(2,7) : [ OPT 2 : VLD2.8  {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%    ]     : B aftertest% : ] : =2
DEF FNvld2_lane_08_2_xxx_wb : PROCregs22(2,7) : [ OPT 2 : VLD2.8  {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%    ]!    : B aftertest% : ] : =2
DEF FNvld2_lane_08_2_xxx_rm : PROCregs22(2,7) : [ OPT 2 : VLD2.8  {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%    ],Rm% : B aftertest% : ] : =2
DEF FNvld2_lane_08_2_016    : PROCregs22(2,7) : [ OPT 2 : VLD2.8  {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%@16 ]     : B aftertest% : ] : =2
DEF FNvld2_lane_08_2_016_wb : PROCregs22(2,7) : [ OPT 2 : VLD2.8  {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%@16 ]!    : B aftertest% : ] : =2
DEF FNvld2_lane_08_2_016_rm : PROCregs22(2,7) : [ OPT 2 : VLD2.8  {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%@16 ],Rm% : B aftertest% : ] : =2
DEF FNvld2_lane_16_2_xxx    : PROCregs22(2,3) : [ OPT 2 : VLD2.16 {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%    ]     : B aftertest% : ] : =4
DEF FNvld2_lane_16_2_xxx_wb : PROCregs22(2,3) : [ OPT 2 : VLD2.16 {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%    ]!    : B aftertest% : ] : =4
DEF FNvld2_lane_16_2_xxx_rm : PROCregs22(2,3) : [ OPT 2 : VLD2.16 {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%    ],Rm% : B aftertest% : ] : =4
DEF FNvld2_lane_16_2_032    : PROCregs22(2,3) : [ OPT 2 : VLD2.16 {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%@32 ]     : B aftertest% : ] : =4
DEF FNvld2_lane_16_2_032_wb : PROCregs22(2,3) : [ OPT 2 : VLD2.16 {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%@32 ]!    : B aftertest% : ] : =4
DEF FNvld2_lane_16_2_032_rm : PROCregs22(2,3) : [ OPT 2 : VLD2.16 {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%@32 ],Rm% : B aftertest% : ] : =4
DEF FNvld2_lane_32_2_xxx    : PROCregs22(2,1) : [ OPT 2 : VLD2.32 {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%    ]     : B aftertest% : ] : =8
DEF FNvld2_lane_32_2_xxx_wb : PROCregs22(2,1) : [ OPT 2 : VLD2.32 {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%    ]!    : B aftertest% : ] : =8
DEF FNvld2_lane_32_2_xxx_rm : PROCregs22(2,1) : [ OPT 2 : VLD2.32 {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%    ],Rm% : B aftertest% : ] : =8
DEF FNvld2_lane_32_2_064    : PROCregs22(2,1) : [ OPT 2 : VLD2.32 {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%@64 ]     : B aftertest% : ] : =8
DEF FNvld2_lane_32_2_064_wb : PROCregs22(2,1) : [ OPT 2 : VLD2.32 {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%@64 ]!    : B aftertest% : ] : =8
DEF FNvld2_lane_32_2_064_rm : PROCregs22(2,1) : [ OPT 2 : VLD2.32 {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%@64 ],Rm% : B aftertest% : ] : =8
DEF FNvld2_lane_16_d_xxx    : PROCregs22(3,3) : [ OPT 2 : VLD2.16 {D#Vd%[imm%],D#(Vd%+2)[imm%]        },[Rn%    ]     : B aftertest% : ] : =4
DEF FNvld2_lane_16_d_xxx_wb : PROCregs22(3,3) : [ OPT 2 : VLD2.16 {D#Vd%[imm%],D#(Vd%+2)[imm%]        },[Rn%    ]!    : B aftertest% : ] : =4
DEF FNvld2_lane_16_d_xxx_rm : PROCregs22(3,3) : [ OPT 2 : VLD2.16 {D#Vd%[imm%],D#(Vd%+2)[imm%]        },[Rn%    ],Rm% : B aftertest% : ] : =4
DEF FNvld2_lane_16_d_032    : PROCregs22(3,3) : [ OPT 2 : VLD2.16 {D#Vd%[imm%],D#(Vd%+2)[imm%]        },[Rn%@32 ]     : B aftertest% : ] : =4
DEF FNvld2_lane_16_d_032_wb : PROCregs22(3,3) : [ OPT 2 : VLD2.16 {D#Vd%[imm%],D#(Vd%+2)[imm%]        },[Rn%@32 ]!    : B aftertest% : ] : =4
DEF FNvld2_lane_16_d_032_rm : PROCregs22(3,3) : [ OPT 2 : VLD2.16 {D#Vd%[imm%],D#(Vd%+2)[imm%]        },[Rn%@32 ],Rm% : B aftertest% : ] : =4
DEF FNvld2_lane_32_d_xxx    : PROCregs22(3,1) : [ OPT 2 : VLD2.32 {D#Vd%[imm%],D#(Vd%+2)[imm%]        },[Rn%    ]     : B aftertest% : ] : =8
DEF FNvld2_lane_32_d_xxx_wb : PROCregs22(3,1) : [ OPT 2 : VLD2.32 {D#Vd%[imm%],D#(Vd%+2)[imm%]        },[Rn%    ]!    : B aftertest% : ] : =8
DEF FNvld2_lane_32_d_xxx_rm : PROCregs22(3,1) : [ OPT 2 : VLD2.32 {D#Vd%[imm%],D#(Vd%+2)[imm%]        },[Rn%    ],Rm% : B aftertest% : ] : =8
DEF FNvld2_lane_32_d_064    : PROCregs22(3,1) : [ OPT 2 : VLD2.32 {D#Vd%[imm%],D#(Vd%+2)[imm%]        },[Rn%@64 ]     : B aftertest% : ] : =8
DEF FNvld2_lane_32_d_064_wb : PROCregs22(3,1) : [ OPT 2 : VLD2.32 {D#Vd%[imm%],D#(Vd%+2)[imm%]        },[Rn%@64 ]!    : B aftertest% : ] : =8
DEF FNvld2_lane_32_d_064_rm : PROCregs22(3,1) : [ OPT 2 : VLD2.32 {D#Vd%[imm%],D#(Vd%+2)[imm%]        },[Rn%@64 ],Rm% : B aftertest% : ] : =8

DEF FNvst2_lane_08_2_xxx    : PROCregs22(2,7) : [ OPT 2 : VST2.8  {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%    ]     : B aftertest% : ] : =2
DEF FNvst2_lane_08_2_xxx_wb : PROCregs22(2,7) : [ OPT 2 : VST2.8  {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%    ]!    : B aftertest% : ] : =2
DEF FNvst2_lane_08_2_xxx_rm : PROCregs22(2,7) : [ OPT 2 : VST2.8  {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%    ],Rm% : B aftertest% : ] : =2
DEF FNvst2_lane_08_2_016    : PROCregs22(2,7) : [ OPT 2 : VST2.8  {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%@16 ]     : B aftertest% : ] : =2
DEF FNvst2_lane_08_2_016_wb : PROCregs22(2,7) : [ OPT 2 : VST2.8  {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%@16 ]!    : B aftertest% : ] : =2
DEF FNvst2_lane_08_2_016_rm : PROCregs22(2,7) : [ OPT 2 : VST2.8  {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%@16 ],Rm% : B aftertest% : ] : =2
DEF FNvst2_lane_16_2_xxx    : PROCregs22(2,3) : [ OPT 2 : VST2.16 {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%    ]     : B aftertest% : ] : =4
DEF FNvst2_lane_16_2_xxx_wb : PROCregs22(2,3) : [ OPT 2 : VST2.16 {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%    ]!    : B aftertest% : ] : =4
DEF FNvst2_lane_16_2_xxx_rm : PROCregs22(2,3) : [ OPT 2 : VST2.16 {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%    ],Rm% : B aftertest% : ] : =4
DEF FNvst2_lane_16_2_032    : PROCregs22(2,3) : [ OPT 2 : VST2.16 {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%@32 ]     : B aftertest% : ] : =4
DEF FNvst2_lane_16_2_032_wb : PROCregs22(2,3) : [ OPT 2 : VST2.16 {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%@32 ]!    : B aftertest% : ] : =4
DEF FNvst2_lane_16_2_032_rm : PROCregs22(2,3) : [ OPT 2 : VST2.16 {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%@32 ],Rm% : B aftertest% : ] : =4
DEF FNvst2_lane_32_2_xxx    : PROCregs22(2,1) : [ OPT 2 : VST2.32 {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%    ]     : B aftertest% : ] : =8
DEF FNvst2_lane_32_2_xxx_wb : PROCregs22(2,1) : [ OPT 2 : VST2.32 {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%    ]!    : B aftertest% : ] : =8
DEF FNvst2_lane_32_2_xxx_rm : PROCregs22(2,1) : [ OPT 2 : VST2.32 {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%    ],Rm% : B aftertest% : ] : =8
DEF FNvst2_lane_32_2_064    : PROCregs22(2,1) : [ OPT 2 : VST2.32 {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%@64 ]     : B aftertest% : ] : =8
DEF FNvst2_lane_32_2_064_wb : PROCregs22(2,1) : [ OPT 2 : VST2.32 {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%@64 ]!    : B aftertest% : ] : =8
DEF FNvst2_lane_32_2_064_rm : PROCregs22(2,1) : [ OPT 2 : VST2.32 {D#Vd%[imm%],D#(Vd%+1)[imm%]        },[Rn%@64 ],Rm% : B aftertest% : ] : =8
DEF FNvst2_lane_16_d_xxx    : PROCregs22(3,3) : [ OPT 2 : VST2.16 {D#Vd%[imm%],D#(Vd%+2)[imm%]        },[Rn%    ]     : B aftertest% : ] : =4
DEF FNvst2_lane_16_d_xxx_wb : PROCregs22(3,3) : [ OPT 2 : VST2.16 {D#Vd%[imm%],D#(Vd%+2)[imm%]        },[Rn%    ]!    : B aftertest% : ] : =4
DEF FNvst2_lane_16_d_xxx_rm : PROCregs22(3,3) : [ OPT 2 : VST2.16 {D#Vd%[imm%],D#(Vd%+2)[imm%]        },[Rn%    ],Rm% : B aftertest% : ] : =4
DEF FNvst2_lane_16_d_032    : PROCregs22(3,3) : [ OPT 2 : VST2.16 {D#Vd%[imm%],D#(Vd%+2)[imm%]        },[Rn%@32 ]     : B aftertest% : ] : =4
DEF FNvst2_lane_16_d_032_wb : PROCregs22(3,3) : [ OPT 2 : VST2.16 {D#Vd%[imm%],D#(Vd%+2)[imm%]        },[Rn%@32 ]!    : B aftertest% : ] : =4
DEF FNvst2_lane_16_d_032_rm : PROCregs22(3,3) : [ OPT 2 : VST2.16 {D#Vd%[imm%],D#(Vd%+2)[imm%]        },[Rn%@32 ],Rm% : B aftertest% : ] : =4
DEF FNvst2_lane_32_d_xxx    : PROCregs22(3,1) : [ OPT 2 : VST2.32 {D#Vd%[imm%],D#(Vd%+2)[imm%]        },[Rn%    ]     : B aftertest% : ] : =8
DEF FNvst2_lane_32_d_xxx_wb : PROCregs22(3,1) : [ OPT 2 : VST2.32 {D#Vd%[imm%],D#(Vd%+2)[imm%]        },[Rn%    ]!    : B aftertest% : ] : =8
DEF FNvst2_lane_32_d_xxx_rm : PROCregs22(3,1) : [ OPT 2 : VST2.32 {D#Vd%[imm%],D#(Vd%+2)[imm%]        },[Rn%    ],Rm% : B aftertest% : ] : =8
DEF FNvst2_lane_32_d_064    : PROCregs22(3,1) : [ OPT 2 : VST2.32 {D#Vd%[imm%],D#(Vd%+2)[imm%]        },[Rn%@64 ]     : B aftertest% : ] : =8
DEF FNvst2_lane_32_d_064_wb : PROCregs22(3,1) : [ OPT 2 : VST2.32 {D#Vd%[imm%],D#(Vd%+2)[imm%]        },[Rn%@64 ]!    : B aftertest% : ] : =8
DEF FNvst2_lane_32_d_064_rm : PROCregs22(3,1) : [ OPT 2 : VST2.32 {D#Vd%[imm%],D#(Vd%+2)[imm%]        },[Rn%@64 ],Rm% : B aftertest% : ] : =8

REM VLD/VST single 3-element structure to one lane

DEF FNvld3_lane_08_3_xxx    : PROCregs22(3,7) : [ OPT 2 : VLD3.8  {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%]},[Rn%    ]     : B aftertest% : ] : =3
DEF FNvld3_lane_08_3_xxx_wb : PROCregs22(3,7) : [ OPT 2 : VLD3.8  {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%]},[Rn%    ]!    : B aftertest% : ] : =3
DEF FNvld3_lane_08_3_xxx_rm : PROCregs22(3,7) : [ OPT 2 : VLD3.8  {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%]},[Rn%    ],Rm% : B aftertest% : ] : =3
DEF FNvld3_lane_16_3_xxx    : PROCregs22(3,3) : [ OPT 2 : VLD3.16 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%]},[Rn%    ]     : B aftertest% : ] : =6
DEF FNvld3_lane_16_3_xxx_wb : PROCregs22(3,3) : [ OPT 2 : VLD3.16 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%]},[Rn%    ]!    : B aftertest% : ] : =6
DEF FNvld3_lane_16_3_xxx_rm : PROCregs22(3,3) : [ OPT 2 : VLD3.16 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%]},[Rn%    ],Rm% : B aftertest% : ] : =6
DEF FNvld3_lane_16_d_xxx    : PROCregs22(5,3) : [ OPT 2 : VLD3.16 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%]},[Rn%    ]     : B aftertest% : ] : =6
DEF FNvld3_lane_16_d_xxx_wb : PROCregs22(5,3) : [ OPT 2 : VLD3.16 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%]},[Rn%    ]!    : B aftertest% : ] : =6
DEF FNvld3_lane_16_d_xxx_rm : PROCregs22(5,3) : [ OPT 2 : VLD3.16 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%]},[Rn%    ],Rm% : B aftertest% : ] : =6
DEF FNvld3_lane_32_3_xxx    : PROCregs22(3,1) : [ OPT 2 : VLD3.32 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%]},[Rn%    ]     : B aftertest% : ] : =12
DEF FNvld3_lane_32_3_xxx_wb : PROCregs22(3,1) : [ OPT 2 : VLD3.32 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%]},[Rn%    ]!    : B aftertest% : ] : =12
DEF FNvld3_lane_32_3_xxx_rm : PROCregs22(3,1) : [ OPT 2 : VLD3.32 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%]},[Rn%    ],Rm% : B aftertest% : ] : =12
DEF FNvld3_lane_32_d_xxx    : PROCregs22(5,1) : [ OPT 2 : VLD3.32 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%]},[Rn%    ]     : B aftertest% : ] : =12
DEF FNvld3_lane_32_d_xxx_wb : PROCregs22(5,1) : [ OPT 2 : VLD3.32 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%]},[Rn%    ]!    : B aftertest% : ] : =12
DEF FNvld3_lane_32_d_xxx_rm : PROCregs22(5,1) : [ OPT 2 : VLD3.32 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%]},[Rn%    ],Rm% : B aftertest% : ] : =12

DEF FNvst3_lane_08_3_xxx    : PROCregs22(3,7) : [ OPT 2 : VST3.8  {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%]},[Rn%    ]     : B aftertest% : ] : =3
DEF FNvst3_lane_08_3_xxx_wb : PROCregs22(3,7) : [ OPT 2 : VST3.8  {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%]},[Rn%    ]!    : B aftertest% : ] : =3
DEF FNvst3_lane_08_3_xxx_rm : PROCregs22(3,7) : [ OPT 2 : VST3.8  {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%]},[Rn%    ],Rm% : B aftertest% : ] : =3
DEF FNvst3_lane_16_3_xxx    : PROCregs22(3,3) : [ OPT 2 : VST3.16 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%]},[Rn%    ]     : B aftertest% : ] : =6
DEF FNvst3_lane_16_3_xxx_wb : PROCregs22(3,3) : [ OPT 2 : VST3.16 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%]},[Rn%    ]!    : B aftertest% : ] : =6
DEF FNvst3_lane_16_3_xxx_rm : PROCregs22(3,3) : [ OPT 2 : VST3.16 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%]},[Rn%    ],Rm% : B aftertest% : ] : =6
DEF FNvst3_lane_16_d_xxx    : PROCregs22(5,3) : [ OPT 2 : VST3.16 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%]},[Rn%    ]     : B aftertest% : ] : =6
DEF FNvst3_lane_16_d_xxx_wb : PROCregs22(5,3) : [ OPT 2 : VST3.16 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%]},[Rn%    ]!    : B aftertest% : ] : =6
DEF FNvst3_lane_16_d_xxx_rm : PROCregs22(5,3) : [ OPT 2 : VST3.16 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%]},[Rn%    ],Rm% : B aftertest% : ] : =6
DEF FNvst3_lane_32_3_xxx    : PROCregs22(3,1) : [ OPT 2 : VST3.32 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%]},[Rn%    ]     : B aftertest% : ] : =12
DEF FNvst3_lane_32_3_xxx_wb : PROCregs22(3,1) : [ OPT 2 : VST3.32 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%]},[Rn%    ]!    : B aftertest% : ] : =12
DEF FNvst3_lane_32_3_xxx_rm : PROCregs22(3,1) : [ OPT 2 : VST3.32 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%]},[Rn%    ],Rm% : B aftertest% : ] : =12
DEF FNvst3_lane_32_d_xxx    : PROCregs22(5,1) : [ OPT 2 : VST3.32 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%]},[Rn%    ]     : B aftertest% : ] : =12
DEF FNvst3_lane_32_d_xxx_wb : PROCregs22(5,1) : [ OPT 2 : VST3.32 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%]},[Rn%    ]!    : B aftertest% : ] : =12
DEF FNvst3_lane_32_d_xxx_rm : PROCregs22(5,1) : [ OPT 2 : VST3.32 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%]},[Rn%    ],Rm% : B aftertest% : ] : =12

REM VLD/VST single 4-element structure to one lane

DEF FNvld4_lane_08_4_xxx    : PROCregs22(4,7) : [ OPT 2 : VLD4.8  {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%    ]     : B aftertest% : ] : =4
DEF FNvld4_lane_08_4_xxx_wb : PROCregs22(4,7) : [ OPT 2 : VLD4.8  {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%    ]!    : B aftertest% : ] : =4
DEF FNvld4_lane_08_4_xxx_rm : PROCregs22(4,7) : [ OPT 2 : VLD4.8  {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%    ],Rm% : B aftertest% : ] : =4
DEF FNvld4_lane_08_4_032    : PROCregs22(4,7) : [ OPT 2 : VLD4.8  {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%@32 ]     : B aftertest% : ] : =4
DEF FNvld4_lane_08_4_032_wb : PROCregs22(4,7) : [ OPT 2 : VLD4.8  {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%@32 ]!    : B aftertest% : ] : =4
DEF FNvld4_lane_08_4_032_rm : PROCregs22(4,7) : [ OPT 2 : VLD4.8  {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%@32 ],Rm% : B aftertest% : ] : =4
DEF FNvld4_lane_16_4_xxx    : PROCregs22(4,3) : [ OPT 2 : VLD4.16 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%    ]     : B aftertest% : ] : =8
DEF FNvld4_lane_16_4_xxx_wb : PROCregs22(4,3) : [ OPT 2 : VLD4.16 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%    ]!    : B aftertest% : ] : =8
DEF FNvld4_lane_16_4_xxx_rm : PROCregs22(4,3) : [ OPT 2 : VLD4.16 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%    ],Rm% : B aftertest% : ] : =8
DEF FNvld4_lane_16_4_064    : PROCregs22(4,3) : [ OPT 2 : VLD4.16 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%@64 ]     : B aftertest% : ] : =8
DEF FNvld4_lane_16_4_064_wb : PROCregs22(4,3) : [ OPT 2 : VLD4.16 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%@64 ]!    : B aftertest% : ] : =8
DEF FNvld4_lane_16_4_064_rm : PROCregs22(4,3) : [ OPT 2 : VLD4.16 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%@64 ],Rm% : B aftertest% : ] : =8
DEF FNvld4_lane_16_d_xxx    : PROCregs22(7,3) : [ OPT 2 : VLD4.16 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%],D#(Vd%+6)[imm%]},[Rn%    ]     : B aftertest% : ] : =8
DEF FNvld4_lane_16_d_xxx_wb : PROCregs22(7,3) : [ OPT 2 : VLD4.16 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%],D#(Vd%+6)[imm%]},[Rn%    ]!    : B aftertest% : ] : =8
DEF FNvld4_lane_16_d_xxx_rm : PROCregs22(7,3) : [ OPT 2 : VLD4.16 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%],D#(Vd%+6)[imm%]},[Rn%    ],Rm% : B aftertest% : ] : =8
DEF FNvld4_lane_16_d_064    : PROCregs22(7,3) : [ OPT 2 : VLD4.16 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%],D#(Vd%+6)[imm%]},[Rn%@64 ]     : B aftertest% : ] : =8
DEF FNvld4_lane_16_d_064_wb : PROCregs22(7,3) : [ OPT 2 : VLD4.16 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%],D#(Vd%+6)[imm%]},[Rn%@64 ]!    : B aftertest% : ] : =8
DEF FNvld4_lane_16_d_064_rm : PROCregs22(7,3) : [ OPT 2 : VLD4.16 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%],D#(Vd%+6)[imm%]},[Rn%@64 ],Rm% : B aftertest% : ] : =8
DEF FNvld4_lane_32_4_xxx    : PROCregs22(4,1) : [ OPT 2 : VLD4.32 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%    ]     : B aftertest% : ] : =16
DEF FNvld4_lane_32_4_xxx_wb : PROCregs22(4,1) : [ OPT 2 : VLD4.32 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvld4_lane_32_4_xxx_rm : PROCregs22(4,1) : [ OPT 2 : VLD4.32 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvld4_lane_32_4_128    : PROCregs22(4,1) : [ OPT 2 : VLD4.32 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%@128]     : B aftertest% : ] : =16
DEF FNvld4_lane_32_4_128_wb : PROCregs22(4,1) : [ OPT 2 : VLD4.32 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvld4_lane_32_4_128_rm : PROCregs22(4,1) : [ OPT 2 : VLD4.32 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%@128],Rm% : B aftertest% : ] : =16
DEF FNvld4_lane_32_d_xxx    : PROCregs22(7,1) : [ OPT 2 : VLD4.32 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%],D#(Vd%+6)[imm%]},[Rn%    ]     : B aftertest% : ] : =16
DEF FNvld4_lane_32_d_xxx_wb : PROCregs22(7,1) : [ OPT 2 : VLD4.32 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%],D#(Vd%+6)[imm%]},[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvld4_lane_32_d_xxx_rm : PROCregs22(7,1) : [ OPT 2 : VLD4.32 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%],D#(Vd%+6)[imm%]},[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvld4_lane_32_d_128    : PROCregs22(7,1) : [ OPT 2 : VLD4.32 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%],D#(Vd%+6)[imm%]},[Rn%@128]     : B aftertest% : ] : =16
DEF FNvld4_lane_32_d_128_wb : PROCregs22(7,1) : [ OPT 2 : VLD4.32 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%],D#(Vd%+6)[imm%]},[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvld4_lane_32_d_128_rm : PROCregs22(7,1) : [ OPT 2 : VLD4.32 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%],D#(Vd%+6)[imm%]},[Rn%@128],Rm% : B aftertest% : ] : =16

DEF FNvst4_lane_08_4_xxx    : PROCregs22(4,7) : [ OPT 2 : VST4.8  {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%    ]     : B aftertest% : ] : =4
DEF FNvst4_lane_08_4_xxx_wb : PROCregs22(4,7) : [ OPT 2 : VST4.8  {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%    ]!    : B aftertest% : ] : =4
DEF FNvst4_lane_08_4_xxx_rm : PROCregs22(4,7) : [ OPT 2 : VST4.8  {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%    ],Rm% : B aftertest% : ] : =4
DEF FNvst4_lane_08_4_032    : PROCregs22(4,7) : [ OPT 2 : VST4.8  {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%@32 ]     : B aftertest% : ] : =4
DEF FNvst4_lane_08_4_032_wb : PROCregs22(4,7) : [ OPT 2 : VST4.8  {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%@32 ]!    : B aftertest% : ] : =4
DEF FNvst4_lane_08_4_032_rm : PROCregs22(4,7) : [ OPT 2 : VST4.8  {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%@32 ],Rm% : B aftertest% : ] : =4
DEF FNvst4_lane_16_4_xxx    : PROCregs22(4,3) : [ OPT 2 : VST4.16 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%    ]     : B aftertest% : ] : =8
DEF FNvst4_lane_16_4_xxx_wb : PROCregs22(4,3) : [ OPT 2 : VST4.16 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%    ]!    : B aftertest% : ] : =8
DEF FNvst4_lane_16_4_xxx_rm : PROCregs22(4,3) : [ OPT 2 : VST4.16 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%    ],Rm% : B aftertest% : ] : =8
DEF FNvst4_lane_16_4_064    : PROCregs22(4,3) : [ OPT 2 : VST4.16 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%@64 ]     : B aftertest% : ] : =8
DEF FNvst4_lane_16_4_064_wb : PROCregs22(4,3) : [ OPT 2 : VST4.16 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%@64 ]!    : B aftertest% : ] : =8
DEF FNvst4_lane_16_4_064_rm : PROCregs22(4,3) : [ OPT 2 : VST4.16 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%@64 ],Rm% : B aftertest% : ] : =8
DEF FNvst4_lane_16_d_xxx    : PROCregs22(7,3) : [ OPT 2 : VST4.16 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%],D#(Vd%+6)[imm%]},[Rn%    ]     : B aftertest% : ] : =8
DEF FNvst4_lane_16_d_xxx_wb : PROCregs22(7,3) : [ OPT 2 : VST4.16 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%],D#(Vd%+6)[imm%]},[Rn%    ]!    : B aftertest% : ] : =8
DEF FNvst4_lane_16_d_xxx_rm : PROCregs22(7,3) : [ OPT 2 : VST4.16 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%],D#(Vd%+6)[imm%]},[Rn%    ],Rm% : B aftertest% : ] : =8
DEF FNvst4_lane_16_d_064    : PROCregs22(7,3) : [ OPT 2 : VST4.16 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%],D#(Vd%+6)[imm%]},[Rn%@64 ]     : B aftertest% : ] : =8
DEF FNvst4_lane_16_d_064_wb : PROCregs22(7,3) : [ OPT 2 : VST4.16 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%],D#(Vd%+6)[imm%]},[Rn%@64 ]!    : B aftertest% : ] : =8
DEF FNvst4_lane_16_d_064_rm : PROCregs22(7,3) : [ OPT 2 : VST4.16 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%],D#(Vd%+6)[imm%]},[Rn%@64 ],Rm% : B aftertest% : ] : =8
DEF FNvst4_lane_32_4_xxx    : PROCregs22(4,1) : [ OPT 2 : VST4.32 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%    ]     : B aftertest% : ] : =16
DEF FNvst4_lane_32_4_xxx_wb : PROCregs22(4,1) : [ OPT 2 : VST4.32 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvst4_lane_32_4_xxx_rm : PROCregs22(4,1) : [ OPT 2 : VST4.32 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvst4_lane_32_4_128    : PROCregs22(4,1) : [ OPT 2 : VST4.32 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%@128]     : B aftertest% : ] : =16
DEF FNvst4_lane_32_4_128_wb : PROCregs22(4,1) : [ OPT 2 : VST4.32 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvst4_lane_32_4_128_rm : PROCregs22(4,1) : [ OPT 2 : VST4.32 {D#Vd%[imm%],D#(Vd%+1)[imm%],D#(Vd%+2)[imm%],D#(Vd%+3)[imm%]},[Rn%@128],Rm% : B aftertest% : ] : =16
DEF FNvst4_lane_32_d_xxx    : PROCregs22(7,1) : [ OPT 2 : VST4.32 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%],D#(Vd%+6)[imm%]},[Rn%    ]     : B aftertest% : ] : =16
DEF FNvst4_lane_32_d_xxx_wb : PROCregs22(7,1) : [ OPT 2 : VST4.32 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%],D#(Vd%+6)[imm%]},[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvst4_lane_32_d_xxx_rm : PROCregs22(7,1) : [ OPT 2 : VST4.32 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%],D#(Vd%+6)[imm%]},[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvst4_lane_32_d_128    : PROCregs22(7,1) : [ OPT 2 : VST4.32 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%],D#(Vd%+6)[imm%]},[Rn%@128]     : B aftertest% : ] : =16
DEF FNvst4_lane_32_d_128_wb : PROCregs22(7,1) : [ OPT 2 : VST4.32 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%],D#(Vd%+6)[imm%]},[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvst4_lane_32_d_128_rm : PROCregs22(7,1) : [ OPT 2 : VST4.32 {D#Vd%[imm%],D#(Vd%+2)[imm%],D#(Vd%+4)[imm%],D#(Vd%+6)[imm%]},[Rn%@128],Rm% : B aftertest% : ] : =16

REM VLD single element to all lanes

DEF FNvld1_repl_08_1_xxx    : PROCregs21(1) : [ OPT 2 : VLD1.8  {D#Vd%[]                            },[Rn%    ]     : B aftertest% : ] : =1
DEF FNvld1_repl_08_1_xxx_wb : PROCregs21(1) : [ OPT 2 : VLD1.8  {D#Vd%[]                            },[Rn%    ]!    : B aftertest% : ] : =1
DEF FNvld1_repl_08_1_xxx_rm : PROCregs21(1) : [ OPT 2 : VLD1.8  {D#Vd%[]                            },[Rn%    ],Rm% : B aftertest% : ] : =1
DEF FNvld1_repl_08_2_xxx    : PROCregs21(2) : [ OPT 2 : VLD1.8  {D#Vd%[],D#(Vd%+1)[]                },[Rn%    ]     : B aftertest% : ] : =1
DEF FNvld1_repl_08_2_xxx_wb : PROCregs21(2) : [ OPT 2 : VLD1.8  {D#Vd%[],D#(Vd%+1)[]                },[Rn%    ]!    : B aftertest% : ] : =1
DEF FNvld1_repl_08_2_xxx_rm : PROCregs21(2) : [ OPT 2 : VLD1.8  {D#Vd%[],D#(Vd%+1)[]                },[Rn%    ],Rm% : B aftertest% : ] : =1
DEF FNvld1_repl_16_1_xxx    : PROCregs21(1) : [ OPT 2 : VLD1.16 {D#Vd%[]                            },[Rn%    ]     : B aftertest% : ] : =2
DEF FNvld1_repl_16_1_xxx_wb : PROCregs21(1) : [ OPT 2 : VLD1.16 {D#Vd%[]                            },[Rn%    ]!    : B aftertest% : ] : =2
DEF FNvld1_repl_16_1_xxx_rm : PROCregs21(1) : [ OPT 2 : VLD1.16 {D#Vd%[]                            },[Rn%    ],Rm% : B aftertest% : ] : =2
DEF FNvld1_repl_16_1_016    : PROCregs21(1) : [ OPT 2 : VLD1.16 {D#Vd%[]                            },[Rn%@16 ]     : B aftertest% : ] : =2
DEF FNvld1_repl_16_1_016_wb : PROCregs21(1) : [ OPT 2 : VLD1.16 {D#Vd%[]                            },[Rn%@16 ]!    : B aftertest% : ] : =2
DEF FNvld1_repl_16_1_016_rm : PROCregs21(1) : [ OPT 2 : VLD1.16 {D#Vd%[]                            },[Rn%@16 ],Rm% : B aftertest% : ] : =2
DEF FNvld1_repl_16_2_xxx    : PROCregs21(2) : [ OPT 2 : VLD1.16 {D#Vd%[],D#(Vd%+1)[]                },[Rn%    ]     : B aftertest% : ] : =2
DEF FNvld1_repl_16_2_xxx_wb : PROCregs21(2) : [ OPT 2 : VLD1.16 {D#Vd%[],D#(Vd%+1)[]                },[Rn%    ]!    : B aftertest% : ] : =2
DEF FNvld1_repl_16_2_xxx_rm : PROCregs21(2) : [ OPT 2 : VLD1.16 {D#Vd%[],D#(Vd%+1)[]                },[Rn%    ],Rm% : B aftertest% : ] : =2
DEF FNvld1_repl_16_2_016    : PROCregs21(2) : [ OPT 2 : VLD1.16 {D#Vd%[],D#(Vd%+1)[]                },[Rn%@16 ]     : B aftertest% : ] : =2
DEF FNvld1_repl_16_2_016_wb : PROCregs21(2) : [ OPT 2 : VLD1.16 {D#Vd%[],D#(Vd%+1)[]                },[Rn%@16 ]!    : B aftertest% : ] : =2
DEF FNvld1_repl_16_2_016_rm : PROCregs21(2) : [ OPT 2 : VLD1.16 {D#Vd%[],D#(Vd%+1)[]                },[Rn%@16 ],Rm% : B aftertest% : ] : =2
DEF FNvld1_repl_32_1_xxx    : PROCregs21(1) : [ OPT 2 : VLD1.32 {D#Vd%[]                            },[Rn%    ]     : B aftertest% : ] : =4
DEF FNvld1_repl_32_1_xxx_wb : PROCregs21(1) : [ OPT 2 : VLD1.32 {D#Vd%[]                            },[Rn%    ]!    : B aftertest% : ] : =4
DEF FNvld1_repl_32_1_xxx_rm : PROCregs21(1) : [ OPT 2 : VLD1.32 {D#Vd%[]                            },[Rn%    ],Rm% : B aftertest% : ] : =4
DEF FNvld1_repl_32_1_032    : PROCregs21(1) : [ OPT 2 : VLD1.32 {D#Vd%[]                            },[Rn%@32 ]     : B aftertest% : ] : =4
DEF FNvld1_repl_32_1_032_wb : PROCregs21(1) : [ OPT 2 : VLD1.32 {D#Vd%[]                            },[Rn%@32 ]!    : B aftertest% : ] : =4
DEF FNvld1_repl_32_1_032_rm : PROCregs21(1) : [ OPT 2 : VLD1.32 {D#Vd%[]                            },[Rn%@32 ],Rm% : B aftertest% : ] : =4
DEF FNvld1_repl_32_2_xxx    : PROCregs21(2) : [ OPT 2 : VLD1.32 {D#Vd%[],D#(Vd%+1)[]                },[Rn%    ]     : B aftertest% : ] : =4
DEF FNvld1_repl_32_2_xxx_wb : PROCregs21(2) : [ OPT 2 : VLD1.32 {D#Vd%[],D#(Vd%+1)[]                },[Rn%    ]!    : B aftertest% : ] : =4
DEF FNvld1_repl_32_2_xxx_rm : PROCregs21(2) : [ OPT 2 : VLD1.32 {D#Vd%[],D#(Vd%+1)[]                },[Rn%    ],Rm% : B aftertest% : ] : =4
DEF FNvld1_repl_32_2_032    : PROCregs21(2) : [ OPT 2 : VLD1.32 {D#Vd%[],D#(Vd%+1)[]                },[Rn%@32 ]     : B aftertest% : ] : =4
DEF FNvld1_repl_32_2_032_wb : PROCregs21(2) : [ OPT 2 : VLD1.32 {D#Vd%[],D#(Vd%+1)[]                },[Rn%@32 ]!    : B aftertest% : ] : =4
DEF FNvld1_repl_32_2_032_rm : PROCregs21(2) : [ OPT 2 : VLD1.32 {D#Vd%[],D#(Vd%+1)[]                },[Rn%@32 ],Rm% : B aftertest% : ] : =4

REM VLD single 2-element structure to all lanes

DEF FNvld2_repl_08_2_xxx    : PROCregs21(2) : [ OPT 2 : VLD2.8  {D#Vd%[],D#(Vd%+1)[]                },[Rn%    ]     : B aftertest% : ] : =2
DEF FNvld2_repl_08_2_xxx_wb : PROCregs21(2) : [ OPT 2 : VLD2.8  {D#Vd%[],D#(Vd%+1)[]                },[Rn%    ]!    : B aftertest% : ] : =2
DEF FNvld2_repl_08_2_xxx_rm : PROCregs21(2) : [ OPT 2 : VLD2.8  {D#Vd%[],D#(Vd%+1)[]                },[Rn%    ],Rm% : B aftertest% : ] : =2
DEF FNvld2_repl_08_2_016    : PROCregs21(2) : [ OPT 2 : VLD2.8  {D#Vd%[],D#(Vd%+1)[]                },[Rn%@16 ]     : B aftertest% : ] : =2
DEF FNvld2_repl_08_2_016_wb : PROCregs21(2) : [ OPT 2 : VLD2.8  {D#Vd%[],D#(Vd%+1)[]                },[Rn%@16 ]!    : B aftertest% : ] : =2
DEF FNvld2_repl_08_2_016_rm : PROCregs21(2) : [ OPT 2 : VLD2.8  {D#Vd%[],D#(Vd%+1)[]                },[Rn%@16 ],Rm% : B aftertest% : ] : =2
DEF FNvld2_repl_08_d_xxx    : PROCregs21(3) : [ OPT 2 : VLD2.8  {D#Vd%[],D#(Vd%+2)[]                },[Rn%    ]     : B aftertest% : ] : =2
DEF FNvld2_repl_08_d_xxx_wb : PROCregs21(3) : [ OPT 2 : VLD2.8  {D#Vd%[],D#(Vd%+2)[]                },[Rn%    ]!    : B aftertest% : ] : =2
DEF FNvld2_repl_08_d_xxx_rm : PROCregs21(3) : [ OPT 2 : VLD2.8  {D#Vd%[],D#(Vd%+2)[]                },[Rn%    ],Rm% : B aftertest% : ] : =2
DEF FNvld2_repl_08_d_016    : PROCregs21(3) : [ OPT 2 : VLD2.8  {D#Vd%[],D#(Vd%+2)[]                },[Rn%@16 ]     : B aftertest% : ] : =2
DEF FNvld2_repl_08_d_016_wb : PROCregs21(3) : [ OPT 2 : VLD2.8  {D#Vd%[],D#(Vd%+2)[]                },[Rn%@16 ]!    : B aftertest% : ] : =2
DEF FNvld2_repl_08_d_016_rm : PROCregs21(3) : [ OPT 2 : VLD2.8  {D#Vd%[],D#(Vd%+2)[]                },[Rn%@16 ],Rm% : B aftertest% : ] : =2
DEF FNvld2_repl_16_2_xxx    : PROCregs21(2) : [ OPT 2 : VLD2.16 {D#Vd%[],D#(Vd%+1)[]                },[Rn%    ]     : B aftertest% : ] : =4
DEF FNvld2_repl_16_2_xxx_wb : PROCregs21(2) : [ OPT 2 : VLD2.16 {D#Vd%[],D#(Vd%+1)[]                },[Rn%    ]!    : B aftertest% : ] : =4
DEF FNvld2_repl_16_2_xxx_rm : PROCregs21(2) : [ OPT 2 : VLD2.16 {D#Vd%[],D#(Vd%+1)[]                },[Rn%    ],Rm% : B aftertest% : ] : =4
DEF FNvld2_repl_16_2_032    : PROCregs21(2) : [ OPT 2 : VLD2.16 {D#Vd%[],D#(Vd%+1)[]                },[Rn%@32 ]     : B aftertest% : ] : =4
DEF FNvld2_repl_16_2_032_wb : PROCregs21(2) : [ OPT 2 : VLD2.16 {D#Vd%[],D#(Vd%+1)[]                },[Rn%@32 ]!    : B aftertest% : ] : =4
DEF FNvld2_repl_16_2_032_rm : PROCregs21(2) : [ OPT 2 : VLD2.16 {D#Vd%[],D#(Vd%+1)[]                },[Rn%@32 ],Rm% : B aftertest% : ] : =4
DEF FNvld2_repl_16_d_xxx    : PROCregs21(3) : [ OPT 2 : VLD2.16 {D#Vd%[],D#(Vd%+2)[]                },[Rn%    ]     : B aftertest% : ] : =4
DEF FNvld2_repl_16_d_xxx_wb : PROCregs21(3) : [ OPT 2 : VLD2.16 {D#Vd%[],D#(Vd%+2)[]                },[Rn%    ]!    : B aftertest% : ] : =4
DEF FNvld2_repl_16_d_xxx_rm : PROCregs21(3) : [ OPT 2 : VLD2.16 {D#Vd%[],D#(Vd%+2)[]                },[Rn%    ],Rm% : B aftertest% : ] : =4
DEF FNvld2_repl_16_d_032    : PROCregs21(3) : [ OPT 2 : VLD2.16 {D#Vd%[],D#(Vd%+2)[]                },[Rn%@32 ]     : B aftertest% : ] : =4
DEF FNvld2_repl_16_d_032_wb : PROCregs21(3) : [ OPT 2 : VLD2.16 {D#Vd%[],D#(Vd%+2)[]                },[Rn%@32 ]!    : B aftertest% : ] : =4
DEF FNvld2_repl_16_d_032_rm : PROCregs21(3) : [ OPT 2 : VLD2.16 {D#Vd%[],D#(Vd%+2)[]                },[Rn%@32 ],Rm% : B aftertest% : ] : =4
DEF FNvld2_repl_32_2_xxx    : PROCregs21(2) : [ OPT 2 : VLD2.32 {D#Vd%[],D#(Vd%+1)[]                },[Rn%    ]     : B aftertest% : ] : =8
DEF FNvld2_repl_32_2_xxx_wb : PROCregs21(2) : [ OPT 2 : VLD2.32 {D#Vd%[],D#(Vd%+1)[]                },[Rn%    ]!    : B aftertest% : ] : =8
DEF FNvld2_repl_32_2_xxx_rm : PROCregs21(2) : [ OPT 2 : VLD2.32 {D#Vd%[],D#(Vd%+1)[]                },[Rn%    ],Rm% : B aftertest% : ] : =8
DEF FNvld2_repl_32_2_064    : PROCregs21(2) : [ OPT 2 : VLD2.32 {D#Vd%[],D#(Vd%+1)[]                },[Rn%@64 ]     : B aftertest% : ] : =8
DEF FNvld2_repl_32_2_064_wb : PROCregs21(2) : [ OPT 2 : VLD2.32 {D#Vd%[],D#(Vd%+1)[]                },[Rn%@64 ]!    : B aftertest% : ] : =8
DEF FNvld2_repl_32_2_064_rm : PROCregs21(2) : [ OPT 2 : VLD2.32 {D#Vd%[],D#(Vd%+1)[]                },[Rn%@64 ],Rm% : B aftertest% : ] : =8
DEF FNvld2_repl_32_d_xxx    : PROCregs21(3) : [ OPT 2 : VLD2.32 {D#Vd%[],D#(Vd%+2)[]                },[Rn%    ]     : B aftertest% : ] : =8
DEF FNvld2_repl_32_d_xxx_wb : PROCregs21(3) : [ OPT 2 : VLD2.32 {D#Vd%[],D#(Vd%+2)[]                },[Rn%    ]!    : B aftertest% : ] : =8
DEF FNvld2_repl_32_d_xxx_rm : PROCregs21(3) : [ OPT 2 : VLD2.32 {D#Vd%[],D#(Vd%+2)[]                },[Rn%    ],Rm% : B aftertest% : ] : =8
DEF FNvld2_repl_32_d_064    : PROCregs21(3) : [ OPT 2 : VLD2.32 {D#Vd%[],D#(Vd%+2)[]                },[Rn%@64 ]     : B aftertest% : ] : =8
DEF FNvld2_repl_32_d_064_wb : PROCregs21(3) : [ OPT 2 : VLD2.32 {D#Vd%[],D#(Vd%+2)[]                },[Rn%@64 ]!    : B aftertest% : ] : =8
DEF FNvld2_repl_32_d_064_rm : PROCregs21(3) : [ OPT 2 : VLD2.32 {D#Vd%[],D#(Vd%+2)[]                },[Rn%@64 ],Rm% : B aftertest% : ] : =8

REM VLD single 3-element structure to all lanes

DEF FNvld3_repl_08_3_xxx    : PROCregs21(3) : [ OPT 2 : VLD3.8  {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[]    },[Rn%    ]     : B aftertest% : ] : =3
DEF FNvld3_repl_08_3_xxx_wb : PROCregs21(3) : [ OPT 2 : VLD3.8  {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[]    },[Rn%    ]!    : B aftertest% : ] : =3
DEF FNvld3_repl_08_3_xxx_rm : PROCregs21(3) : [ OPT 2 : VLD3.8  {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[]    },[Rn%    ],Rm% : B aftertest% : ] : =3
DEF FNvld3_repl_08_d_xxx    : PROCregs21(5) : [ OPT 2 : VLD3.8  {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[]    },[Rn%    ]     : B aftertest% : ] : =3
DEF FNvld3_repl_08_d_xxx_wb : PROCregs21(5) : [ OPT 2 : VLD3.8  {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[]    },[Rn%    ]!    : B aftertest% : ] : =3
DEF FNvld3_repl_08_d_xxx_rm : PROCregs21(5) : [ OPT 2 : VLD3.8  {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[]    },[Rn%    ],Rm% : B aftertest% : ] : =3
DEF FNvld3_repl_16_3_xxx    : PROCregs21(3) : [ OPT 2 : VLD3.16 {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[]    },[Rn%    ]     : B aftertest% : ] : =6
DEF FNvld3_repl_16_3_xxx_wb : PROCregs21(3) : [ OPT 2 : VLD3.16 {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[]    },[Rn%    ]!    : B aftertest% : ] : =6
DEF FNvld3_repl_16_3_xxx_rm : PROCregs21(3) : [ OPT 2 : VLD3.16 {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[]    },[Rn%    ],Rm% : B aftertest% : ] : =6
DEF FNvld3_repl_16_d_xxx    : PROCregs21(5) : [ OPT 2 : VLD3.16 {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[]    },[Rn%    ]     : B aftertest% : ] : =6
DEF FNvld3_repl_16_d_xxx_wb : PROCregs21(5) : [ OPT 2 : VLD3.16 {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[]    },[Rn%    ]!    : B aftertest% : ] : =6
DEF FNvld3_repl_16_d_xxx_rm : PROCregs21(5) : [ OPT 2 : VLD3.16 {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[]    },[Rn%    ],Rm% : B aftertest% : ] : =6
DEF FNvld3_repl_32_3_xxx    : PROCregs21(3) : [ OPT 2 : VLD3.32 {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[]    },[Rn%    ]     : B aftertest% : ] : =12
DEF FNvld3_repl_32_3_xxx_wb : PROCregs21(3) : [ OPT 2 : VLD3.32 {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[]    },[Rn%    ]!    : B aftertest% : ] : =12
DEF FNvld3_repl_32_3_xxx_rm : PROCregs21(3) : [ OPT 2 : VLD3.32 {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[]    },[Rn%    ],Rm% : B aftertest% : ] : =12
DEF FNvld3_repl_32_d_xxx    : PROCregs21(5) : [ OPT 2 : VLD3.32 {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[]    },[Rn%    ]     : B aftertest% : ] : =12
DEF FNvld3_repl_32_d_xxx_wb : PROCregs21(5) : [ OPT 2 : VLD3.32 {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[]    },[Rn%    ]!    : B aftertest% : ] : =12
DEF FNvld3_repl_32_d_xxx_rm : PROCregs21(5) : [ OPT 2 : VLD3.32 {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[]    },[Rn%    ],Rm% : B aftertest% : ] : =12

REM VLD single 4-element structure to all lanes

DEF FNvld4_repl_08_4_xxx    : PROCregs21(4) : [ OPT 2 : VLD4.8  {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[],D#(Vd%+3)[]},[Rn%    ]     : B aftertest% : ] : =4
DEF FNvld4_repl_08_4_xxx_wb : PROCregs21(4) : [ OPT 2 : VLD4.8  {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[],D#(Vd%+3)[]},[Rn%    ]!    : B aftertest% : ] : =4
DEF FNvld4_repl_08_4_xxx_rm : PROCregs21(4) : [ OPT 2 : VLD4.8  {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[],D#(Vd%+3)[]},[Rn%    ],Rm% : B aftertest% : ] : =4
DEF FNvld4_repl_08_4_032    : PROCregs21(4) : [ OPT 2 : VLD4.8  {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[],D#(Vd%+3)[]},[Rn%@32 ]     : B aftertest% : ] : =4
DEF FNvld4_repl_08_4_032_wb : PROCregs21(4) : [ OPT 2 : VLD4.8  {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[],D#(Vd%+3)[]},[Rn%@32 ]!    : B aftertest% : ] : =4
DEF FNvld4_repl_08_4_032_rm : PROCregs21(4) : [ OPT 2 : VLD4.8  {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[],D#(Vd%+3)[]},[Rn%@32 ],Rm% : B aftertest% : ] : =4
DEF FNvld4_repl_08_d_xxx    : PROCregs21(7) : [ OPT 2 : VLD4.8  {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[],D#(Vd%+6)[]},[Rn%    ]     : B aftertest% : ] : =4
DEF FNvld4_repl_08_d_xxx_wb : PROCregs21(7) : [ OPT 2 : VLD4.8  {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[],D#(Vd%+6)[]},[Rn%    ]!    : B aftertest% : ] : =4
DEF FNvld4_repl_08_d_xxx_rm : PROCregs21(7) : [ OPT 2 : VLD4.8  {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[],D#(Vd%+6)[]},[Rn%    ],Rm% : B aftertest% : ] : =4
DEF FNvld4_repl_08_d_032    : PROCregs21(7) : [ OPT 2 : VLD4.8  {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[],D#(Vd%+6)[]},[Rn%@32 ]     : B aftertest% : ] : =4
DEF FNvld4_repl_08_d_032_wb : PROCregs21(7) : [ OPT 2 : VLD4.8  {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[],D#(Vd%+6)[]},[Rn%@32 ]!    : B aftertest% : ] : =4
DEF FNvld4_repl_08_d_032_rm : PROCregs21(7) : [ OPT 2 : VLD4.8  {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[],D#(Vd%+6)[]},[Rn%@32 ],Rm% : B aftertest% : ] : =4
DEF FNvld4_repl_16_4_xxx    : PROCregs21(4) : [ OPT 2 : VLD4.16 {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[],D#(Vd%+3)[]},[Rn%    ]     : B aftertest% : ] : =8
DEF FNvld4_repl_16_4_xxx_wb : PROCregs21(4) : [ OPT 2 : VLD4.16 {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[],D#(Vd%+3)[]},[Rn%    ]!    : B aftertest% : ] : =8
DEF FNvld4_repl_16_4_xxx_rm : PROCregs21(4) : [ OPT 2 : VLD4.16 {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[],D#(Vd%+3)[]},[Rn%    ],Rm% : B aftertest% : ] : =8
DEF FNvld4_repl_16_4_064    : PROCregs21(4) : [ OPT 2 : VLD4.16 {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[],D#(Vd%+3)[]},[Rn%@64 ]     : B aftertest% : ] : =8
DEF FNvld4_repl_16_4_064_wb : PROCregs21(4) : [ OPT 2 : VLD4.16 {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[],D#(Vd%+3)[]},[Rn%@64 ]!    : B aftertest% : ] : =8
DEF FNvld4_repl_16_4_064_rm : PROCregs21(4) : [ OPT 2 : VLD4.16 {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[],D#(Vd%+3)[]},[Rn%@64 ],Rm% : B aftertest% : ] : =8
DEF FNvld4_repl_16_d_xxx    : PROCregs21(7) : [ OPT 2 : VLD4.16 {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[],D#(Vd%+6)[]},[Rn%    ]     : B aftertest% : ] : =8
DEF FNvld4_repl_16_d_xxx_wb : PROCregs21(7) : [ OPT 2 : VLD4.16 {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[],D#(Vd%+6)[]},[Rn%    ]!    : B aftertest% : ] : =8
DEF FNvld4_repl_16_d_xxx_rm : PROCregs21(7) : [ OPT 2 : VLD4.16 {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[],D#(Vd%+6)[]},[Rn%    ],Rm% : B aftertest% : ] : =8
DEF FNvld4_repl_16_d_064    : PROCregs21(7) : [ OPT 2 : VLD4.16 {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[],D#(Vd%+6)[]},[Rn%@64 ]     : B aftertest% : ] : =8
DEF FNvld4_repl_16_d_064_wb : PROCregs21(7) : [ OPT 2 : VLD4.16 {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[],D#(Vd%+6)[]},[Rn%@64 ]!    : B aftertest% : ] : =8
DEF FNvld4_repl_16_d_064_rm : PROCregs21(7) : [ OPT 2 : VLD4.16 {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[],D#(Vd%+6)[]},[Rn%@64 ],Rm% : B aftertest% : ] : =8
DEF FNvld4_repl_32_4_xxx    : PROCregs21(4) : [ OPT 2 : VLD4.32 {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[],D#(Vd%+3)[]},[Rn%    ]     : B aftertest% : ] : =16
DEF FNvld4_repl_32_4_xxx_wb : PROCregs21(4) : [ OPT 2 : VLD4.32 {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[],D#(Vd%+3)[]},[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvld4_repl_32_4_xxx_rm : PROCregs21(4) : [ OPT 2 : VLD4.32 {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[],D#(Vd%+3)[]},[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvld4_repl_32_4_064    : PROCregs21(4) : [ OPT 2 : VLD4.32 {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[],D#(Vd%+3)[]},[Rn%@64 ]     : B aftertest% : ] : =16
DEF FNvld4_repl_32_4_064_wb : PROCregs21(4) : [ OPT 2 : VLD4.32 {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[],D#(Vd%+3)[]},[Rn%@64 ]!    : B aftertest% : ] : =16
DEF FNvld4_repl_32_4_064_rm : PROCregs21(4) : [ OPT 2 : VLD4.32 {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[],D#(Vd%+3)[]},[Rn%@64 ],Rm% : B aftertest% : ] : =16
DEF FNvld4_repl_32_4_128    : PROCregs21(4) : [ OPT 2 : VLD4.32 {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[],D#(Vd%+3)[]},[Rn%@128]     : B aftertest% : ] : =16
DEF FNvld4_repl_32_4_128_wb : PROCregs21(4) : [ OPT 2 : VLD4.32 {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[],D#(Vd%+3)[]},[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvld4_repl_32_4_128_rm : PROCregs21(4) : [ OPT 2 : VLD4.32 {D#Vd%[],D#(Vd%+1)[],D#(Vd%+2)[],D#(Vd%+3)[]},[Rn%@128],Rm% : B aftertest% : ] : =16
DEF FNvld4_repl_32_d_xxx    : PROCregs21(7) : [ OPT 2 : VLD4.32 {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[],D#(Vd%+6)[]},[Rn%    ]     : B aftertest% : ] : =16
DEF FNvld4_repl_32_d_xxx_wb : PROCregs21(7) : [ OPT 2 : VLD4.32 {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[],D#(Vd%+6)[]},[Rn%    ]!    : B aftertest% : ] : =16
DEF FNvld4_repl_32_d_xxx_rm : PROCregs21(7) : [ OPT 2 : VLD4.32 {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[],D#(Vd%+6)[]},[Rn%    ],Rm% : B aftertest% : ] : =16
DEF FNvld4_repl_32_d_064    : PROCregs21(7) : [ OPT 2 : VLD4.32 {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[],D#(Vd%+6)[]},[Rn%@64 ]     : B aftertest% : ] : =16
DEF FNvld4_repl_32_d_064_wb : PROCregs21(7) : [ OPT 2 : VLD4.32 {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[],D#(Vd%+6)[]},[Rn%@64 ]!    : B aftertest% : ] : =16
DEF FNvld4_repl_32_d_064_rm : PROCregs21(7) : [ OPT 2 : VLD4.32 {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[],D#(Vd%+6)[]},[Rn%@64 ],Rm% : B aftertest% : ] : =16
DEF FNvld4_repl_32_d_128    : PROCregs21(7) : [ OPT 2 : VLD4.32 {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[],D#(Vd%+6)[]},[Rn%@128]     : B aftertest% : ] : =16
DEF FNvld4_repl_32_d_128_wb : PROCregs21(7) : [ OPT 2 : VLD4.32 {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[],D#(Vd%+6)[]},[Rn%@128]!    : B aftertest% : ] : =16
DEF FNvld4_repl_32_d_128_rm : PROCregs21(7) : [ OPT 2 : VLD4.32 {D#Vd%[],D#(Vd%+2)[],D#(Vd%+4)[],D#(Vd%+6)[]},[Rn%@128],Rm% : B aftertest% : ] : =16

DEF FNswp  : PROCregs23 : [ OPT 2 : SWP  (Rt%),(Rt2%),[(Rn%)] : B aftertest% : ] : =4
DEF FNswpb : PROCregs23 : [ OPT 2 : SWPB (Rt%),(Rt2%),[(Rn%)] : B aftertest% : ] : =1

REM SRS
REM To keep things simple we'll test from SVC mode, using R13_usr as the destination
DEF FNsrsia_usr    : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #&93 : MSR SPSR_cxsf, R1 : MOV LR,R0 : SRSIA SP ,#16 : MSR CPSR_c, #16 : B aftertest% : ] : =0
DEF FNsrsib_usr    : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #&93 : MSR SPSR_cxsf, R1 : MOV LR,R0 : SRSIB SP ,#16 : MSR CPSR_c, #16 : B aftertest% : ] : =0
DEF FNsrsda_usr    : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #&93 : MSR SPSR_cxsf, R1 : MOV LR,R0 : SRSDA SP ,#16 : MSR CPSR_c, #16 : B aftertest% : ] : =0
DEF FNsrsdb_usr    : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #&93 : MSR SPSR_cxsf, R1 : MOV LR,R0 : SRSDB SP ,#16 : MSR CPSR_c, #16 : B aftertest% : ] : =0
DEF FNsrsia_usr_wb : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #&93 : MSR SPSR_cxsf, R1 : MOV LR,R0 : SRSIA SP!,#16 : MSR CPSR_c, #16 : B aftertest% : ] : =0
DEF FNsrsib_usr_wb : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #&93 : MSR SPSR_cxsf, R1 : MOV LR,R0 : SRSIB SP!,#16 : MSR CPSR_c, #16 : B aftertest% : ] : =0
DEF FNsrsda_usr_wb : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #&93 : MSR SPSR_cxsf, R1 : MOV LR,R0 : SRSDA SP!,#16 : MSR CPSR_c, #16 : B aftertest% : ] : =0
DEF FNsrsdb_usr_wb : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #&93 : MSR SPSR_cxsf, R1 : MOV LR,R0 : SRSDB SP!,#16 : MSR CPSR_c, #16 : B aftertest% : ] : =0

REM Exception return LDM

DEF FNldmia_exc    : PROCregs24 : X%=P%+12 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #&93 : MSR SPSR_cxsf, #16 : LDMIA (Rn%) ,{R0-R15}^ : SWI "OS_LeaveOS" : B aftertest% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =16
DEF FNldmib_exc    : PROCregs24 : X%=P%+12 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #&93 : MSR SPSR_cxsf, #16 : LDMIB (Rn%) ,{R0-R15}^ : SWI "OS_LeaveOS" : B aftertest% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =16
DEF FNldmda_exc    : PROCregs24 : X%=P%+12 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #&93 : MSR SPSR_cxsf, #16 : LDMDA (Rn%) ,{R0-R15}^ : SWI "OS_LeaveOS" : B aftertest% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =16
DEF FNldmdb_exc    : PROCregs24 : X%=P%+12 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #&93 : MSR SPSR_cxsf, #16 : LDMDB (Rn%) ,{R0-R15}^ : SWI "OS_LeaveOS" : B aftertest% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =16
DEF FNldmia_exc_wb : PROCregs25 : X%=P%+12 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #&93 : MSR SPSR_cxsf, #16 : LDMIA (Rn%)!,{R0-R15}^ : SWI "OS_LeaveOS" : B aftertest% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =16
DEF FNldmib_exc_wb : PROCregs25 : X%=P%+12 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #&93 : MSR SPSR_cxsf, #16 : LDMIB (Rn%)!,{R0-R15}^ : SWI "OS_LeaveOS" : B aftertest% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =16
DEF FNldmda_exc_wb : PROCregs25 : X%=P%+12 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #&93 : MSR SPSR_cxsf, #16 : LDMDA (Rn%)!,{R0-R15}^ : SWI "OS_LeaveOS" : B aftertest% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =16
DEF FNldmdb_exc_wb : PROCregs25 : X%=P%+12 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #&93 : MSR SPSR_cxsf, #16 : LDMDB (Rn%)!,{R0-R15}^ : SWI "OS_LeaveOS" : B aftertest% : ] : ?X%=Rt% : X%?1=(Rt%>>8) : SYS "OS_SynchroniseCodeAreas",1,X%,X%+4 : =16

REM RFE
REM We can test this from SYS mode, allowing us to use any of R0-R14 as the base register
DEF FNrfeia_sys    : Rn%=FNrnd(0,14) : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #&1F : RFEIA (Rn%)  : MSR CPSR_c, #16 : B aftertest% : ] : =0
DEF FNrfeib_sys    : Rn%=FNrnd(0,14) : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #&1F : RFEIB (Rn%)  : MSR CPSR_c, #16 : B aftertest% : ] : =0
DEF FNrfeda_sys    : Rn%=FNrnd(0,14) : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #&1F : RFEDA (Rn%)  : MSR CPSR_c, #16 : B aftertest% : ] : =0
DEF FNrfedb_sys    : Rn%=FNrnd(0,14) : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #&1F : RFEDB (Rn%)  : MSR CPSR_c, #16 : B aftertest% : ] : =0
DEF FNrfeia_sys_wb : Rn%=FNrnd(0,14) : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #&1F : RFEIA (Rn%)! : MSR CPSR_c, #16 : B aftertest% : ] : =0
DEF FNrfeib_sys_wb : Rn%=FNrnd(0,14) : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #&1F : RFEIB (Rn%)! : MSR CPSR_c, #16 : B aftertest% : ] : =0
DEF FNrfeda_sys_wb : Rn%=FNrnd(0,14) : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #&1F : RFEDA (Rn%)! : MSR CPSR_c, #16 : B aftertest% : ] : =0
DEF FNrfedb_sys_wb : Rn%=FNrnd(0,14) : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c, #&1F : RFEDB (Rn%)! : MSR CPSR_c, #16 : B aftertest% : ] : =0

REM Load/store unprivileged immediate

DEF FNldrt_imm_post   : PROCregs4 : [ OPT 2 : LDRT   (Rt%),[(Rn%)],#FNimm(-4095,4095)   : B aftertest% : ] : =4
DEF FNstrt_imm_post   : PROCregs4 : [ OPT 2 : STRT   (Rt%),[(Rn%)],#FNimm(-4095,4095)   : B aftertest% : ] : =4

DEF FNldrbt_imm_post  : PROCregs4 : [ OPT 2 : LDRBT  (Rt%),[(Rn%)],#FNimm(-4095,4095)   : B aftertest% : ] : =1
DEF FNstrbt_imm_post  : PROCregs4 : [ OPT 2 : STRBT  (Rt%),[(Rn%)],#FNimm(-4095,4095)   : B aftertest% : ] : =1

DEF FNldrht_imm_post  : PROCregs4 : [ OPT 2 : LDRHT  (Rt%),[(Rn%)],#FNimm(-255,255)     : B aftertest% : ] : =2
DEF FNstrht_imm_post  : PROCregs4 : [ OPT 2 : STRHT  (Rt%),[(Rn%)],#FNimm(-255,255)     : B aftertest% : ] : =2

DEF FNldrsbt_imm_post : PROCregs4 : [ OPT 2 : LDRSBT (Rt%),[(Rn%)],#FNimm(-255,255)     : B aftertest% : ] : =-1
DEF FNldrsht_imm_post : PROCregs4 : [ OPT 2 : LDRSHT (Rt%),[(Rn%)],#FNimm(-255,255)     : B aftertest% : ] : =-2

REM Load/store unprivileged register

DEF FNldrt_reg_p_post   : PROCregs14("p")    : [ OPT 2 : LDRT   (Rt%),[(Rn%)], (Rm%)               : B aftertest% : ] : =4
DEF FNldrt_reg_n_post   : PROCregs14("n")    : [ OPT 2 : LDRT   (Rt%),[(Rn%)],-(Rm%)               : B aftertest% : ] : =4
DEF FNldrt_LSL_p_post   : PROCregs14("pLSL") : [ OPT 2 : LDRT   (Rt%),[(Rn%)], (Rm%),LSL #shift%   : B aftertest% : ] : =4
DEF FNldrt_LSL_n_post   : PROCregs14("nLSL") : [ OPT 2 : LDRT   (Rt%),[(Rn%)],-(Rm%),LSL #shift%   : B aftertest% : ] : =4
DEF FNldrt_LSR_p_post   : PROCregs14("pLSR") : [ OPT 2 : LDRT   (Rt%),[(Rn%)], (Rm%),LSR #shift%   : B aftertest% : ] : =4
DEF FNldrt_LSR_n_post   : PROCregs14("nLSR") : [ OPT 2 : LDRT   (Rt%),[(Rn%)],-(Rm%),LSR #shift%   : B aftertest% : ] : =4
DEF FNldrt_ASR_p_post   : PROCregs14("pASR") : [ OPT 2 : LDRT   (Rt%),[(Rn%)], (Rm%),ASR #shift%   : B aftertest% : ] : =4
DEF FNldrt_ASR_n_post   : PROCregs14("nASR") : [ OPT 2 : LDRT   (Rt%),[(Rn%)],-(Rm%),ASR #shift%   : B aftertest% : ] : =4
DEF FNldrt_ROR_p_post   : PROCregs14("pROR") : [ OPT 2 : LDRT   (Rt%),[(Rn%)], (Rm%),ROR #shift%   : B aftertest% : ] : =4
DEF FNldrt_ROR_n_post   : PROCregs14("nROR") : [ OPT 2 : LDRT   (Rt%),[(Rn%)],-(Rm%),ROR #shift%   : B aftertest% : ] : =4
DEF FNldrt_RRX_p_post   : PROCregs14("pRRX") : [ OPT 2 : LDRT   (Rt%),[(Rn%)], (Rm%),RRX           : B aftertest% : ] : =4
DEF FNldrt_RRX_n_post   : PROCregs14("nRRX") : [ OPT 2 : LDRT   (Rt%),[(Rn%)],-(Rm%),RRX           : B aftertest% : ] : =4
DEF FNstrt_reg_p_post   : PROCregs14("p")    : [ OPT 2 : STRT   (Rt%),[(Rn%)], (Rm%)               : B aftertest% : ] : =4
DEF FNstrt_reg_n_post   : PROCregs14("n")    : [ OPT 2 : STRT   (Rt%),[(Rn%)],-(Rm%)               : B aftertest% : ] : =4
DEF FNstrt_LSL_p_post   : PROCregs14("pLSL") : [ OPT 2 : STRT   (Rt%),[(Rn%)], (Rm%),LSL #shift%   : B aftertest% : ] : =4
DEF FNstrt_LSL_n_post   : PROCregs14("nLSL") : [ OPT 2 : STRT   (Rt%),[(Rn%)],-(Rm%),LSL #shift%   : B aftertest% : ] : =4
DEF FNstrt_LSR_p_post   : PROCregs14("pLSR") : [ OPT 2 : STRT   (Rt%),[(Rn%)], (Rm%),LSR #shift%   : B aftertest% : ] : =4
DEF FNstrt_LSR_n_post   : PROCregs14("nLSR") : [ OPT 2 : STRT   (Rt%),[(Rn%)],-(Rm%),LSR #shift%   : B aftertest% : ] : =4
DEF FNstrt_ASR_p_post   : PROCregs14("pASR") : [ OPT 2 : STRT   (Rt%),[(Rn%)], (Rm%),ASR #shift%   : B aftertest% : ] : =4
DEF FNstrt_ASR_n_post   : PROCregs14("nASR") : [ OPT 2 : STRT   (Rt%),[(Rn%)],-(Rm%),ASR #shift%   : B aftertest% : ] : =4
DEF FNstrt_ROR_p_post   : PROCregs14("pROR") : [ OPT 2 : STRT   (Rt%),[(Rn%)], (Rm%),ROR #shift%   : B aftertest% : ] : =4
DEF FNstrt_ROR_n_post   : PROCregs14("nROR") : [ OPT 2 : STRT   (Rt%),[(Rn%)],-(Rm%),ROR #shift%   : B aftertest% : ] : =4
DEF FNstrt_RRX_p_post   : PROCregs14("pRRX") : [ OPT 2 : STRT   (Rt%),[(Rn%)], (Rm%),RRX           : B aftertest% : ] : =4
DEF FNstrt_RRX_n_post   : PROCregs14("nRRX") : [ OPT 2 : STRT   (Rt%),[(Rn%)],-(Rm%),RRX           : B aftertest% : ] : =4

DEF FNldrbt_reg_p_post  : PROCregs14("p")    : [ OPT 2 : LDRBT  (Rt%),[(Rn%)], (Rm%)               : B aftertest% : ] : =1
DEF FNldrbt_reg_n_post  : PROCregs14("n")    : [ OPT 2 : LDRBT  (Rt%),[(Rn%)],-(Rm%)               : B aftertest% : ] : =1
DEF FNldrbt_LSL_p_post  : PROCregs14("pLSL") : [ OPT 2 : LDRBT  (Rt%),[(Rn%)], (Rm%),LSL #shift%   : B aftertest% : ] : =1
DEF FNldrbt_LSL_n_post  : PROCregs14("nLSL") : [ OPT 2 : LDRBT  (Rt%),[(Rn%)],-(Rm%),LSL #shift%   : B aftertest% : ] : =1
DEF FNldrbt_LSR_p_post  : PROCregs14("pLSR") : [ OPT 2 : LDRBT  (Rt%),[(Rn%)], (Rm%),LSR #shift%   : B aftertest% : ] : =1
DEF FNldrbt_LSR_n_post  : PROCregs14("nLSR") : [ OPT 2 : LDRBT  (Rt%),[(Rn%)],-(Rm%),LSR #shift%   : B aftertest% : ] : =1
DEF FNldrbt_ASR_p_post  : PROCregs14("pASR") : [ OPT 2 : LDRBT  (Rt%),[(Rn%)], (Rm%),ASR #shift%   : B aftertest% : ] : =1
DEF FNldrbt_ASR_n_post  : PROCregs14("nASR") : [ OPT 2 : LDRBT  (Rt%),[(Rn%)],-(Rm%),ASR #shift%   : B aftertest% : ] : =1
DEF FNldrbt_ROR_p_post  : PROCregs14("pROR") : [ OPT 2 : LDRBT  (Rt%),[(Rn%)], (Rm%),ROR #shift%   : B aftertest% : ] : =1
DEF FNldrbt_ROR_n_post  : PROCregs14("nROR") : [ OPT 2 : LDRBT  (Rt%),[(Rn%)],-(Rm%),ROR #shift%   : B aftertest% : ] : =1
DEF FNldrbt_RRX_p_post  : PROCregs14("pRRX") : [ OPT 2 : LDRBT  (Rt%),[(Rn%)], (Rm%),RRX           : B aftertest% : ] : =1
DEF FNldrbt_RRX_n_post  : PROCregs14("nRRX") : [ OPT 2 : LDRBT  (Rt%),[(Rn%)],-(Rm%),RRX           : B aftertest% : ] : =1
DEF FNstrbt_reg_p_post  : PROCregs14("p")    : [ OPT 2 : STRBT  (Rt%),[(Rn%)], (Rm%)               : B aftertest% : ] : =1
DEF FNstrbt_reg_n_post  : PROCregs14("n")    : [ OPT 2 : STRBT  (Rt%),[(Rn%)],-(Rm%)               : B aftertest% : ] : =1
DEF FNstrbt_LSL_p_post  : PROCregs14("pLSL") : [ OPT 2 : STRBT  (Rt%),[(Rn%)], (Rm%),LSL #shift%   : B aftertest% : ] : =1
DEF FNstrbt_LSL_n_post  : PROCregs14("nLSL") : [ OPT 2 : STRBT  (Rt%),[(Rn%)],-(Rm%),LSL #shift%   : B aftertest% : ] : =1
DEF FNstrbt_LSR_p_post  : PROCregs14("pLSR") : [ OPT 2 : STRBT  (Rt%),[(Rn%)], (Rm%),LSR #shift%   : B aftertest% : ] : =1
DEF FNstrbt_LSR_n_post  : PROCregs14("nLSR") : [ OPT 2 : STRBT  (Rt%),[(Rn%)],-(Rm%),LSR #shift%   : B aftertest% : ] : =1
DEF FNstrbt_ASR_p_post  : PROCregs14("pASR") : [ OPT 2 : STRBT  (Rt%),[(Rn%)], (Rm%),ASR #shift%   : B aftertest% : ] : =1
DEF FNstrbt_ASR_n_post  : PROCregs14("nASR") : [ OPT 2 : STRBT  (Rt%),[(Rn%)],-(Rm%),ASR #shift%   : B aftertest% : ] : =1
DEF FNstrbt_ROR_p_post  : PROCregs14("pROR") : [ OPT 2 : STRBT  (Rt%),[(Rn%)], (Rm%),ROR #shift%   : B aftertest% : ] : =1
DEF FNstrbt_ROR_n_post  : PROCregs14("nROR") : [ OPT 2 : STRBT  (Rt%),[(Rn%)],-(Rm%),ROR #shift%   : B aftertest% : ] : =1
DEF FNstrbt_RRX_p_post  : PROCregs14("pRRX") : [ OPT 2 : STRBT  (Rt%),[(Rn%)], (Rm%),RRX           : B aftertest% : ] : =1
DEF FNstrbt_RRX_n_post  : PROCregs14("nRRX") : [ OPT 2 : STRBT  (Rt%),[(Rn%)],-(Rm%),RRX           : B aftertest% : ] : =1

DEF FNldrht_reg_p_post  : PROCregs14("p")    : [ OPT 2 : LDRHT  (Rt%),[(Rn%)], (Rm%)   : B aftertest% : ] : =2
DEF FNldrht_reg_n_post  : PROCregs14("n")    : [ OPT 2 : LDRHT  (Rt%),[(Rn%)],-(Rm%)   : B aftertest% : ] : =2
DEF FNstrht_reg_p_post  : PROCregs14("p")    : [ OPT 2 : STRHT  (Rt%),[(Rn%)], (Rm%)   : B aftertest% : ] : =2
DEF FNstrht_reg_n_post  : PROCregs14("n")    : [ OPT 2 : STRHT  (Rt%),[(Rn%)],-(Rm%)   : B aftertest% : ] : =2

DEF FNldrsbt_reg_p_post : PROCregs14("p")    : [ OPT 2 : LDRSBT (Rt%),[(Rn%)], (Rm%)   : B aftertest% : ] : =-1
DEF FNldrsbt_reg_n_post : PROCregs14("n")    : [ OPT 2 : LDRSBT (Rt%),[(Rn%)],-(Rm%)   : B aftertest% : ] : =-1

DEF FNldrsht_reg_p_post : PROCregs14("p")    : [ OPT 2 : LDRSHT (Rt%),[(Rn%)], (Rm%)   : B aftertest% : ] : =-2
DEF FNldrsht_reg_n_post : PROCregs14("n")    : [ OPT 2 : LDRSHT (Rt%),[(Rn%)],-(Rm%)   : B aftertest% : ] : =-2

REM LDREX/STREX, LDA/STA, etc.

DEF FNldrexU  : PROCregs3  : [ OPT 2 : LDREX        (Rt%),       [(Rn%)] : B aftertest% : ] : =4
DEF FNldrexUb : PROCregs3  : [ OPT 2 : LDREXB       (Rt%),       [(Rn%)] : B aftertest% : ] : =1
DEF FNldrexUd : PROCregs5  : [ OPT 2 : LDREXD       (Rt%),(Rt2%),[(Rn%)] : B aftertest% : ] : =8
DEF FNldrexUh : PROCregs3  : [ OPT 2 : LDREXH       (Rt%),       [(Rn%)] : B aftertest% : ] : =2
DEF FNstrexU  : PROCregs26 : [ OPT 2 : STREX  (Rd%),(Rt%),       [(Rn%)] : B aftertest% : ] : =4
DEF FNstrexUb : PROCregs26 : [ OPT 2 : STREXB (Rd%),(Rt%),       [(Rn%)] : B aftertest% : ] : =1
DEF FNstrexUd : PROCregs27 : [ OPT 2 : STREXD (Rd%),(Rt%),(Rt2%),[(Rn%)] : B aftertest% : ] : =8
DEF FNstrexUh : PROCregs26 : [ OPT 2 : STREXH (Rd%),(Rt%),       [(Rn%)] : B aftertest% : ] : =2

DEF FNldaexU  : PROCregs3  : [ OPT 2 : LDAEX        (Rt%),       [(Rn%)] : B aftertest% : ] : =4
DEF FNldaexUb : PROCregs3  : [ OPT 2 : LDAEXB       (Rt%),       [(Rn%)] : B aftertest% : ] : =1
DEF FNldaexUd : PROCregs5  : [ OPT 2 : LDAEXD       (Rt%),(Rt2%),[(Rn%)] : B aftertest% : ] : =8
DEF FNldaexUh : PROCregs3  : [ OPT 2 : LDAEXH       (Rt%),       [(Rn%)] : B aftertest% : ] : =2
DEF FNstlexU  : PROCregs26 : [ OPT 2 : STLEX  (Rd%),(Rt%),       [(Rn%)] : B aftertest% : ] : =4
DEF FNstlexUb : PROCregs26 : [ OPT 2 : STLEXB (Rd%),(Rt%),       [(Rn%)] : B aftertest% : ] : =1
DEF FNstlexUd : PROCregs27 : [ OPT 2 : STLEXD (Rd%),(Rt%),(Rt2%),[(Rn%)] : B aftertest% : ] : =8
DEF FNstlexUh : PROCregs26 : [ OPT 2 : STLEXH (Rd%),(Rt%),       [(Rn%)] : B aftertest% : ] : =2

DEF FNldaU  : PROCregs3 : [ OPT 2 : LDA  (Rt%),[(Rn%)] : B aftertest% : ] : =4
DEF FNldaUb : PROCregs3 : [ OPT 2 : LDAB (Rt%),[(Rn%)] : B aftertest% : ] : =1
DEF FNldaUh : PROCregs3 : [ OPT 2 : LDAH (Rt%),[(Rn%)] : B aftertest% : ] : =2
DEF FNstlU  : PROCregs3 : [ OPT 2 : STL  (Rt%),[(Rn%)] : B aftertest% : ] : =4
DEF FNstlUb : PROCregs3 : [ OPT 2 : STLB (Rt%),[(Rn%)] : B aftertest% : ] : =1
DEF FNstlUh : PROCregs3 : [ OPT 2 : STLH (Rt%),[(Rn%)] : B aftertest% : ] : =2

DEF FNldrexP  : PROCregs3  : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c,#&1F : LDREX        (Rt%),       [(Rn%)] : MSR CPSR_c,#16 : B aftertest% : ] : =4
DEF FNldrexPb : PROCregs3  : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c,#&1F : LDREXB       (Rt%),       [(Rn%)] : MSR CPSR_c,#16 : B aftertest% : ] : =1
DEF FNldrexPd : PROCregs5  : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c,#&1F : LDREXD       (Rt%),(Rt2%),[(Rn%)] : MSR CPSR_c,#16 : B aftertest% : ] : =8
DEF FNldrexPh : PROCregs3  : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c,#&1F : LDREXH       (Rt%),       [(Rn%)] : MSR CPSR_c,#16 : B aftertest% : ] : =2
DEF FNstrexP  : PROCregs26 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c,#&1F : STREX  (Rd%),(Rt%),       [(Rn%)] : MSR CPSR_c,#16 : B aftertest% : ] : =4
DEF FNstrexPb : PROCregs26 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c,#&1F : STREXB (Rd%),(Rt%),       [(Rn%)] : MSR CPSR_c,#16 : B aftertest% : ] : =1
DEF FNstrexPd : PROCregs27 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c,#&1F : STREXD (Rd%),(Rt%),(Rt2%),[(Rn%)] : MSR CPSR_c,#16 : B aftertest% : ] : =8
DEF FNstrexPh : PROCregs26 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c,#&1F : STREXH (Rd%),(Rt%),       [(Rn%)] : MSR CPSR_c,#16 : B aftertest% : ] : =2

DEF FNldaexP  : PROCregs3  : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c,#&1F : LDAEX        (Rt%),       [(Rn%)] : MSR CPSR_c,#16 : B aftertest% : ] : =4
DEF FNldaexPb : PROCregs3  : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c,#&1F : LDAEXB       (Rt%),       [(Rn%)] : MSR CPSR_c,#16 : B aftertest% : ] : =1
DEF FNldaexPd : PROCregs5  : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c,#&1F : LDAEXD       (Rt%),(Rt2%),[(Rn%)] : MSR CPSR_c,#16 : B aftertest% : ] : =8
DEF FNldaexPh : PROCregs3  : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c,#&1F : LDAEXH       (Rt%),       [(Rn%)] : MSR CPSR_c,#16 : B aftertest% : ] : =2
DEF FNstlexP  : PROCregs26 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c,#&1F : STLEX  (Rd%),(Rt%),       [(Rn%)] : MSR CPSR_c,#16 : B aftertest% : ] : =4
DEF FNstlexPb : PROCregs26 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c,#&1F : STLEXB (Rd%),(Rt%),       [(Rn%)] : MSR CPSR_c,#16 : B aftertest% : ] : =1
DEF FNstlexPd : PROCregs27 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c,#&1F : STLEXD (Rd%),(Rt%),(Rt2%),[(Rn%)] : MSR CPSR_c,#16 : B aftertest% : ] : =8
DEF FNstlexPh : PROCregs26 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c,#&1F : STLEXH (Rd%),(Rt%),       [(Rn%)] : MSR CPSR_c,#16 : B aftertest% : ] : =2

DEF FNldaP  : PROCregs3 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c,#&1F : LDA  (Rt%),[(Rn%)] : MSR CPSR_c,#16 : B aftertest% : ] : =4
DEF FNldaPb : PROCregs3 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c,#&1F : LDAB (Rt%),[(Rn%)] : MSR CPSR_c,#16 : B aftertest% : ] : =1
DEF FNldaPh : PROCregs3 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c,#&1F : LDAH (Rt%),[(Rn%)] : MSR CPSR_c,#16 : B aftertest% : ] : =2
DEF FNstlP  : PROCregs3 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c,#&1F : STL  (Rt%),[(Rn%)] : MSR CPSR_c,#16 : B aftertest% : ] : =4
DEF FNstlPb : PROCregs3 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c,#&1F : STLB (Rt%),[(Rn%)] : MSR CPSR_c,#16 : B aftertest% : ] : =1
DEF FNstlPh : PROCregs3 : [ OPT 2 : SWI "OS_EnterOS" : MSR CPSR_c,#&1F : STLH (Rt%),[(Rn%)] : MSR CPSR_c,#16 : B aftertest% : ] : =2

REM FPA

DEF FNldfs_pre  : PROCregs28( 4,1) : [ OPT 2 : LDFS F0,[(Rn%), #imm%]  : B aftertest% : ] : =4
DEF FNldfd_pre  : PROCregs28( 8,1) : [ OPT 2 : LDFD F0,[(Rn%), #imm%]  : B aftertest% : ] : =8
DEF FNldfe_pre  : PROCregs28(12,1) : [ OPT 2 : LDFE F0,[(Rn%), #imm%]  : B aftertest% : ] : =12
DEF FNldfp_pre  : PROCregs28(16,1) : [ OPT 2 : LDFP F0,[(Rn%), #imm%]  : B aftertest% : ] : =16
DEF FNldfs_wb   : PROCregs29       : [ OPT 2 : LDFS F0,[(Rn%), #imm%]! : B aftertest% : ] : =4
DEF FNldfd_wb   : PROCregs29       : [ OPT 2 : LDFD F0,[(Rn%), #imm%]! : B aftertest% : ] : =8
DEF FNldfe_wb   : PROCregs29       : [ OPT 2 : LDFE F0,[(Rn%), #imm%]! : B aftertest% : ] : =12
DEF FNldfp_wb   : PROCregs29       : [ OPT 2 : LDFP F0,[(Rn%), #imm%]! : B aftertest% : ] : =16
DEF FNldfs_post : PROCregs29       : [ OPT 2 : LDFS F0,[(Rn%)],#imm%   : B aftertest% : ] : =4
DEF FNldfd_post : PROCregs29       : [ OPT 2 : LDFD F0,[(Rn%)],#imm%   : B aftertest% : ] : =8
DEF FNldfe_post : PROCregs29       : [ OPT 2 : LDFE F0,[(Rn%)],#imm%   : B aftertest% : ] : =12
DEF FNldfp_post : PROCregs29       : [ OPT 2 : LDFP F0,[(Rn%)],#imm%   : B aftertest% : ] : =16

DEF FNstfs_pre  : PROCregs28( 4,1) : [ OPT 2 : STFS F0,[(Rn%), #imm%]  : B aftertest% : ] : =4
DEF FNstfd_pre  : PROCregs28( 8,1) : [ OPT 2 : STFD F0,[(Rn%), #imm%]  : B aftertest% : ] : =8
DEF FNstfe_pre  : PROCregs28(12,1) : [ OPT 2 : STFE F0,[(Rn%), #imm%]  : B aftertest% : ] : =12
DEF FNstfp_pre  : PROCregs28(16,1) : [ OPT 2 : STFP F0,[(Rn%), #imm%]  : B aftertest% : ] : =16
DEF FNstfs_wb   : PROCregs29       : [ OPT 2 : STFS F0,[(Rn%), #imm%]! : B aftertest% : ] : =4
DEF FNstfd_wb   : PROCregs29       : [ OPT 2 : STFD F0,[(Rn%), #imm%]! : B aftertest% : ] : =8
DEF FNstfe_wb   : PROCregs29       : [ OPT 2 : STFE F0,[(Rn%), #imm%]! : B aftertest% : ] : =12
DEF FNstfp_wb   : PROCregs29       : [ OPT 2 : STFP F0,[(Rn%), #imm%]! : B aftertest% : ] : =16
DEF FNstfs_post : PROCregs29       : [ OPT 2 : STFS F0,[(Rn%)],#imm%   : B aftertest% : ] : =4
DEF FNstfd_post : PROCregs29       : [ OPT 2 : STFD F0,[(Rn%)],#imm%   : B aftertest% : ] : =8
DEF FNstfe_post : PROCregs29       : [ OPT 2 : STFE F0,[(Rn%)],#imm%   : B aftertest% : ] : =12
DEF FNstfp_post : PROCregs29       : [ OPT 2 : STFP F0,[(Rn%)],#imm%   : B aftertest% : ] : =16

DEF FNlfm_pre  : PROCregs28(12,4) : [ OPT 2 : LFM F0,count%,[(Rn%), #imm%]  : B aftertest% : ] : =12*count%
DEF FNlfm_wb   : PROCregs29       : [ OPT 2 : LFM F0,count%,[(Rn%), #imm%]! : B aftertest% : ] : =12*count%
DEF FNlfm_post : PROCregs29       : [ OPT 2 : LFM F0,count%,[(Rn%)],#imm%   : B aftertest% : ] : =12*count%
DEF FNsfm_pre  : PROCregs28(12,4) : [ OPT 2 : SFM F0,count%,[(Rn%), #imm%]  : B aftertest% : ] : =12*count%
DEF FNsfm_wb   : PROCregs29       : [ OPT 2 : SFM F0,count%,[(Rn%), #imm%]! : B aftertest% : ] : =12*count%
DEF FNsfm_post : PROCregs29       : [ OPT 2 : SFM F0,count%,[(Rn%)],#imm%   : B aftertest% : ] : =12*count%

REM LDR/STR immediate
DEF PROCregs1
 Rt%=FNrnd(0,15)
 Rn%=FNrnd(0,14)
ENDPROC

REM LDR/STR immediate + wb or post index
DEF PROCregs2
 REPEAT
  Rt%=FNrnd(0,15)
  Rn%=FNrnd(0,14)
 UNTIL Rt%<>Rn%
ENDPROC

REM LDRB/STRB/LDRH/STRH/LDRSB/LDRSH immediate, LDREX, LDA/STL
DEF PROCregs3
 Rt%=FNrnd(0,14)
 Rn%=FNrnd(0,14)
ENDPROC

REM LDRB/STRB/LDRH/STRH/LDRSB/LDRSH immediate + wb or post index, or any LDR/STR unprivileged
DEF PROCregs4
 REPEAT
  Rt%=FNrnd(0,14)
  Rn%=FNrnd(0,14)
 UNTIL Rt%<>Rn%
ENDPROC

REM LDRD/STRD immediate, LDREXD
DEF PROCregs5
 Rt%=FNrnd(0,12) AND NOT 1
 Rt2%=Rt%+1
 Rn%=FNrnd(0,14)
ENDPROC

REM LDRD/STRD immediate + wb or post index
DEF PROCregs6
 REPEAT
  Rt%=FNrnd(0,12) AND NOT 1
  Rt2%=Rt%+1
  Rn%=FNrnd(0,14)
 UNTIL Rn%<>Rt% AND Rn%<>Rt2%
ENDPROC

REM LDM/STM
DEF PROCregs7
 Rt%=FNrnd(1,65535)
 Rn%=FNrnd(0,14)
ENDPROC

REM LDM/STM + wb
DEF PROCregs8
 REPEAT
  Rt%=FNrnd(1,65535)
  Rn%=FNrnd(0,14)
 UNTIL ((1<<Rn%) AND Rt%)=0
ENDPROC

REM LDR/STR literal
DEF PROCregs9(len%,range%)
 IF len%=8 THEN Rt%=FNrnd(0,12) AND NOT 1 : Rt2%=Rt%+1 ELSE IF len%=4 THEN Rt%=FNrnd(0,15) ELSE Rt%=FNrnd(0,14)
 Rn%=15
 REPEAT
  imm%=FNrnd(len%-1-range%,range%) AND NOT (len%-1)
 UNTIL imm%+len%+8<=0 OR imm%>=0
 REM For positive offsets, use the testcode at the end of the code page
 REM For negative offsets, use the testcode at the start of the code page
 IF imm%>=0 THEN PROCat(testcode_end%) ELSE PROCat(testcode_start%)
ENDPROC

REM LDM/STM user
DEF PROCregs10(limit%)
 Rt%=FNrnd(1,(2<<limit%)-1)
 Rn%=FNrnd(0,14)
 REM Completely avoid SP as base reg (mainly for safety)
 IF Rn%=13 THEN Rn%=14
 CASE RND(5) OF
  WHEN 1: testpsr%=&13 : REM SVC
  WHEN 2: testpsr%=&D1 : IF Rn%>=8 THEN Rn%=14 : REM FIQ, FIQ+IRQ disabled, avoid R8-R12 as base reg (just in case active FIQ handler is using it)
  WHEN 3: testpsr%=&92 : REM IRQ, IRQs disabled
  WHEN 4: testpsr%=&97 : REM ABT, IRQs disabled
   REM Can't use R14 as the base register, the abort will corrupt it
   IF Rn%=14 THEN Rn%=FNrnd(0,12)
  WHEN 5: testpsr%=&9B : REM UND, IRQs disabled
 ENDCASE
ENDPROC

REM LDR/STR register
DEF PROCregs11(op$)
 shift%=FNrnd(1,31)
 carry_in%=FNrnd(0,1)
 register_op$="FNldrstr_regop_"+op$
 REPEAT
  Rm%=FNrnd(0,14)
  Rt%=FNrnd(0,15)
  Rn%=FNrnd(0,14) : REM Could technically include R15 here, but testing would be tricky (we rely on being able to adjust Rn to get the right target address)
 UNTIL Rm%<>Rn% : REM Testing Rm=Rn will be tricky (will be hard to control the target address)
ENDPROC

REM LDR/STR register + wb or post index
DEF PROCregs12(op$)
 shift%=FNrnd(1,31)
 carry_in%=FNrnd(0,1)
 register_op$="FNldrstr_regop_"+op$
 REPEAT
  Rm%=FNrnd(0,14)
  Rt%=FNrnd(0,15)
  Rn%=FNrnd(0,14)
 UNTIL Rn%<>Rt% AND Rm%<>Rn% : REM Testing Rm=Rn will be tricky (will be hard to control the target address)
ENDPROC

REM LDRB/STRB/LDRH/STRH/LDRSB/LDRSH register
DEF PROCregs13(op$)
 shift%=FNrnd(1,31)
 carry_in%=FNrnd(0,1)
 register_op$="FNldrstr_regop_"+op$
 REPEAT
  Rm%=FNrnd(0,14)
  Rt%=FNrnd(0,14)
  Rn%=FNrnd(0,14) : REM Could technically include R15 here, but testing would be tricky (we rely on being able to adjust Rn to get the right target address)
 UNTIL Rm%<>Rn% : REM Testing Rm=Rn will be tricky (will be hard to control the target address)
ENDPROC

REM LDRB/STRB/LDRH/STRH/LDRSB/LDRSH register + wb or post index, or LDR/STR unprivileged register
DEF PROCregs14(op$)
 shift%=FNrnd(1,31)
 carry_in%=FNrnd(0,1)
 register_op$="FNldrstr_regop_"+op$
 REPEAT
  Rm%=FNrnd(0,14)
  Rt%=FNrnd(0,14)
  Rn%=FNrnd(0,14)
 UNTIL Rn%<>Rt% AND Rm%<>Rn% : REM Testing Rm=Rn will be tricky (will be hard to control the target address)
ENDPROC

REM LDRD register
DEF PROCregs15(op$)
 shift%=FNrnd(1,31)
 carry_in%=FNrnd(0,1)
 register_op$="FNldrstr_regop_"+op$
 REPEAT
  Rm%=FNrnd(0,14)
  Rt%=FNrnd(0,12) AND NOT 1
  Rt2%=Rt%+1
  Rn%=FNrnd(0,14) : REM Could technically include R15 here, but testing would be tricky (we rely on being able to adjust Rn to get the right target address)
 UNTIL Rm%<>Rt% AND Rm%<>Rt2% AND Rm%<>Rn% : REM Testing Rm=Rn will be tricky (will be hard to control the target address)
ENDPROC

REM LDRD register + wb or post index
DEF PROCregs16(op$)
 shift%=FNrnd(1,31)
 carry_in%=FNrnd(0,1)
 register_op$="FNldrstr_regop_"+op$
 REPEAT
  Rm%=FNrnd(0,14)
  Rt%=FNrnd(0,12) AND NOT 1
  Rt2%=Rt%+1
  Rn%=FNrnd(0,14)
 UNTIL Rm%<>Rt% AND Rm%<>Rt2% AND Rn%<>Rt% AND Rn%<>Rt2% AND Rm%<>Rn% : REM Testing Rm=Rn will be tricky (will be hard to control the target address)
ENDPROC

REM STRD register
DEF PROCregs17(op$)
 shift%=FNrnd(1,31)
 carry_in%=FNrnd(0,1)
 register_op$="FNldrstr_regop_"+op$
 REPEAT
  Rm%=FNrnd(0,14)
  Rt%=FNrnd(0,12) AND NOT 1
  Rt2%=Rt%+1
  Rn%=FNrnd(0,14) : REM Could technically include R15 here, but testing would be tricky (we rely on being able to adjust Rn to get the right target address)
 UNTIL Rm%<>Rn% : REM Testing Rm=Rn will be tricky (will be hard to control the target address)
ENDPROC

REM STRD register + wb or post index
DEF PROCregs18(op$)
 shift%=FNrnd(1,31)
 carry_in%=FNrnd(0,1)
 register_op$="FNldrstr_regop_"+op$
 REPEAT
  Rm%=FNrnd(0,14)
  Rt%=FNrnd(0,12) AND NOT 1
  Rt2%=Rt%+1
  Rn%=FNrnd(0,14)
 UNTIL Rn%<>Rt% AND Rn%<>Rt2% AND Rm%<>Rn% : REM Testing Rm=Rn wil be tricky (will be hard to control the target address)
ENDPROC

REM VLDR/VSTR literal
DEF PROCregs19(len%,range%)
 Vd%=FNrnd(0,max_dregs%-1)
 Rn%=15
 REPEAT
  imm%=FNrnd(len%-1-range%,range%)<<2
 UNTIL imm%+len%+8<=0 OR imm%>=0
 REM For positive offsets, use the testcode at the end of the code page
 REM For negative offsets, use the testcode at the start of the code page
 IF imm%>=0 THEN PROCat(testcode_end%) ELSE PROCat(testcode_start%)
ENDPROC

REM VDLMIA/VSTMIA
DEF PROCregs20(double%)
 Rn%=FNrnd(0,14) : REM TODO PC
 Vd%=FNrnd(0,max_dregs%-1)
 Vd2%=FNrnd(Vd%,max_dregs%-1)
 IF Vd2%-Vd%>15 THEN Vd2%=Vd%+15
 REM Calculate the bitfield to merge into the LDM/STM instruction
 IF double% THEN Vx%=((Vd2%-Vd%)<<1) + ((Vd% AND &F)<<12) + ((Vd%>>4)<<22) ELSE Vx%=(Vd2%-Vd%) + ((Vd%>>1)<<12) + ((Vd% AND 1)<<22)
ENDPROC

REM VLD/VST
DEF PROCregs21(count%)
 REPEAT
  Rn%=FNrnd(0,14)
  Rm%=FNrnd(0,14)
 UNTIL (Rn%<>Rm%) AND (Rm%<>13)
 Vd%=FNrnd(0,max_dregs%-count%)
ENDPROC

REM VLD/VST single lane
DEF PROCregs22(count%,lanes%)
 REPEAT
  Rn%=FNrnd(0,14)
  Rm%=FNrnd(0,14)
 UNTIL (Rn%<>Rm%) AND (Rm%<>13)
 Vd%=FNrnd(0,max_dregs%-count%)
 imm%=FNrnd(0,lanes%)
ENDPROC

REM SWP, SWPB
DEF PROCregs23
 REPEAT
  Rn%=FNrnd(0,14)
  Rt%=FNrnd(0,14)
  Rt2%=FNrnd(0,14)
 UNTIL (Rn%<>Rt%) AND (Rn%<>Rt2%)
ENDPROC

REM Exception return LDM
DEF PROCregs24
 Rt%=FNrnd(0,8191)+32768 : REM R0-R12 are safe for our test code
 Rn%=FNrnd(0,12) : REM Likewise, only R0-R12 safe
ENDPROC

REM Exception return LDM + wb
DEF PROCregs25
 REPEAT
  Rt%=FNrnd(0,8191)+32768
  Rn%=FNrnd(0,12)
 UNTIL ((1<<Rn%) AND Rt%)=0
ENDPROC

REM STREX
DEF PROCregs26
 REPEAT
  Rt%=FNrnd(0,14)
  Rn%=FNrnd(0,14)
  Rd%=FNrnd(0,14)
 UNTIL (Rd%<>Rn%) AND (Rd%<>Rt%)
ENDPROC

REM STREXD
DEF PROCregs27
 REPEAT
  Rt%=FNrnd(0,12) AND NOT 1
  Rt2%=Rt%+1
  Rn%=FNrnd(0,14)
  Rd%=FNrnd(0,14)
 UNTIL (Rd%<>Rn%) AND (Rd%<>Rt%) AND (Rd%<>Rt2%)
ENDPROC

REM FPA, pre-indexed
DEF PROCregs28(len%,maxcount%)
 Rn%=FNrnd(0,15)
 count%=FNrnd(1,maxcount%)
 len%=len%*count%
 REPEAT
  imm%=FNrnd(len%-1-1023,1023) AND NOT 3
 UNTIL imm%+len%+8<=0 OR imm%>=0
 REM For positive offsets, use the testcode at the end of the code page
 REM For negative offsets, use the testcode at the start of the code page
 IF imm%>=0 THEN PROCat(testcode_end%) ELSE PROCat(testcode_start%)
ENDPROC

REM FPA, post-indexed or writeback
DEF PROCregs29
 Rn%=FNrnd(0,14)
 imm%=FNrnd(-255,255)<<2
 count%=FNrnd(1,4)
ENDPROC

DEF FNldrstr_regop_p    : =   (in_regs%!(Rm%*4))
DEF FNldrstr_regop_n    : =-  (in_regs%!(Rm%*4))
DEF FNldrstr_regop_pLSL : = ( (in_regs%!(Rm%*4)) <<  shift%)
DEF FNldrstr_regop_nLSL : =-( (in_regs%!(Rm%*4)) <<  shift%)
DEF FNldrstr_regop_pLSR : = ( (in_regs%!(Rm%*4)) >>> shift%)
DEF FNldrstr_regop_nLSR : =-( (in_regs%!(Rm%*4)) >>> shift%)
DEF FNldrstr_regop_pASR : = ( (in_regs%!(Rm%*4)) >>  shift%)
DEF FNldrstr_regop_nASR : =-( (in_regs%!(Rm%*4)) >>  shift%)
DEF FNldrstr_regop_pROR : = (((in_regs%!(Rm%*4)) >>> shift%) OR ((in_regs%!(Rm%*4)) << (32-shift%)))
DEF FNldrstr_regop_nROR : =-(((in_regs%!(Rm%*4)) >>> shift%) OR ((in_regs%!(Rm%*4)) << (32-shift%)))
DEF FNldrstr_regop_pRRX : = (((in_regs%!(Rm%*4)) >>> 1) OR (carry_in%<<31))
DEF FNldrstr_regop_nRRX : =-(((in_regs%!(Rm%*4)) >>> 1) OR (carry_in%<<31))

DEF FNimm(min%,max%)
imm%=FNrnd(min%,max%)
=imm%

DEF FNrnd(min%,max%)
IF min%=max% THEN =min%
=RND(max%-min%+1)+min%-1

DEF FNcheck_ldr(len%,wback%,post%,isreg%)
 signed%=(len%<0)
 len%=ABS(len%)
 REM Fill regs with garbage
 FOR A=0 TO 14 : in_regs%!(A*4)=RND : NEXT A
 REM Compute register offset value if needed
 IF isreg% THEN imm%=EVAL(register_op$)
 IF Rn%=15 THEN
  REM Compute location of the literal value
  offset%=(testcode%-da_base%) + 8 + imm%
 ELSE
  CASE len% OF
  WHEN 8:
   REM If configured for unaligned loads, LDRD/STRD can be word aligned, else must be doubleword aligned
   IF (sctlr% AND sctlr_u%)<>0 THEN align%=4 ELSE align%=8
  WHEN 4:
   REM Any kind of unaligned PC load is unpredictable, stick to aligned only
   IF (sctlr% AND sctlr_a%)<>0 OR Rt%=15 THEN align%=len% ELSE align%=1
  WHEN 2:
   REM In rotated load mode, halfword accesses must still be halfword aligned
   IF (sctlr% AND sctlr_a%)<>0 OR (sctlr% AND sctlr_u%)=0 THEN align%=len% ELSE align%=1
  WHEN 1: align%=1
  ENDCASE
  REM Pick an address in the page
  offset%=FNrnd(0,4096-len%) AND NOT (align%-1)
  REM Reverse back to required input reg values
  in_regs%!(Rn%*4)=da_base%+offset%
  IF NOT post% THEN in_regs%!(Rn%*4)=(in_regs%!(Rn%*4)) - imm%
 ENDIF
 REM For LDR PC, set up to branch to a different location
 IF Rt%=15 THEN test_base%!(offset%+len%-4) = ldr_pc_success_code% : !ldr_pc_success%=0
 REM Get expected value
 PROCexpected(offset%,len%)
 REM Run test
 A%=carry_in%<<29
 CALL code%
 PROCexpectedcall(1,1,offset%,len%)
 IF wback% THEN in_regs%!(Rn%*4)=(in_regs%!(Rn%*4)) + imm%
 REM Load the value into the input regs, so we can compare against the output regs
 CASE len% OF
 WHEN 8: in_regs%!(Rt%*4)=!expected% : in_regs%!(Rt2%*4)=expected%!4
 WHEN 4: in_regs%!(Rt%*4)=!expected%
 WHEN 1: in_regs%!(Rt%*4)=?expected%
 WHEN 2: in_regs%!(Rt%*4)=?expected% : in_regs%?(Rt%*4+1)=expected%?1
 OTHERWISE PRINT "Bad length ";len% : PROCfailed
 ENDCASE
 IF signed% THEN in_regs%!(Rt%*4) = ((in_regs%!(Rt%*4))<<(32-len%*8))>>(32-len%*8)
 REM Check registers
 FOR A=0 TO 14
  IF out_regs%!(A*4)<>in_regs%!(A*4) THEN PRINT "Bad reg ";A;" in ";~(in_regs%!(A*4));" out ";~(out_regs%!(A*4)) : PROCfailed
 NEXT A
 REM For LDR PC, re-randomise the word we overwrote, and check for success
 IF Rt%=15 THEN test_base%!(offset%+len%-4) = RND : IF (!ldr_pc_success%)=0 THEN PRINT "LDR PC failed" : PROCfailed
=0

DEF FNcheck_str(len%,wback%,post%,isreg%)
 REM Fill regs with garbage
 FOR A=0 TO 14 : in_regs%!(A*4)=RND : NEXT A
 in_regs%!(15*4)=testcode%+str_pc_offset%
 REM Compute register offset value if needed
 IF isreg% THEN imm%=EVAL(register_op$)
 IF Rn%=15 THEN
  REM Compute location of the literal value
  offset%=(testcode%-da_base%) + 8 + imm%
 ELSE
  CASE len% OF
  WHEN 8:
   REM If configured for unaligned loads, LDRD/STRD can be word aligned, else must be doubleword aligned
   IF (sctlr% AND sctlr_u%)<>0 THEN align%=4 ELSE align%=8
  WHEN 4:
   IF (sctlr% AND sctlr_a%)<>0 THEN align%=len% ELSE align%=1
  WHEN 2:
   REM In rotated load mode, halfword accesses must still be halfword aligned
   IF (sctlr% AND sctlr_a%)<>0 OR (sctlr% AND sctlr_u%)=0 THEN align%=len% ELSE align%=1
  WHEN 1: align%=1
  ENDCASE
  REM Pick an address in the page
  offset%=FNrnd(0,4096-len%) AND NOT (align%-1)
  REM Reverse back to required input reg values
  in_regs%!(Rn%*4)=da_base%+offset%
  IF NOT post% THEN in_regs%!(Rn%*4)=(in_regs%!(Rn%*4)) - imm%
 ENDIF
 REM Run test
 A%=carry_in%<<29
 CALL code%
 PROCexpectedcall(1,0,offset%,len%)
 IF wback% THEN in_regs%!(Rn%*4)=(in_regs%!(Rn%*4)) + imm%
 REM Get expected value
 IF (sctlr% AND sctlr_u%)=0 AND len%=4 THEN offset%=offset% AND NOT 3
 PROCexpected(offset%,len%)
 REM Check against input registers
 CASE len% OF
 WHEN 8: ok%=(in_regs%!(Rt%*4)=!expected%) AND (in_regs%!(Rt2%*4)=expected%!4)
 WHEN 4: ok%=(in_regs%!(Rt%*4)=!expected%)
 WHEN 1: ok%=(in_regs%?(Rt%*4)=?expected%)
 WHEN 2: ok%=(in_regs%?(Rt%*4)=?expected%) AND (in_regs%?(Rt%*4+1)=expected%?1)
 OTHERWISE PRINT "Bad length ";len% : PROCfailed
 ENDCASE
 IF ok%=FALSE THEN PRINT "Bad memory" : PROCfailed
 REM Check registers
 FOR A=0 TO 14
  IF out_regs%!(A*4)<>in_regs%!(A*4) THEN PRINT "Bad reg ";A;" in ";~(in_regs%!(A*4));" out ";~(out_regs%!(A*4)) : PROCfailed
 NEXT A
=0

DEF FNcheck_ldm(privflag%,inc%,after%,wback%)
 len%=0
 FOR A=0 TO 15 : IF Rt% AND (1<<A) THEN len%+=4
 NEXT A
 REM Fill regs with garbage
 FOR A=0 TO 14 : in_regs%!(A*4)=RND : NEXT A
 REM Pick an address in the page
 offset%=FNrnd(0,4096-len%) AND NOT 3
 REM Reverse back to required input reg values
 in_regs%!(Rn%*4)=da_base%+offset%
 IF (sctlr% AND (sctlr_u%+sctlr_a%))=0 THEN in_regs%!(Rn%*4)+=FNrnd(0,3)
 IF after%=FALSE THEN in_regs%!(Rn%*4)-=4
 IF inc%=FALSE THEN in_regs%!(Rn%*4)+=len%-4 : IF NOT after% THEN in_regs%!(Rn%*4)+=8
 REM For LDM PC, set up to branch to a different location
 IF Rt% AND &8000 THEN test_base%!(offset%+len%-4) = ldr_pc_success_code% : !ldr_pc_success%=0
 REM Get expected value
 PROCexpected(offset%,len%)
 REM Run test
 CALL code%
 PROCexpectedcall(1,privflag%+1,offset%,len%)
 IF wback% THEN
  IF inc% THEN in_regs%!(Rn%*4)+=len% ELSE in_regs%!(Rn%*4)-=len%
 ENDIF
 REM Load the value into the input regs, so we can compare against the output regs
 offset%=0
 FOR A=0 TO 14 : IF Rt% AND (1<<A) THEN in_regs%!(A*4)=expected%!offset% : offset%+=4
 NEXT A
 REM Check registers
 FOR A=0 TO 14
  IF out_regs%!(A*4)<>in_regs%!(A*4) THEN PRINT "Bad reg ";A;" in ";~(in_regs%!(A*4));" out ";~(out_regs%!(A*4)) : PROCfailed
 NEXT A
 REM For LDM PC, re-randomise the word we overwrote, and check for success
 IF Rt% AND &8000 THEN test_base%!(offset%+len%-4) = RND : IF (!ldr_pc_success%)=0 THEN PRINT "LDM PC failed" : PROCfailed
=0

DEF FNcheck_stm(privflag%,inc%,after%,wback%)
 len%=0
 FOR A=0 TO 15 : IF Rt% AND (1<<A) THEN len%+=4
 NEXT A
 REM Fill regs with garbage
 FOR A=0 TO 14 : in_regs%!(A*4)=RND : NEXT A
 in_regs%!(15*4)=X%+str_pc_offset%
 REM Pick an address in the page
 offset%=FNrnd(0,4096-len%) AND NOT 3
 REM Reverse back to required input reg values
 in_regs%!(Rn%*4)=da_base%+offset%
 IF (sctlr% AND (sctlr_u%+sctlr_a%))=0 THEN in_regs%!(Rn%*4)+=FNrnd(0,3)
 IF after%=FALSE THEN in_regs%!(Rn%*4)-=4
 IF inc%=FALSE THEN in_regs%!(Rn%*4)+=len%-4 : IF NOT after% THEN in_regs%!(Rn%*4)+=8
 REM Run test
 CALL code%
 PROCexpectedcall(1,privflag%,offset%,len%)
 IF wback% THEN
  IF inc% THEN in_regs%!(Rn%*4)+=len% ELSE in_regs%!(Rn%*4)-=len%
 ENDIF
 REM Get expected value
 PROCexpected(offset%,len%)
 REM Check against input registers
 offset%=0
 FOR A=0 TO 15
  IF Rt% AND (1<<A) THEN
   IF (in_regs%!(A*4))<>(expected%!offset%) THEN PRINT "Bad memory offset ";~offset%;" expected ";~(in_regs%!(A*4));" actual ";~(expected%!offset%) : PROCfailed ELSE offset%+=4
  ENDIF
 NEXT A
 REM Check registers
 FOR A=0 TO 14
  IF out_regs%!(A*4)<>in_regs%!(A*4) THEN PRINT "Bad reg ";A;" in ";~(in_regs%!(A*4));" out ";~(out_regs%!(A*4)) : PROCfailed
 NEXT A
=0

DEF FNcheck_vldr(len%)
 REM Fill regs with garbage
 FOR A=0 TO 14 : in_regs%!(A*4)=RND : NEXT A
 FOR A=0 TO max_dregs%*2-1 : in_vfp%!(A*4)=RND : NEXT A
 IF Rn%=15 THEN
  REM Compute location of the literal value
  offset%=(testcode%-da_base%) + 8 + imm%
 ELSE
  REM Pick an address in the page
  offset%=FNrnd(0,4096-len%) AND NOT 3
  REM Reverse back to required input reg values
  in_regs%!(Rn%*4)=da_base%+offset%-imm%
  IF (sctlr% AND (sctlr_a%+sctlr_u%))=0 THEN in_regs%!(Rn%*4)+=FNrnd(0,3)
 ENDIF
 REM Get expected value
 PROCexpected(offset%,len%)
 REM Run test
 CALL vfp_code%
 PROCexpectedcall(1,1,offset%,len%)
 REM Load the value into the input regs, so we can compare against the output regs
 CASE len% OF
 WHEN 8: in_vfp%!(Vd%*8)=!expected% : in_vfp%!(Vd%*8+4)=expected%!4
 WHEN 4: in_vfp%!(Vd%*4)=!expected%
 OTHERWISE PRINT "Bad length ";len% : PROCfailed
 ENDCASE
 REM Check registers
 FOR A=0 TO 14
  IF out_regs%!(A*4)<>in_regs%!(A*4) THEN PRINT "Bad reg ";A;" in ";~(in_regs%!(A*4));" out ";~(out_regs%!(A*4)) : PROCfailed
 NEXT A
 FOR A=0 TO max_dregs%*2-1
  IF out_vfp%!(A*4)<>in_vfp%!(A*4) THEN PRINT "Bad reg S";A;" in ";~(in_vfp%!(A*4));" out ";~(out_vfp%!(A*4)) : PROCfailed
 NEXT A
=0

DEF FNcheck_vstr(len%)
 REM Fill regs with garbage
 FOR A=0 TO 14 : in_regs%!(A*4)=RND : NEXT A
 FOR A=0 TO max_dregs%*2-1 : in_vfp%!(A*4)=RND : NEXT A
 IF Rn%=15 THEN
  REM Compute location of the literal value
  offset%=(testcode%-da_base%) + 8 + imm%
 ELSE
  REM Pick an address in the page
  offset%=FNrnd(0,4096-len%) AND NOT 3
  REM Reverse back to required input reg values
  in_regs%!(Rn%*4)=da_base%+offset%-imm%
  IF (sctlr% AND (sctlr_a%+sctlr_u%))=0 THEN in_regs%!(Rn%*4)+=FNrnd(0,3)
 ENDIF
 REM Run test
 CALL vfp_code%
 PROCexpectedcall(1,0,offset%,len%)
 REM Get expected value
 PROCexpected(offset%,len%)
 REM Check against input registers
 CASE len% OF
 WHEN 8: ok%=(in_vfp%!(Vd%*8)=!expected%) AND (in_vfp%!(Vd%*8+4)=expected%!4)
 WHEN 4: ok%=(in_vfp%!(Vd%*4)=!expected%)
 OTHERWISE PRINT "Bad length ";len% : PROCfailed
 ENDCASE
 IF ok%=FALSE THEN PRINT "Bad memory" : PROCfailed
 REM Check registers
 FOR A=0 TO 14
  IF out_regs%!(A*4)<>in_regs%!(A*4) THEN PRINT "Bad reg ";A;" in ";~(in_regs%!(A*4));" out ";~(out_regs%!(A*4)) : PROCfailed
 NEXT A
 FOR A=0 TO max_dregs%*2-1
  IF out_vfp%!(A*4)<>in_vfp%!(A*4) THEN PRINT "Bad reg S";A;" in ";~(in_vfp%!(A*4));" out ";~(out_vfp%!(A*4)) : PROCfailed
 NEXT A
=0

DEF FNcheck_vldm(regsize%,inc%,wback%)
 x%=regsize% AND 1
 regsize%=regsize% AND NOT 1
 len%=(Vd2%-Vd%+1)*regsize%+x%*4
 REM Fill regs with garbage
 FOR A=0 TO 14 : in_regs%!(A*4)=RND : NEXT A
 FOR A=0 TO max_dregs%*2-1 : in_vfp%!(A*4)=RND : NEXT A
 REM Pick an address in the page
 offset%=FNrnd(0,4096-len%) AND NOT 3
 REM Reverse back to required input reg values
 in_regs%!(Rn%*4)=da_base%+offset%
 IF (sctlr% AND (sctlr_a%+sctlr_u%))=0 THEN in_regs%!(Rn%*4)+=FNrnd(0,3)
 IF inc%=FALSE THEN in_regs%!(Rn%*4)+=len%
 REM Get expected value
 PROCexpected(offset%,len%)
 REM Run test
 CALL vfp_code%
 PROCexpectedcall(1,1,offset%,len%-x%*4)
 IF wback% THEN
  IF inc% THEN in_regs%!(Rn%*4)+=len% ELSE in_regs%!(Rn%*4)-=len%
 ENDIF
 REM Load the value into the input regs, so we can compare against the output regs
 FOR offset%=0 TO len%-4-x%*4 STEP 4 : in_vfp%!(Vd%*regsize%+offset%)=expected%!offset% : NEXT offset%
 REM Check registers
 FOR A=0 TO 14
  IF out_regs%!(A*4)<>in_regs%!(A*4) THEN PRINT "Bad reg ";A;" in ";~(in_regs%!(A*4));" out ";~(out_regs%!(A*4)) : PROCfailed
 NEXT A
 FOR A=0 TO max_dregs%*2-1
  IF out_vfp%!(A*4)<>in_vfp%!(A*4) THEN PRINT "Bad reg S";A;" in ";~(in_vfp%!(A*4));" out ";~(out_vfp%!(A*4)) : PROCfailed
 NEXT A
=0

DEF FNcheck_vstm(regsize%,inc%,wback%)
 x%=regsize% AND 1
 regsize%=regsize% AND NOT 1
 len%=(Vd2%-Vd%+1)*regsize%+x%*4
 REM Fill regs with garbage
 FOR A=0 TO 14 : in_regs%!(A*4)=RND : NEXT A
 FOR A=0 TO max_dregs%*2-1 : in_vfp%!(A*4)=RND : NEXT A
 REM Pick an address in the page
 offset%=FNrnd(0,4096-len%) AND NOT 3
 REM Reverse back to required input reg values
 in_regs%!(Rn%*4)=da_base%+offset%
 IF (sctlr% AND (sctlr_a%+sctlr_u%))=0 THEN in_regs%!(Rn%*4)+=FNrnd(0,3)
 IF inc%=FALSE THEN in_regs%!(Rn%*4)+=len%
 REM Run test
 CALL vfp_code%
 PROCexpectedcall(1,0,offset%,len%-x%*4)
 IF wback% THEN
  IF inc% THEN in_regs%!(Rn%*4)+=len% ELSE in_regs%!(Rn%*4)-=len%
 ENDIF
 REM Get expected value
 PROCexpected(offset%,len%)
 REM Check against input registers
 FOR offset%=0 TO len%-4-x%*4 STEP 4
  IF (in_vfp%!(Vd%*regsize%+offset%))<>(expected%!offset%) THEN PRINT "Bad memory" : PROCfailed
 NEXT offset%
 REM Check registers
 FOR A=0 TO 14
  IF out_regs%!(A*4)<>in_regs%!(A*4) THEN PRINT "Bad reg ";A;" in ";~(in_regs%!(A*4));" out ";~(out_regs%!(A*4)) : PROCfailed
 NEXT A
 FOR A=0 TO max_dregs%*2-1
  IF out_vfp%!(A*4)<>in_vfp%!(A*4) THEN PRINT "Bad reg S";A;" in ";~(in_vfp%!(A*4));" out ";~(out_vfp%!(A*4)) : PROCfailed
 NEXT A
=0

DEF FNcheck_vldst(test$)
 REM Decode the test name
 load%=(LEFT$(test$,5)="FNvld")
 align$=MID$(test$,18,3)
 IF align$="xxx" THEN align%=1 ELSE align%=VAL(align$)>>3
 len%=EVAL(test$)

 REM Ensure aligned to element size if alignment faults enabled
 IF sctlr% AND sctlr_a% THEN
  esize%=EVAL(MID$(test$,13,2))>>3
  IF esize%>align% THEN align%=esize%
 ENDIF

 REM Pick an address in the page
 offset%=FNrnd(0,4096-len%) AND NOT (align%-1)

 REM Fill VFP regs with garbage
 FOR A=0 TO max_dregs%*2-1 : in_vfp%!(A*4)=RND : NEXT A
 REM Fill scratch area with garbage
 FOR A=0 TO 28 STEP 4 : vfp_scratch%!A=RND : NEXT A
 IF load% THEN
  REM Make sure vfp_scratch is populated with the expected value
  PROCexpected(offset%,len%)
  FOR A=0 TO len%-1 : vfp_scratch%?A=expected%?A : NEXT A
 ENDIF

 REM Run once, targeting vfp_scratch%
 in_regs%!(Rn%*4)=vfp_scratch%
 CALL vfp_code%

 REM Copy VFP regs to out_vfp2
 FOR A=0 TO max_dregs%*8-4 STEP 4 : out_vfp2%!A = out_vfp%!A : NEXT A

 REM Fill regs with garbage
 FOR A=0 TO 14 : in_regs%!(A*4)=RND : NEXT A
 REM Run real test
 in_regs%!(Rn%*4)=da_base%+offset%
 CALL vfp_code%
 IF load% THEN PROCexpectedcall(1,1,offset%,len%) ELSE PROCexpectedcall(1,0,offset%,len%)

 REM Apply writeback to in_regs%
 CASE RIGHT$(test$,3) OF
 WHEN "_wb" : wback%=len%
 WHEN "_rm" : wback%=(in_regs%!(Rm%*4))
 OTHERWISE : wback%=0
 ENDCASE
 in_regs%!(Rn%*4)+=wback%

 REM Check registers
 FOR A=0 TO 14
  IF out_regs%!(A*4)<>in_regs%!(A*4) THEN PRINT "Bad reg ";A;" in ";~(in_regs%!(A*4));" out ";~(out_regs%!(A*4)) : PROCfailed
 NEXT A
 FOR A=0 TO max_dregs%*2-1
  IF out_vfp%!(A*4)<>out_vfp2%!(A*4) THEN PRINT "Bad reg S";A;" expected ";~(out_vfp2%!(A*4));" got ";~(out_vfp%!(A*4)) : PROCfailed
 NEXT A

 REM Check memory
 IF NOT load% THEN
  PROCexpected(offset%,len%)
  FOR offset%=0 TO len%-1
   IF (vfp_scratch%?offset%)<>(expected%?offset%) THEN PRINT "Bad memory" : PROCfailed
  NEXT offset%
 ENDIF

=0

DEF FNcheck_swp(len%)
 REM Fill regs with garbage
 FOR A=0 TO 14 : in_regs%!(A*4)=RND : NEXT A
 REM Pick an address in the page
 offset%=FNrnd(0,4096-len%)
 REM Only legacy rotated load mode allows unaligned pointers
 IF sctlr% AND (sctlr_a%+sctlr_u%) THEN offset%=offset% AND NOT (len%-1)
 REM Reverse back to required input reg values
 in_regs%!(Rn%*4)=da_base%+offset%
 REM Get expected value
 PROCexpected(offset%,len%)
 expected_write%=in_regs%!(Rt2%*4)
 REM Run test
 CALL code%
 PROCexpectedcall(2,0,offset%,len%)
 REM Load the value into the input regs, so we can compare against the output regs
 CASE len% OF
 WHEN 4: in_regs%!(Rt%*4)=!expected%
 WHEN 1: in_regs%!(Rt%*4)=?expected%
 OTHERWISE PRINT "Bad length ";len% : PROCfailed
 ENDCASE
 REM Check registers
 FOR A=0 TO 14
  IF out_regs%!(A*4)<>in_regs%!(A*4) THEN PRINT "Bad reg ";A;" in ";~(in_regs%!(A*4));" out ";~(out_regs%!(A*4)) : PROCfailed
 NEXT A
 REM Check memory was updated correctly
 PROCexpected(offset% AND NOT (len%-1),len%)
 CASE len% OF
 WHEN 4: ok%=(expected_write%=!expected%)
 WHEN 1: ok%=((expected_write% AND 255)=?expected%)
 OTHERWISE PRINT "Bad length ";len% : PROCfailed
 IF ok%=FALSE THEN PRINT "Bad memory" : PROCfailed
 ENDCASE
=0

DEF FNcheck_srs(ignore%,inc%,after%,wback%)
 REM Pick random LR value
 in_regs%!0=RND
 REM Pick random, valid SPSR value
 in_regs%!4=(RND AND &F0000003) OR 16
 REM Remainder is as if an STM
 Rt%=3
 Rn%=13
 len%=8
 REM Pick an address in the page
 offset%=FNrnd(0,4096-len%) AND NOT 3
 REM Reverse back to required input reg values
 in_regs%!(Rn%*4)=da_base%+offset%
 IF after%=FALSE THEN in_regs%!(Rn%*4)-=4
 IF inc%=FALSE THEN in_regs%!(Rn%*4)+=len%-4 : IF NOT after% THEN in_regs%!(Rn%*4)+=8
 REM Run test
 CALL code%
 PROCexpectedcall(1,16,offset%,len%)
 IF wback% THEN
  IF inc% THEN in_regs%!(Rn%*4)+=len% ELSE in_regs%!(Rn%*4)-=len%
 ENDIF
 REM Get expected value
 PROCexpected(offset%,len%)
 REM Check against input registers
 offset%=0
 FOR A=0 TO 15
  IF Rt% AND (1<<A) THEN
   IF (in_regs%!(A*4))<>(expected%!offset%) THEN PRINT "Bad memory offset ";~offset%;" expected ";~(in_regs%!(A*4));" actual ";~(expected%!offset%) : PROCfailed ELSE offset%+=4
  ENDIF
 NEXT A
 REM Check registers
 FOR A=0 TO 14
  IF out_regs%!(A*4)<>in_regs%!(A*4) THEN PRINT "Bad reg ";A;" in ";~(in_regs%!(A*4));" out ";~(out_regs%!(A*4)) : PROCfailed
 NEXT A
=0

DEF FNcheck_rfe(ignore%,inc%,after%,wback%)
 len%=8
 REM Fill regs with garbage
 FOR A=0 TO 14 : in_regs%!(A*4)=RND : NEXT A
 REM Pick an address in the page
 offset%=FNrnd(0,4096-len%) AND NOT 3
 REM Reverse back to required input reg values
 in_regs%!(Rn%*4)=da_base%+offset%
 IF after%=FALSE THEN in_regs%!(Rn%*4)-=4
 IF inc%=FALSE THEN in_regs%!(Rn%*4)+=len%-4 : IF NOT after% THEN in_regs%!(Rn%*4)+=8
 REM Prepeare suitable PC & PSR values for loading
 test_base%!(offset%) = ldr_pc_success_code% : !ldr_pc_success%=0
 test_base%!(offset%+4) = (RND AND &F0000000) OR 16
 REM Run test
 CALL code%
 PROCexpectedcall(1,17,offset%,len%)
 IF wback% THEN
  IF inc% THEN in_regs%!(Rn%*4)+=len% ELSE in_regs%!(Rn%*4)-=len%
 ENDIF
 REM Re-randomise the words we overwrote, and check for success
 IF (!ldr_pc_success%)=0 THEN PRINT "RFE failed" : PROCfailed
 IF !out_psr%<>test_base%!(offset%+4) THEN PRINT "RFE PSR failed, in ";~test_base%!(offset%+4);" out ";~!out_psr% : PROCfailed
 test_base%!(offset%) = RND
 test_base%!(offset%+4) = RND
=0

DEF FNcheck_ldrex(len%,flags%)
 REM Fill regs with garbage
 FOR A=0 TO 14 : in_regs%!(A*4)=RND : NEXT A
 REM Pick an address in the page
 offset%=FNrnd(0,4096-len%) AND NOT (len%-1)
 REM Reverse back to required input reg values
 in_regs%!(Rn%*4)=da_base%+offset%
 REM Run test
 CALL code%
 PROCexpectedcall(1,(flags%<<4)+2,offset%,len%)
 REM Get the expected value straight from the DA (page should be mapped in now)
 val%=da_base%+offset%
 REM Load the value into the input regs, so we can compare against the output regs
 CASE len% OF
 WHEN 8: in_regs%!(Rt%*4)=!val% : in_regs%!(Rt2%*4)=val%!4
 WHEN 4: in_regs%!(Rt%*4)=!val%
 WHEN 1: in_regs%!(Rt%*4)=?val%
 WHEN 2: in_regs%!(Rt%*4)=?val% : in_regs%?(Rt%*4+1)=val%?1
 OTHERWISE PRINT "Bad length ";len% : PROCfailed
 ENDCASE
 REM Check registers
 FOR A=0 TO 14
  IF out_regs%!(A*4)<>in_regs%!(A*4) THEN PRINT "Bad reg ";A;" in ";~(in_regs%!(A*4));" out ";~(out_regs%!(A*4)) : PROCfailed
 NEXT A
 REM Map out the page before going round again
 IF test_base%=buffer% THEN SYS "OS_DynamicArea",10,da_num%,da_base%,4096
=0

DEF FNcheck_strex(len%,flags%)
 REM Fill regs with garbage
 FOR A=0 TO 14 : in_regs%!(A*4)=RND : NEXT A
 REM Pick an address in the page
 offset%=FNrnd(0,4096-len%) AND NOT (len%-1)
 REM Reverse back to required input reg values
 in_regs%!(Rn%*4)=da_base%+offset%
 REM Run test
 CALL code%
 REM If the exclusive monitor state is such that the STREX will fail, and it's targeting invalid memory, it's implementation-defined whether it will trigger a data abort
 REM i.e. AbortTrap might not be invoked
 IF !call_count%<>0 THEN
  PROCexpectedcall(1,(flags%<<4)+2,offset%,len%)
  REM Map out the page before going round again
  IF test_base%=buffer% THEN SYS "OS_DynamicArea",10,da_num%,da_base%,4096
 ENDIF
 REM The store operation should have failed
 in_regs%!(Rd%*4)=1
 REM Check registers
 FOR A=0 TO 14
  IF out_regs%!(A*4)<>in_regs%!(A*4) THEN PRINT "Bad reg ";A;" in ";~(in_regs%!(A*4));" out ";~(out_regs%!(A*4)) : PROCfailed
 NEXT A
=0

DEF FNcheck_stl(len%,flags%)
 REM Fill regs with garbage
 FOR A=0 TO 14 : in_regs%!(A*4)=RND : NEXT A
 REM Pick an address in the page
 offset%=FNrnd(0,4096-len%) AND NOT (len%-1)
 REM Reverse back to required input reg values
 in_regs%!(Rn%*4)=da_base%+offset%
 REM Run test
 CALL code%
 PROCexpectedcall(1,(flags%<<4)+2,offset%,len%)
 REM Get the expected value straight from the DA (page should be mapped in now)
 val%=da_base%+offset%
 REM Check against input registers
 CASE len% OF
 WHEN 8: ok%=(in_regs%!(Rt%*4)=!val%) AND (in_regs%!(Rt2%*4)=val%!4)
 WHEN 4: ok%=(in_regs%!(Rt%*4)=!val%)
 WHEN 1: ok%=(in_regs%?(Rt%*4)=?val%)
 WHEN 2: ok%=(in_regs%?(Rt%*4)=?val%) AND (in_regs%?(Rt%*4+1)=val%?1)
 OTHERWISE PRINT "Bad length ";len% : PROCfailed
 ENDCASE
 IF ok%=FALSE THEN PRINT "Bad memory" : PROCfailed
 REM Check registers
 FOR A=0 TO 14
  IF out_regs%!(A*4)<>in_regs%!(A*4) THEN PRINT "Bad reg ";A;" in ";~(in_regs%!(A*4));" out ";~(out_regs%!(A*4)) : PROCfailed
 NEXT A
 REM Map out the page before going round again
 IF test_base%=buffer% THEN SYS "OS_DynamicArea",10,da_num%,da_base%,4096
=0

DEF FNcheck_fpa(len%,wback%,post%,flags%)
 REM Fill regs with garbage
 FOR A=0 TO 14 : in_regs%!(A*4)=RND : NEXT A
 IF Rn%=15 THEN
  REM Compute location of the literal value
  offset%=(testcode%-da_base%) + 8 + imm%
 ELSE
  REM Pick an address in the page
  offset%=FNrnd(0,4096-len%) AND NOT 3
  REM Reverse back to required input reg values
  in_regs%!(Rn%*4)=da_base%+offset%
  IF NOT post% THEN in_regs%!(Rn%*4)=(in_regs%!(Rn%*4)) - imm%
 ENDIF
 REM Run test
 CALL fpa_code%
 REM Check for the expected AbortTrap calls
 REM Note that we don't check that memory or the FPA registers were updated correctly, since AbortTrap simply re-executes the instruction after the memory is mapped in
 IF test_base%=buffer% THEN
  IF have_fpa% AND len%<>16 THEN
   REM Expect FPA hardware to trigger the abort, resulting in an AbortTrap MemMap request
   PROCexpectedcall(1,(flags%<<4)+2,offset%,len%)
  ELSE
   REM Expect FPEmulator to trigger the abort, resulting in a sequence of reads/writes totaling len% bytes
   actual_len%=(!last_R3%)*(!call_count%)
   REM P/EP is treated as if length 16, fix up to actual length here
   IF len%=16 THEN len%=ep_len%
   IF actual_len%<>len% THEN PRINT "Bad AbortTrap length: expected ";len%;" got ";actual_len% : PROCfailed
   IF !last_R0%<>(flags%>>2) THEN PRINT "Bad AbortTrap flags: expected ";(flags%>>2);" got ";!last_R0% : PROCfailed
   !call_count%=0
  ENDIF
 ENDIF
 IF wback% THEN in_regs%!(Rn%*4)=(in_regs%!(Rn%*4)) + imm%
 REM Check registers
 FOR A=0 TO 14
  IF out_regs%!(A*4)<>in_regs%!(A*4) THEN PRINT "Bad reg ";A;" in ";~(in_regs%!(A*4));" out ";~(out_regs%!(A*4)) : PROCfailed
 NEXT A
 REM Map out the page before going round again
 IF test_base%=buffer% THEN SYS "OS_DynamicArea",10,da_num%,da_base%+(offset% AND NOT 4095),4096
=0

DEF PROCendtest
ENDPROC

DEF PROCfailed
 OSCLI("*memoryi "+STR$~testcode%+" "+STR$~P%)
 PROCend(1)
ENDPROC

DEF PROCend(E%)
 PROCendtest
 IF at_registered% THEN
  PROClast
  at_registered%=FALSE
  SYS swi$,1,da_base%,da_base%+da_size%,handler%,wp%
 ENDIF
 IF da_num%<>0 THEN SYS "OS_DynamicArea",1,da_num% : da_num%=0
 IF vfp_context%<>0 THEN SYS "VFPSupport_DestroyContext",vfp_context%,vfp_context_old% : vfp_context%=0
 SYS "OS_Module",7,,rma%
 A%=orig_sctlr% : CALL write_sctlr%
 IF E% THEN ERROR EXT 0,"Failed"
 PRINT "Success"
 END
ENDPROC

DEF PROCat(val%)
 testcode%=val%
 !testcode_ptr%=testcode%
 P%=testcode%
ENDPROC

DEF PROClast
 PRINT "last R0 ";~!last_R0%;" R1 ";~!last_R1%;" R2 ";~!last_R2%;" R3 ";~!last_R3%;" PSR ";~!last_PSR%;" R12 ";~!last_R12%
ENDPROC

DEF PROCfill(base%,len%)
 WHILE len%>0
  !base%=RND
  base%+=4
  len%-=4
 ENDWHILE
ENDPROC

DEF FNexpected(addr%)
 IF addr%<da_base% OR addr%>=da_base%+da_size% THEN PRINT "Bad addr ";~addr% : PROCend(1)
 IF test_base%=da_base% THEN =?addr%
 addr%-=da_base%
=buffer%?addr%

DEF PROCexpected(offset%,len%)
 LOCAL p%
 IF (len%=4) AND (sctlr% AND sctlr_u%)=0 THEN
  len%=offset% AND 3
  offset%=offset% AND NOT 3
  FOR p%=0 TO 3
   expected%?p%=FNexpected(da_base%+offset%+((len%+p%) AND 3))
  NEXT p%
 ELSE
  WHILE len%>0
   len%-=1
   expected%?len%=FNexpected(da_base%+offset%+len%)
  ENDWHILE
 ENDIF
ENDPROC

DEF FNfeature(name$)
 LOCAL flag%
 SYS "OS_PlatformFeatures",34,EVAL("CPUFeature_"+name$) TO flag%
=flag%

DEF PROCexpectedcall(count%,flags%,offset%,len%)
 IF test_base%=da_base% THEN ENDPROC
 IF (len%=4) AND (sctlr% AND sctlr_u%)=0 THEN offset%=offset% AND NOT 3
 IF !call_count%<>count% THEN PRINT "Bad AbortTrap call count: expected ";count%;" got ";!call_count% : PROCfailed
 IF !last_R0%<>flags% OR !last_R2%<>(offset%+da_base%) OR !last_R3%<>len% OR !last_R12%<>wp% THEN PRINT "Bad AbortTrap call" : PRINT "Expected R0 ";STR$~flags%;" R2 ";STR$~(offset%+da_base%);" R3 ";STR$~len%;" R12 ";STR$~wp% : PROCfailed
 !call_count%=0
ENDPROC