; Copyright 2013 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
;     http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
        SUBT    VIDC List type 3 format => &.Hdr.VIDCList

OldOpt  SETA    {OPT}
        OPT     OptNoList+OptNoP1List

;
; format of a VIDC list type 3
;
                                ^       0
VIDCList3_Type                  #       4  ; must be '3'
VIDCList3_PixelDepth            #       4  ; Log2BPP
VIDCList3_HorizSyncWidth        #       4
VIDCList3_HorizBackPorch        #       4
VIDCList3_HorizLeftBorder       #       4
VIDCList3_HorizDisplaySize      #       4
VIDCList3_HorizRightBorder      #       4
VIDCList3_HorizFrontPorch       #       4
VIDCList3_VertiSyncWidth        #       4
VIDCList3_VertiBackPorch        #       4
VIDCList3_VertiTopBorder        #       4
VIDCList3_VertiDisplaySize      #       4
VIDCList3_VertiBottomBorder     #       4
VIDCList3_VertiFrontPorch       #       4
VIDCList3_PixelRate             #       4
VIDCList3_SyncPol               #       4  ; sync polarity/flag bits
VIDCList3_ControlList           #       0  ; possibly empty list of pairs of index,value words
;
; and VIDCList3 is terminated by a -1 word
;
; Indices in VIDCList3_ControlList
;
                                ^       1
ControlList_LCDMode             #       1
ControlList_LCDDualPanelMode    #       1
ControlList_LCDOffset0          #       1
ControlList_LCDOffset1          #       1
ControlList_HiResMode           #       1
ControlList_DACControl          #       1
ControlList_RGBPedestals        #       1
ControlList_ExternalRegister    #       1
ControlList_HClockSelect        #       1
ControlList_RClockFrequency     #       1
ControlList_DPMSState           #       1
                                #       1 ; Obsolete, see SyncPol b4
ControlList_OutputFormat        #       1
ControlList_ExtraBytes          #       1
ControlList_NColour             #       1
ControlList_ModeFlags           #       1
ControlList_InvalidReason       #       0

ControlList_Terminator          *      -1

; bits/flags in VIDCList3_SyncPol word:
;
SyncPol_InvertHSync        *  1   ; 0 = positive, 1 = negative
SyncPol_InvertVSync        *  2   ; 0 = positive, 1 = negative
SyncPol_InterlaceSpecified *  4   ; if set, interlace bit has been specified, else filled in by kernel
SyncPol_Interlace          *  8   ; 0 = progressive sync, 1 = interlace sync (either specified
                                  ; by service call claimant or filled in from *TV by kernel).
SyncPol_InterlaceFields    *  16  ; 0 = both fields are identical, 1 = adjust DMA so each field shows alternate rows

        OPT     OldOpt

        END