; Copyright 2015 Castle Technology Ltd ; ; Licensed under the Apache License, Version 2.0 (the "License"); ; you may not use this file except in compliance with the License. ; You may obtain a copy of the License at ; ; http://www.apache.org/licenses/LICENSE-2.0 ; ; Unless required by applicable law or agreed to in writing, software ; distributed under the License is distributed on an "AS IS" BASIS, ; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ; See the License for the specific language governing permissions and ; limitations under the License. ; ; Miscellaneous public definitions that aren't important enough to pollute ; Hdr:RISCOS or to have their own header ; OS_PlatformFeatures reason codes OSPlatformFeatures_ReadCodeFeatures * 0 OSPlatformFeatures_ReadProcessorVectors * 32 OSPlatformFeatures_ReadCacheInfo * 33 OSPlatformFeatures_ReadCPUFeatures * 34 OSPlatformFeatures_ReadClearExclusive * 35 ; These flags are returned by OS_PlatformFeatures 0 (Read code features) CPUFlag_SynchroniseCodeAreas * 1:SHL:0 ; Calls to OS_SynchroniseCodeAreas required CPUFlag_InterruptDelay * 1:SHL:1 ; Clearing then setting I bit immediately doesn't trigger IRQs CPUFlag_VectorReadException * 1:SHL:2 ; 26-bit reads of hardware vectors abort CPUFlag_StorePCplus8 * 1:SHL:3 ; Stores of R15 store PC+8 rather than PC+12 CPUFlag_BaseRestored * 1:SHL:4 ; Base Restored abort model rather than Base Updated CPUFlag_SplitCache * 1:SHL:5 ; CPU has separate I and D caches CPUFlag_32bitOS * 1:SHL:6 ; OS is 32-bit CPUFlag_No26bitMode * 1:SHL:7 ; CPU does not support 26-bit modes CPUFlag_LongMul * 1:SHL:8 ; Has M extensions (UMULL etc) CPUFlag_Thumb * 1:SHL:9 ; Supports Thumb CPUFlag_DSP * 1:SHL:10 ; Has E extensions (QADD etc) CPUFlag_NoSWP * 1:SHL:11 ; CPU does not support SWP/SWPB CPUFlag_LoadStoreEx * 1:SHL:12 ; Has LDR/STREX CPUFlag_LoadStoreClearExSizes * 1:SHL:13 ; Has CLREX and LDR/STREX[B|H|D] CPUFlag_NoDCacheDisable * 1:SHL:14 ; D-cache can't be disabled safely & OS_MMUControl won't allow it CPUFlag_ExtendedPages * 1:SHL:15 ; Supports extended small page L2 descriptors CPUFlag_NoWBDrain * 1:SHL:16 ; CPU does not support Drain Write Buffer instruction CPUFlag_AbortRestartBroken * 1:SHL:17 ; Aborts do not correctly follow documented abort model CPUFlag_XScale * 1:SHL:18 ; it's an XScale, so weird debug etc CPUFlag_XScaleJTAGconnected * 1:SHL:19 ; JTAG has been connected CPUFlag_HiProcVecs * 1:SHL:20 ; High processor vectors are in use CPUFlag_ExtraReasonCodesFixed * 1:SHL:31 ; Bug causing unknown reason codes to always raise an error has been fixed (bug affected 3.7X, 5.XX, and CallASWI) ; OS_PlatformFeatures 34 flags: ^ 0 CPUFeature_AESE_AESD_AESMC_AESIMC # 1 CPUFeature_BFC_BFI_SBFX_UBFX # 1 CPUFeature_BKPT # 1 CPUFeature_BLX # 1 CPUFeature_BX # 1 CPUFeature_CLREX_LDREXB_LDREXH_STREXB_STREXH # 1 CPUFeature_CLZ # 1 CPUFeature_CRC32B_CRC32H_CRC32W_CRC32CB_CRC32CH_CRC32CW # 1 CPUFeature_DMB_DSB_ISB # 1 CPUFeature_ERET_MSR_MRS_banked # 1 CPUFeature_HVC # 1 CPUFeature_Interworking_MOV_pc # 1 CPUFeature_LDAx_STLx # 1 ; LDAB, LDAH, LDA, LDAEXB, LDAEXH, LDAEX, LDAEXD, STLB, STLH, STL, STLEXB, STLEXH, STLEX, STLEXD CPUFeature_LDM_STM_continuable # 1 CPUFeature_LDM_STM_noninterruptible # 1 CPUFeature_LDM_STM_restartable # 1 CPUFeature_LDRD_STRD # 1 CPUFeature_LDREXD_STREXD # 1 CPUFeature_LDREX_STREX # 1 CPUFeature_LDRHT_LDRSBT_LDRSHT_STRHT # 1 CPUFeature_LDRH_LDRSH_STRH # 1 CPUFeature_LDRSB # 1 CPUFeature_LDR_STR_Rd_Rn_restriction # 1 ; LDR/STR with writeback and Rd == Rn is not allowed. Applies to all load/store single instructions. CPUFeature_MLS # 1 CPUFeature_MOVW_MOVT # 1 CPUFeature_MRS_MSR # 1 CPUFeature_MUL_Rd_Rn_restriction # 1 ; MUL with Rd == Rn is not allowed. Applies to MUL, MLA, SMLAL, SMULL, UMLAL, UMULL CPUFeature_MULS_flag_corruption # 1 ; MULS, MLAS corrupt C flag. SMLALS, SMULLS, UMLALS, UMULLS corrupt C & V flags. CPUFeature_NOP_hints # 1 CPUFeature_PKHxy_xADD16_xADD8_xASX_xSUB16_xSUB8_xSAX_SEL # 1 ; PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT16, SSUB16, SSUB8, SSAX, UADD16, UADD8, UASX, UHADD16, UADD8, UHASX, UHSUB16, UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8, USAT16, USUB16, USUB8, USAX CPUFeature_PLD # 1 CPUFeature_PLDW # 1 CPUFeature_PLI # 1 CPUFeature_PSR_GE_bits # 1 CPUFeature_PSR_Q_bit # 1 CPUFeature_QADD_QDADD_QDSUB_QSUB # 1 CPUFeature_RBIT # 1 CPUFeature_REV_REV16_REVSH # 1 CPUFeature_SEVL # 1 CPUFeature_SHA1C_SHA1P_SHA1M_SHA1H_SHA1SU0_SHA1SU1 # 1 CPUFeature_SHA256H_SHA256H2_SHA256SU0_SHA256SU1 # 1 CPUFeature_SMC # 1 CPUFeature_SMLAxy_SMLALxy_SMLAWy_SMULxy_SMULWy # 1 ; SMLABB, SMLABT, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT CPUFeature_SMLAlDx_SMLSlDx_SMMLAr_SMMLSr_SMMULr_SMUADx_SMUSDx # 1 ; SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, SMUSDX CPUFeature_SMULL_SMLAL # 1 CPUFeature_SRS_RFE_CPS # 1 CPUFeature_SSAT_USAT # 1 CPUFeature_SWP_SWPB # 1 CPUFeature_SWP_SWPB_uniproc # 1 CPUFeature_SXTAB_SXTAH_UXTAB_UXTAH # 1 CPUFeature_SXTB16_SXTAB16_UXTB16_UXTAB16 # 1 CPUFeature_SXTB_SXTH_UXTB_UXTH # 1 CPUFeature_SYS_mode # 1 CPUFeature_TEQP # 1 ; TEQP, TSTP, CMPP, CMNP CPUFeature_UDIV_SDIV # 1 CPUFeature_UMAAL # 1 CPUFeature_UMULL_UMLAL # 1 CPUFeature_WFE # 1 CPUFeature_Rotated_loads # 1 ; CPU supports old-style rotated load behaviour CPUFeature_Unaligned_loads # 1 ; CPU supports new-style unaligned load/store behaviour CPUFeature_Max # 0 ; OS_MMUControl reason codes ^ 0 MMUCReason_ModifyControl # 1 MMUCReason_Flush # 1 MMUCReason_GetARMop # 1 MMUCReason_Unknown # 0 ; These are the ARMops exposed by OS_MMUControl 2 ^ 0 ARMop_Cache_CleanInvalidateAll # 1 ; 0 ARMop_Cache_CleanAll # 1 ; 1 ARMop_Cache_InvalidateAll # 1 ; 2 ARMop_Cache_RangeThreshold # 1 ; 3 ARMop_TLB_InvalidateAll # 1 ; 4 ARMop_TLB_InvalidateEntry # 1 ; 5 ARMop_DSB_ReadWrite # 1 ; 6 ARMop_IMB_Full # 1 ; 7 ARMop_IMB_Range # 1 ; 8 ARMop_IMB_List # 1 ; 9 ARMop_MMU_Changing # 1 ; 10 ARMop_MMU_ChangingEntry # 1 ; 11 ARMop_MMU_ChangingUncached # 1 ; 12 ARMop_MMU_ChangingUncachedEntry # 1 ; 13 ARMop_MMU_ChangingEntries # 1 ; 14 ARMop_MMU_ChangingUncachedEntries # 1 ; 15 ARMop_DSB_Write # 1 ; 16 ARMop_DSB_Read # 1 ; 17 ARMop_DMB_ReadWrite # 1 ; 18 ARMop_DMB_Write # 1 ; 19 ARMop_DMB_Read # 1 ; 20 ARMop_Cache_CleanInvalidateRange # 1 ; 21 ; Not fully tested yet, so keep out of the public API ;ARMop_Cache_CleanRange # 1 ; 22 ;ARMop_Cache_InvalidateRange # 1 ; 23 ;ARMop_ICache_InvalidateAll # 1 ; 24 ;ARMop_ICache_InvalidateRange # 1 ; 25 ARMop_Max # 0 ; SeriousErrorV reason codes (R2) ^ 0 SeriousErrorV_Collect # 1 ; ABT mode, IRQ disabled (maybe FIQ disabled too), R0=reg dump, R1=(untranslated) error block SeriousErrorV_Recover # 1 ; SVC mode, IRQ disabled, R0=translated error block SeriousErrorV_Report # 1 ; SVC mode, IRQ enabled, R0=translated error block SeriousErrorV_CustomReport # 1 ; SVC mode, IRQ enabled, R0=translated error, R1=flags, R3=callback function, R4=callback R0 SeriousErrorV_CustomReport_Annotated * 1 ; 1 => Produce annotated text dump ; 0 => Produce raw binary dump ; Have more flags to control which items are included in the annotated dump? ; Extended ROM footer entries ^ 0 ExtROMFooter_BuildDate # 1 ExtROMFooter_CompressedROMHints # 1 ExtROMFooter_DebugSymbols # 1 END