0 STATE (X)                     0->X (8)
1 nWAIT                         1->9
2 BRST                          2->X (2)
3 nFIQ                          3->X (13)
4 nIRQ                          4->X (12)
5 nc (MAS[0])                   5->6
6 nMREQ           1             6->1
7 SEQ (X)                       7->0
8 nRW                           8->3
9 nBW (MAS[1])                  9->7
10 LOCK                         10->X (10)
11 nTRANS (X)                   11->5
12 nOPC (X)                     12->4
13 nc                           13->11 (DMA low)
14 ABE
15 DBE



Master clock: (MCLK down)
0 SEQ                           0->7
1 nMREQ                         1->6
2 nEXEC

Slave clock: (MCLK up)
3 nRW                          16->8
4 nOPC                         17->12
5 nTRANS                       18->11
6 MAS[0]                       19->5
7 MAS[1]                       20->9
8 DBGACK
9 nWAIT                        22->1
10 ABORT
11 DMA
12 BIGEND
13 CS0
14 CS1
15 CS2
16 CS3
17 CS4
18 CS5
19 CS6
20 CS7


0

0->X