; > TestSrc.IOC TTL RISC OS 2+ POST IO controller ; ; This initial IOC test simply reports the content of the IRQ and FIRQ ; registers, to show any unexpected pending IRQs. ; Certain of these should really be cleared, and the effect of an ; interrupt tested. ; ;------------------------------------------------------------------------ ; History ; ; Date Name Comment ; ---- ---- ------- ; 18-Dec-89 ArtG Initial version ; 29-Nov-91 ArtG Added IOC bus test using mask registers ; 20-Jun-93 ArtG Modified for 29-bit IOMD test ; 18-Nov-94 RCM Morris changes ; 15-May-96 BAR Changes for 7500FE - new IOMD ID code. ; Now list 3 ID codes. ; 17-Jun-96 BAR Change ts_IOMD_IDn definitions to point to ; definitions in IOMDL ; 09-Jul-96 BAR Improve IOMD ID code. ; ; ;------------------------------------------------------------------------ [ IO_Type = "IOMD" ts_IObase * IOMD_Base ts_IOmask * &00fffff0 ;&1fffffff ts_IOreg1 * IOMD_VIDEND ;IOMD_VIDCUR ts_IOreg2 * IOMD_VIDSTART ts_IObswap * 32 ts_IOMD_ID1 * IOMD_Original ts_IOMD_ID2 * IOMD_7500 ts_IOMD_ID3 * IOMD_7500FE | ts_IObase * IOC ts_IOmask * &ff0000 ts_IOreg1 * IOCIRQMSKA ts_IOreg2 * IOCIRQMSKB ts_IObswap * 16 ] ts_IOCreg MOV r0,#0 ; zero error accumulator LDR r3, =ts_IObase MOV r1,#(1 :SHL: 31) ; initialise bit-set test mask 0 MVN r2,r1 ; make bit-clear test mask LDR r4, =ts_IOmask ANDS r4,r1,r4 BEQ %FT1 ; skip if this bit isn't tested STR r1,[r3,#ts_IOreg1] STR r2,[r3,#ts_IOreg2] LDR r4,[r3,#ts_IOreg1] ; EOR r4, r4, r1, LSR #ts_IObswap ; check bit-set test was OK EOR r4, r4, r1 ; check bit-set test was OK ORR r0, r0, r4 ; accumulate errors in r0 LDR r4,[r3,#ts_IOreg2] ; EOR r4, r4, r2, LSR #ts_IObswap ; check bit-clear test was OK EOR r4, r4, r2 ; check bit-clear test was OK ORR r0, r0, r4 ; accumulate errors in r0 1 MOV r1, r1, LSR #1 ; shift mask downwards TEQ r1,#0 BNE %BT0 ; and loop until all bits tested LDR r8, =ts_IOmask ANDS r8, r0, r8 MOV pc,r14 ; return error if any bit failed ts_IOCstat LDR r3, =ts_IObase ; r3 points to IO Chip base address MOV r0,#0 ; clear r0 [ IO_Type = "IOMD" ; Check IOMD chip variants LDRB r1,[r3,#IOMD_ID1] ; load r1 with IOMD ID high byte LDRB r0,[r3,#IOMD_ID0] ; load r1 with IOMD ID low byte ORR r0,r0,r1, LSL #8 ; Or r0 and r1 - shifted left 8, put in r0 LDR r1,=ts_IOMD_ID1 ; get Ref IOMD ID code #1 CMPS r0,r1 ; check =to IOMD ID Code #1 LDRNE r1,=ts_IOMD_ID2 ; If not ID1, get Ref IOMD ID code #2 CMPNES r0,r1 ; If not ID1, check =to IOMD ID Code #2 LDRNE r1,=ts_IOMD_ID3 ; if not ID1 and ID2, get Ref IOMD ID code #3 CMPNES r0,r1 ; If not ID1 and ID2, check =to IOMD ID Code #3 MOV r0,r0,LSL #16 ; Move ID code in to top 16 bits LDRB r1,[r3,#IOMD_VERSION] ; Load r with IOMD Version number ORR r8,r0,r1, LSL #12 ; Or r0 and r1 - shifted left 12, put in r8 MOV pc,r14 ; extit to whence came from. | ; Check IOC chip variants LDRB r1,[r3,#IOCControl] ORR r0,r0,r1, LSL #(32 - 8) LDRB r1,[r3,#IOCIRQSTAA] ORR r0,r0,r1, LSL #(32 - 16) LDRB r1,[r3,#IOCIRQSTAB] ORR r0,r0,r1, LSL #(32 - 24) LDRB r1,[r3,#IOCFIQSTA] ORR r8,r0,r1 ANDS r1,r1,#0 ; return zero flag (OK) MOV pc,r14 ] END