; Copyright 1996 Acorn Computers Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
;     http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; > Morris

;
; ROM entry code for RISC OS Black
;

MorrisHeaderCodeSize * (24*4)   ;Code occupies less than this, we pad to this boundary so POST code
                                ;has a nicely defined place for its romsize and code entry points
; VECTOR AREA:

        LDR     pc, .+ResetIndirection
        LDR     PC, UNDEF_VEC
        LDR     PC, SWI_VEC
        LDR     PC, PREF_VEC
        LDR     PC, DATA_VEC
        LDR     PC, RES_VEC                   ; addr. exn not generated
        LDR     PC, IRQ_VEC
        LDR     PC, FIQ_VEC

        ! 0, "*** WARNING *** assembling Morris code"

; The above 8 instructions will operate as expected in 32-bit ROM mode,
; or in 16-bit ROM mode with a 16-bit ROM used.  In 16-bit ROM mode, and
; with 32-bit wide ROMs in use, they will instead be intepreted as 4
; NV-condition instructions (exact meaning not determined and should be
; irrelevant) which should do nothing and so allow control to drop
; through to this point, still in 16-bit mode.  Force IOMD into 32-bit
; ROM mode for bank 0.  The following instruction sequence has been
; produced in 16-in-32 form by extracting hex values from a listing...

        DCD     &0000B632, &0000E3A0    ; 20: MOV R11, #IO+IOMDREGS - point at IOMD
        DCD     &00000000, &0000E3A0    ; 28: MOV R0, #&0 - ROMCR:32b,slow,218.75us,no burst
        DCD     &00000080, &0000E5CB    ; 30: STRB R0,[R11,#ROMCR0] - switch mode
 [ :LNOT: ParallelFlashUpgrade
        DCD     &0000F000, &0000E3A0    ; 38: MOV PC, #0 - jump to 0 (this instr pre-fetched)
 |
; At this point, we know that we're in an ARM 7500-based box with 32-bit ROMs that's
; just been powered up. These are the conditions under which we may wish to reprogram
; ourselves.
CFR_Offset * (ConsiderFlashROM - ROM - ((.-ROM)/2) - 8)/4
        DCD     CFR_Offset :AND: &FFFF  ; 38: B ConsiderFlashROM (this instr pre-fetched)
        DCD     &0000EA00 + (CFR_Offset:SHR:16)
 ]

; vector absolute targets for use from physical vector instructions

UNDEF_VEC       DCD     UndInstInReset-ROM
SWI_VEC         DCD     SWIInReset    -ROM
PREF_VEC        DCD     PrefAbInReset -ROM
DATA_VEC        DCD     DataAbInReset -ROM
RES_VEC         DCD     AddrExInReset -ROM
IRQ_VEC         DCD     IRQInReset    -ROM
FIQ_VEC         DCD     FIQInReset    -ROM

UndInstInReset
SWIInReset
PrefAbInReset
DataAbInReset
AddrExInReset
IRQInReset
FIQInReset
        SUB     pc, pc, #8

        ASSERT  .-ROM <= MorrisHeaderCodeSize
        %       MorrisHeaderCodeSize-(.-ROM)

        END