Commits (79)
  • Jeffrey Lee's avatar
    Initial kernel support for Cortex-A8 processors. · e2262380
    Jeffrey Lee authored
    Detail:
      hdr/ARMops - Added Cortex_A8 processor type, new ARM architecture number
      hdr/Options - Enabled various kernel debug options
      s/ARMops - Added Cortex-A8/OMAP3530 to known CPUs list. Ignore cache type register for ARM architecture &F.
      s/NewIRQs - Increase MaxInterrupts to 96
    Admin:
      Brief testing under qemu-omap3.
    
    
    
    Version 5.35, 4.79.2.98.2.1. Tagged as 'Kernel-5_35-4_79_2_98_2_1'
    e2262380
  • Jeffrey Lee's avatar
    Add support for Cortex cache type. Extend ARM_Analyse to, where appropriate,... · ad9cdf41
    Jeffrey Lee authored
    Add support for Cortex cache type. Extend ARM_Analyse to, where appropriate, use CPU feature registers to identify CPU capabilities.
    
    Detail:
      s/ARMops - Support for Cortex multi-level cache (CT_ctype_WB_CR7_Lx). New ARM_Analyse_Fancy to identify CPU capabilities using feature registers.
      s/HAL - Modify pre-ARMop cache code to handle Cortex-syle caches.
      s/MemInfo - Replace ARM_flush_TLB macro call with appropriate ARMop to provide Cortex compatability
      hdr/ARMops - Update list of ARM architectures
      hdr/CoPro15ops - Deprecate ARM_flush_* macros for HAL kernels, as they are no longer capable of flushing all cache types. ARMops should be used instead.
      hdr/KernelWS - Add storage space for multi-level cache properties required for new cache cleaning code.
    Admin:
      Tested under qemu-omap3. Still unable to verify on real hardware due to lack of appropriate MMU code. However new OMAP3 HAL code that uses similar cache management functions appears to work fine on real hardware.
    
    
    Version 5.35, 4.79.2.98.2.2. Tagged as 'Kernel-5_35-4_79_2_98_2_2'
    ad9cdf41
  • Jeffrey Lee's avatar
    Add VMSAv6 MMU support, fixes to allow booting on beagleboard · 3d1317e7
    Jeffrey Lee authored
    Detail:
      s/ARM600 - fix to SyncCodeAreasRange to correctly read cache line length for WB_CR7_Lx caches
      s/ARMops - Cortex cache handling fixes. Enable L2 cache for Cortex.
      s/ChangeDyn - VMSAv6 support in AllocateBackingLevel2
      s/HAL - Improve RISCOS_InitARM to set/clear correct CP15 flags for ARMv6/v7. VMSAv6 support in code to generate initial page tables.
      s/NewReset - Extra DebugTX calls during OS startup. Disable pre-HAL Processor_Type for HAL builds.
      s/VMSAv6 - Main VMSAv6 MMU code - stripped down version of s/ARM600 with support for basic VMSAv6 features.
      hdr/Options - Use VMSAv6 MMU code, not ARM600. Disable ARM6support since current VMSAv6 code will conflict with it.
    Admin:
      Tested basic OS functionality under qemu-omap3 and revision B6 beagleboard.
    
    
    Version 5.35, 4.79.2.98.2.3. Tagged as 'Kernel-5_35-4_79_2_98_2_3'
    3d1317e7
  • Ben Avison's avatar
    "Unknown OS_PlatformFeatures reason code" now has a non-zero error number. · b2c2bc9e
    Ben Avison authored
    Detail:
      Error number &1F3 allocated.
    Admin:
      Requires HdrSrc 1.63.
      Fix supplied by Rob Sprowson.
    
    Version 5.35, 4.79.2.99. Tagged as 'Kernel-5_35-4_79_2_99'
    b2c2bc9e
  • John Ballance's avatar
    Datestamp of kernel for 5.15 build · fdebe479
    John Ballance authored
    Detail:
        Version file updated
    Admin:
        John Ballance, Castle
    
    Version 5.35, 4.79.2.100. Tagged as 'Kernel-5_35-4_79_2_100'
    fdebe479
  • Ben Avison's avatar
    Increased Kernel version number to 5.15. · 40949773
    Ben Avison authored
    Detail:
      Castle seems to have settled on an official 5.14 build, so changed our
      version to distinguish our test builds from the official one.
    Admin:
      No testing required
    
    Version 5.35, 4.79.2.101. Tagged as 'Kernel-5_35-4_79_2_101'
    40949773
  • Jeffrey Lee's avatar
    Fix kernel cache clean/invalidate operations for Cortex CPUs · d28235ea
    Jeffrey Lee authored
    Detail:
      s/ARMops - Fix set/way-based cache ops for cache type WB_CR7_Lx to iterate sets/ways/cache levels properly
      s/HAL - Fix HAL_InvalidateCache_ARMvF to iterate sets/ways/cache levels properly
    Admin:
      Tested on rev C2 beagleboard
    
    
    Version 5.35, 4.79.2.98.2.4. Tagged as 'Kernel-5_35-4_79_2_98_2_4'
    d28235ea
  • Jeffrey Lee's avatar
    Assorted kernel fixes for ARMv6/ARMv7 · ca8f36f5
    Jeffrey Lee authored
    Detail:
      s/ARMops - Fix IMB_Range_WB_CR7_Lx to clean the correct number of cache lines
      s/HAL - Change CP15 control register flags so unaligned loads are enabled on ARMv6 (to simplify support for ARMv7 where unaligned loads are always enabled, and to match the behaviour expected by the example code in Hdr:CPU.Arch)
      s/AMBControl/memmap - Make AMB_LazyFixUp use the correct L2PT protection flags depending on ARM600/VMSAv6 MMU model. Also guard against problems caused by future L2PT flag changes.
      s/vdu/vdugrafj - Fix previously undiscovered 32bit incompatability in GetSprite (OS_SpriteOp 14/16)
    Admin:
      Tested on rev C2 beagleboard
    
    
    Version 5.35, 4.79.2.98.2.5. Tagged as 'Kernel-5_35-4_79_2_98_2_5'
    ca8f36f5
  • Ben Avison's avatar
    Unaligned loads/stores optimised for ARMv6+ · 70865f8b
    Ben Avison authored
    Detail:
      Having scanned the kernel source for unaligned load code fragments which
      would abort on ARMv6 and v7 and not having found any, I took the opportunity
      to give them build-time switches to use unaligned LDR((S)H)/STR(H)
      instructions if built for a new enough platform. Also added a couple of
      cases of LDRSB that will benefit v4 CPUs and a few instances of the v6
      SXTH instruction, but since objasm doesn't yet understand it (and when it
      does, not everyone will have upgraded) they are currently written as
      DCI statements.
      Most of the changes are to OS_Word handlers, which are notorious in that
      their input/output block is not word-aligned.
    Admin:
      Not tested, but it should at least build.
    
    Version 5.35, 4.79.2.98.2.6. Tagged as 'Kernel-5_35-4_79_2_98_2_6'
    70865f8b
  • Jeffrey Lee's avatar
    Disable paged scrolling when using the debug terminal · 76cbfa84
    Jeffrey Lee authored
    Detail:
      s/vdu/vduwrch - Modify PageTest to never use paged scrolling when DebugTerminal is true (since serial terminals aren't able to send shift up/down messages)
    Admin:
      Tested on rev C2 beagleboard.
    
    
    Version 5.35, 4.79.2.98.2.7. Tagged as 'Kernel-5_35-4_79_2_98_2_7'
    76cbfa84
  • Ben Avison's avatar
    Miscellaneous v6-related updates · 9d9aa41b
    Ben Avison authored
    Detail:
     * Stopped calling the broken abort fixup code when running under VMSAv6.
       Might be desirable to update it, possibly farmed out to a separate module -
       still need to think about this.
     * Unaligned load optimisations can now be disabled by the global NoUnaligned
       flag for testing purposes.
     * Extended OS_ReadUnsigned to permit reading of 64-bit unsigned integers.
       See Docs.ReadUnsigned for more details. Also sped it up by using MLA
       (or UMLAL) for most digits rather than repeated addition.
     * Bugfix is OS_GSRead: an uninitialised r0 was being passed to
       OS_ReadUnsigned, causing undesirable effects on rare occasions.
    Admin:
      Tested on a rev B7 beagleboard.
    
    Version 5.35, 4.79.2.98.2.8. Tagged as 'Kernel-5_35-4_79_2_98_2_8'
    9d9aa41b
  • Ben Avison's avatar
    Build fix · 0538bbba
    Ben Avison authored
    Detail:
      Some users reported problems building the sources if they had other
      installations of perl on their build machine. The build system was using a
      mixture of "perl" and "<Perl$Dir>.perl" to invoke the interpreter, and
      sometimes but not always using "do" to expand system variables on the
      command line. This has now been standardised to use "do <Perl$Dir>.perl in
      all cases, and where possible, to use the makefile macro ${PERL}.
    Admin:
      Checked that a Tungsten build still works on a build machine with no other
      perl installation. "perl" was aliased to an error to ensure it wasn't used.
    
    Version 5.35, 4.79.2.102. Tagged as 'Kernel-5_35-4_79_2_102'
    0538bbba
  • Ben Avison's avatar
    Added comment · 9e7233fb
    Ben Avison authored
    Detail:
      Noted reservation of IO controller type  passed to OS_Memory 9 used when
      system is running as a coprocessor. Not used by current code but we need to
      make sure that any future reservations use different numbers.
    Admin:
      No functional change. Brought to our attention by Rob Sprowson.
    
    Version 5.35, 4.79.2.103. Tagged as 'Kernel-5_35-4_79_2_103'
    9e7233fb
  • Ben Avison's avatar
    Fix bugs and inefficiencies revealed by unaligned data audit · 8a9e694c
    Ben Avison authored
    Detail:
      s.PMF.i2cutils line 454: this LDR of byte values was harmless (bits 8
        upwards are discarded later) but slower than an LDRB on ARMv6 or later.
      s.PMF.i2cutils line 556: should have loaded RTCFitted using LDRB. Looks
        like effect would have been to reduce utilisation of CMOS cache.
      s.vdu.vduswis line 1500: mistakenly accessing ExternalFramestore using LDR.
        I don't think the intention was to prevent the screen DA being resized
        while screen memory was claimed, but that was the effect.
      s.vdu.vduwrch line 3106: this LDR of a 1-byte variable was harmless (only
        used for testing bit 4) but slower than an LDRB on ARMv6 or later.
      CPU version is no longer specified in the makefile - it's better to inherit
      it from the build environment now that we actually set it appropriately.
    Admin:
      Built and briefly tested.
    
    Version 5.35, 4.79.2.98.2.9. Tagged as 'Kernel-5_35-4_79_2_98_2_9'
    8a9e694c
  • Jeffrey Lee's avatar
    Make Cortex kernel call HAL_IRQClear after servicing I2C interrupts · 7f375f88
    Jeffrey Lee authored
    Detail:
      s/PMF/IIC - IICIRQ now calls HAL_IRQClear after HAL_IICMonitorTransfer, in order to make sure the IRQ controller is restarted.
    Admin:
      Tested on rev C2 beagleboard
    
    
    Version 5.35, 4.79.2.98.2.10. Tagged as 'Kernel-5_35-4_79_2_98_2_10'
    7f375f88
  • Jeffrey Lee's avatar
    Add HAL RTC support to Cortex branch of kernel, clean up RTCSupport code · 7f21e480
    Jeffrey Lee authored
    Detail:
      HAL kernels (on the Cortex branch at least) now support HALDevice-based RTCs. If the kernels own RTC code is disabled or fails to detect an RTC, then after HAL_InitDevices is called the HALDevice list will be scanned for any HAL-resident RTC devices.
      Additionally, the RTCSupport flag (in Hdr:Machine.Machine), which was previously TRUE for all HAL kernels, can now be set to FALSE in HAL kernels to disable the kernels own IIC RTC code. This allows the unwanted legacy RTC code to be disabled for machines which are known to use HAL RTCs instead.
      hdr/RTCDevice - new header describing data structures used for HAL RTC device
      hdr/HALDevice - added RTCDevice device type, IIC serial bus type
      hdr/KernelWS - upgraded RTCFitted from a 1 byte field to 4 byte. It now stores either a null value (for no RTC), a value <2048 for an IIC RTC address, or a value >= 2048 for a RTCDevice ptr
      Makefile - added header export of hdr/RTCDevice
      s/GetAll - include hdr/RTCDevice
      s/NewReset - initialise HAL RTC after HAL_InitDevices if required
      s/PMF/i2cutils, s/PMF/osinit, s/PMF/osword - modifications to allow use of HAL RTC (and disallow use of builtin IIC RTC)
    Admin:
      Tested on rev C2 beagleboard
    
    
    Version 5.35, 4.79.2.98.2.11. Tagged as 'Kernel-5_35-4_79_2_98_2_11'
    7f21e480
  • Jeffrey Lee's avatar
    Disable DebugTerminal by default for OMAP3 kernel · a44eed24
    Jeffrey Lee authored
    Detail:
      The host-mode driver for the MUSB OTG controller is now working, so there's no longer any reason to have the DebugTerminal enabled by default.
    Admin:
      Tested on rev C2 beagleboard
    
    
    Version 5.35, 4.79.2.98.2.12. Tagged as 'Kernel-5_35-4_79_2_98_2_12'
    a44eed24
  • Jeffrey Lee's avatar
    Update Cortex kernel to cope correctly with HAL RTC errors · d08aa9dc
    Jeffrey Lee authored
    Detail:
      The kernel will now attempt to cope with errors returned by HAL RTC devices - For RTC read operations, instead of just loading random garbage, the bad result will now be ignored and the soft 5-byte time left unaltered.
    Admin:
      Tested on rev C2 beagleboard. Year now correctly defaults to 1970 instead of 1900 if the OMAP3 RTC driver returns an error because the RTC isn't running yet.
    
    
    Version 5.35, 4.79.2.98.2.13. Tagged as 'Kernel-5_35-4_79_2_98_2_13'
    d08aa9dc
  • Jeffrey Lee's avatar
    Fix error handling for sparse dynamic area resize operations, increase Cortex... · 04f4e5cd
    Jeffrey Lee authored
    Fix error handling for sparse dynamic area resize operations, increase Cortex kernel version number to 5.15
    
    Detail:
      s/ChangeDyn - Swap CMP with TEQ to avoid accidental clobbering of V flag before its state is checked on return from a SWI. Errors encountered during sparse dynamic area resize operations (OS_DynamicArea 9 & 10) should now be reported properly.
      Version - Update kernel version/date to 5.15, to match current HAL version. This change is to allow modules to properly detect whether the kernel has the sparse dynamic area fix - it does not (yet) mean that the Cortex kernel contains all the features of the current development HAL kernel!
    Admin:
      Tested on rev C2 beagleboard
    
    
    Version 5.35, 4.79.2.98.2.14. Tagged as 'Kernel-5_35-4_79_2_98_2_14'
    04f4e5cd
  • Jeffrey Lee's avatar
    Fix error handling for sparse dynamic area resize operations (for main HAL branch) · d0ddc243
    Jeffrey Lee authored
    Detail:
      s/ChangeDyn - Swap CMP with TEQ to avoid accidental clobbering of V flag before its state is checked on return from a SWI. Errors encounterd during sparse dynamic area resize operations (OS_DynamicArea 9 & 10) should now be reported properly.
    Admin:
      Not tested, but the same fix has been proven to work on the Cortex branch.
    
    
    Version 5.35, 4.79.2.104. Tagged as 'Kernel-5_35-4_79_2_104'
    d0ddc243
  • Ben Avison's avatar
    Build fix · 62fb1997
    Ben Avison authored
    Detail:
      Hdr:Macros has just been changed on the trunk in such a way that you now
      need to include Hdr:CPU.Arch as well. Previously this include file was only
      referenced by the Cortex branch kernel - now mirrored on the HAL branch
      kernel too.
    Admin:
      Verified that IOMD ROM now builds again - should fix Tungsten ROM build too.
    
    Version 5.35, 4.79.2.105. Tagged as 'Kernel-5_35-4_79_2_105'
    62fb1997
  • Jeffrey Lee's avatar
    Fix bug when creating code variables via OS_SetVarVal (HAL branch) · 9fe47897
    Jeffrey Lee authored
    Detail:
      OS_SetVarVal was failing to call XOS_SynchroniseCodeAreas after copying the code variables code block into the system heap. This has now been fixed.
    Admin:
      Fix tested in Cortex branch on rev C2 beagleboard. Debugger module now shows the right register names instead of ofla!
    
    
    Version 5.35, 4.79.2.106. Tagged as 'Kernel-5_35-4_79_2_106'
    9fe47897
  • Jeffrey Lee's avatar
    Fix bug when creating code variables via OS_SetVarVal, remove errant line from... · e1e71002
    Jeffrey Lee authored
    Fix bug when creating code variables via OS_SetVarVal, remove errant line from s.ARM600, automatically enable alignment exceptions if NoUnaligned is TRUE (Cortex branch)
    
    Detail:
      s/ARM600 - Removed an errant line that could have caused problems if the ARM600 MMU model was used with the WB_CR7_Lx cache type
      s/Arthur2 - OS_SetVarVal was failing to call XOS_SynchroniseCodeAreas after copying the code variables code block into the system heap. This has now been fixed.
      s/HAL - Alignment exceptions are now automatically enabled when the kernel is built with the NoUnaligned option turned on.
    Admin:
      Tested on rev C2 beagleboard. OS_SetVarVal fix means the Debugger module now shows the right register names instead of ofla!
    
    
    Version 5.35, 4.79.2.98.2.15. Tagged as 'Kernel-5_35-4_79_2_98_2_15'
    e1e71002
  • Jeffrey Lee's avatar
    Add header for video HAL devices, device IDs for OMAP3 DMA & video controllers to Cortex kernel · a15ebf9a
    Jeffrey Lee authored
    Detail:
      hdr/VideoDevice, Makefile - Add initial version of header for video HAL devices
      hdr/HALDevice - Add device IDs for OMAP3 DMA & video devices.
    Admin:
      Tested on rev C2 beagleboard
    
    
    Version 5.35, 4.79.2.98.2.16. Tagged as 'Kernel-5_35-4_79_2_98_2_16'
    a15ebf9a
  • Jeffrey Lee's avatar
    Fix cortex kernel makefile · 232135e5
    Jeffrey Lee authored
    Detail:
      Makefile rule was missing for VideoDevice header export, preventing it from being exported
    Admin:
      Tested on rev C2 beagleboard. (No, really, I mean it this time!)
    
    
    Version 5.35, 4.79.2.98.2.17. Tagged as 'Kernel-5_35-4_79_2_98_2_17'
    232135e5
  • Jeffrey Lee's avatar
    Fix HAL RTC initialisation in Cortex kernel · fc0b6873
    Jeffrey Lee authored
    Detail:
      LookForHALRTC wasn't initialising R12 to point to the OS Byte workspace before calling CheckYear, and instead relying on the previous value. This resulted in the RTC initialisation breaking once HAL_InitDevices started doing things to corrupt R12.
    Admin:
      Tested on rev C2 beagleboard
    
    
    Version 5.35, 4.79.2.98.2.18. Tagged as 'Kernel-5_35-4_79_2_98_2_18'
    fc0b6873
  • Jeffrey Lee's avatar
    Add TPS65950 audio & mixer devices to Cortex HALDevice.hdr · ab7051c3
    Jeffrey Lee authored
    Version 5.35, 4.79.2.98.2.19. Tagged as 'Kernel-5_35-4_79_2_98_2_19'
    ab7051c3
  • John Ballance's avatar
    modified s.PMF.osword to cope with the iyonix RTC operating in BCD · 23e2c1e0
    John Ballance authored
    Also upissued to RISC OS 5.16 to release this in ROM
    Detail:
      (list files and functions that have changed)
    Admin:
    tested at Castle (JB)
      (highlight level of testing that has taken place)
      (bugfix number if appropriate)
    
    
    Version 5.35, 4.79.2.107. Tagged as 'Kernel-5_35-4_79_2_107'
    23e2c1e0
  • Steve Revill's avatar
    Incremented RISC OS version for the HAL branch to next development number (5.17). · dc03d9c3
    Steve Revill authored
    Version 5.35, 4.79.2.108. Tagged as 'Kernel-5_35-4_79_2_108'
    dc03d9c3
  • Steve Revill's avatar
    Incremented RISC OS version for the Cortex branch to next development number (5.17). · 6dfb2430
    Steve Revill authored
    Version 5.35, 4.79.2.98.2.20. Tagged as 'Kernel-5_35-4_79_2_98_2_20'
    6dfb2430
  • Jeffrey Lee's avatar
    Migrate 2012 RTC fix to Cortex branch of kernel · 73eefecf
    Jeffrey Lee authored
    Detail:
      s/PMF/osword - Migrate the 2012 RTC fix from the HAL branch to the Cortex branch, plus apply similar fix to the code that handles HAL RTC devices (via new YearLOIsGood flag)
      s/PMF/i2cutils - Update HAL RTC year handling to correctly treat YearLO as either 2-bit int or 2-digit BCD
      hdr/RTCDevice - Add YearLOIsGood flag, revise NeedsYearHelp description
    Admin:
      Tested on rev C2 beagleboard. Code seems to behave as intended.
    
    
    Version 5.35, 4.79.2.98.2.21. Tagged as 'Kernel-5_35-4_79_2_98_2_21'
    73eefecf
  • Jeffrey Lee's avatar
    Fix bug in InitCMOSCache that could cause CMOS to be errouneously reset if... · ed3cc555
    Jeffrey Lee authored
    Fix bug in InitCMOSCache that could cause CMOS to be errouneously reset if NVRAM is of type 'MaybeIIC'
    
    Detail:
      s/PMF/i2cutils - Kernel was checking if the full IIC flags word was equal to MaybeIIC instead of just checking if the Provision bits equalled MaybeIIC. Thus if any of the additional flags were set along with MaybeIIC the kernel would have skipped the probing code, skipped the IIC code, and fallen through to using the (likely unimplemented) HAL interface for initialising the NVRAM cache.
    Admin:
      Tested in IOMD build under RPCemu; kernel now takes the correct path for MaybeIIC + ProtectAtEnd.
    
    
    Version 5.35, 4.79.2.109. Tagged as 'Kernel-5_35-4_79_2_109'
    ed3cc555
  • Jeffrey Lee's avatar
    Fix bug in InitCMOSCache that could cause CMOS to be erroneously reset if... · 2b35d8c2
    Jeffrey Lee authored
    Fix bug in InitCMOSCache that could cause CMOS to be erroneously reset if NVRAM is of type 'MaybeIIC' (Cortex branch)
    
    Detail:
      s/PMF/i2cutils - Kernel was checking if the full IIC flags word was equal to MaybeIIC instead of just checking if the Provision bits equalled MaybeIIC. Thus if any of the additional flags were set along with MaybeIIC the kernel would have skipped the probing code, skipped the IIC code, and then fallen through to using the (likely unimplemented) HAL interface for initialising the NVRAM cache.
    Admin:
      Fix tested in HAL branch in IOMD build under RPCemu; kernel now takes the correct path for MaybeIIC + ProtectAtEnd.
    
    
    Version 5.35, 4.79.2.98.2.22. Tagged as 'Kernel-5_35-4_79_2_98_2_22'
    2b35d8c2
  • Jeffrey Lee's avatar
    Fix detection of Philips RTC/NVRAM when MaybeIIC is in use · a6492b14
    Jeffrey Lee authored
    Detail:
      s/PMF/i2cutils - Although the code will detect the Philips RTC correctly, it was failing to set the device size in R4, causing CMOS RAM to be misread. This change fixes that.
    Admin:
      Tested in IOMD HAL build on development version of RPCEmu.
    
    
    Version 5.35, 4.79.2.110. Tagged as 'Kernel-5_35-4_79_2_110'
    a6492b14
  • Jeffrey Lee's avatar
    Fix detection of Philips RTC/NVRAM when MaybeIIC is in use (Cortex branch) · 114948c8
    Jeffrey Lee authored
    Detail:
      s/PMF/i2cutils - Although the code will detect the Philips RTC correctly, it was failing to set the device size in R4, causing CMOS RAM to be misread. This change fixes that.
    Admin:
      Not tested; however it's identical to the fix applied to the HAL branch
    
    
    Version 5.35, 4.79.2.98.2.23. Tagged as 'Kernel-5_35-4_79_2_98_2_23'
    114948c8
  • Jeffrey Lee's avatar
    Update VDU HAL device for new OMAPVideo driver, fix MVA-based cache/TLB... · b213fdd5
    Jeffrey Lee authored
    Update VDU HAL device for new OMAPVideo driver, fix MVA-based cache/TLB maintenance ops aborting on ARMv7, add warning to VDU driver about inconsistent state variables during screen mode changes
    
    Detail:
      hdr/VideoDevice - removed Address2 and Device2 fields as it makes more sense for them to be in the device specific field (which for OMAP3 is a pointer to an OMAP3-specific struct)
      s/VMSAv6 - Modify data abort handler to ignore aborts that are generated by MVA-based cache/TLB maintenance ops. Unlike earlier ARM architectures, MVA-based ops can abort under ARMv7 if the page has no mapping to a physical address.
      s/vdu/vdudriver - Add a warning about VDU driver state variables (particularly CursorAddr) being left in invalid states during the execution of mode changes. This can cause problems if any attempt is made to output to the screen during the mode change (e.g. as a result of an abort)
    Admin:
      Tested on rev C2 beagleboard. Video device changes mean that OMAP3 HAL 0.23 will be needed for ROM compilation to succeed.
    
    
    Version 5.35, 4.79.2.98.2.24. Tagged as 'Kernel-5_35-4_79_2_98_2_24'
    b213fdd5
  • Jeffrey Lee's avatar
    Add ClearIRQ entry to base HAL device struct, plus a couple of new HAL device IDs & bus types · 736b815d
    Jeffrey Lee authored
    Detail:
      hdr/HALDevice, h/HALDevice - inserted the new 'ClearIRQ' entry point into one of the reserved areas.
      Once the RISC OS-side driver has serviced the device's IRQ the ClearIRQ entry point should be called to allow the HAL device to clear any latched interrupt states in intermediate IRQ controllers (e.g. when using GPIO IRQs on OMAP)
      Since this entry point is new, support for it in existing device drivers isn't guaranteed; HAL device implementations of existing APIs must make sure the use a new major version number to indicate that they require ClearIRQ to be called.
      hdr/HALDevice - added some new bus types to represent the GPMC & L3/L4 interconnects in the OMAP.
      hdr/HALDevice - added ethernet NIC device type & IDs for SMSC9221 & DM9000 NICs
    Admin:
      Tested on rev C2 beagleboard
    
    
    Version 5.35, 4.79.2.98.2.25. Tagged as 'Kernel-5_35-4_79_2_98_2_25'
    736b815d
  • Jeffrey Lee's avatar
    Bring HAL branch of hdr/HALDevice, h/HALDevice in line with Cortex branch · ff0710fa
    Jeffrey Lee authored
    Detail:
      A fair number of bus/device types and IDs have been added to the Cortex branch since the branch was created.
      Now that the ClearIRQ entry has also been added, it's about time that the HAL branch was brought up to date.
    Admin:
      Untested, but should be fine.
    
    
    Version 5.35, 4.79.2.111. Tagged as 'Kernel-5_35-4_79_2_111'
    ff0710fa
  • Jeffrey Lee's avatar
    Change default filing system to SCSIFS for CortexA8 machines · 55d55e10
    Jeffrey Lee authored
    Detail:
      s/NewReset - boot filing system now defaults to SCSIFS for the CortexA8 machine type. BeagleBoards, etc. should now be able to run their boot sequence if one is placed on a USB mass storage device.
    Admin:
      Tested on rev C2 beagleboard.
    
    
    Version 5.35, 4.79.2.98.2.26. Tagged as 'Kernel-5_35-4_79_2_98_2_26'
    55d55e10
  • Jeffrey Lee's avatar
    Update Cortex kernel to use correct instruction/memory barriers and to perform... · de8e610e
    Jeffrey Lee authored
    Update Cortex kernel to use correct instruction/memory barriers and to perform branch target predictor maintenance. Plus tweak default CMOS settings.
    
    Detail:
      hdr/Copro15ops - Added myISB, myDSB, myDMB macros to provide barrier functionality on ARMv6+
      s/ARMops, s/HAL, s/VMSAv6, s/AMBControl/memmap - Correct barrier operations are now performed on ARMv6+ following CP15 writes. Branch predictors are now also maintained properly.
      s/NewReset - Change default CMOS settings so number of CDFS drives is 0 in Cortex builds. Fixes rogue CDFS icon on iconbar.
    Admin:
      Tested on rev C2 beagleboard
    
    
    Version 5.35, 4.79.2.98.2.27. Tagged as 'Kernel-5_35-4_79_2_98_2_27'
    de8e610e
  • Jeffrey Lee's avatar
    Minor MMU_ChangingEntries_WB_CR7_Lx fix · 119585a5
    Jeffrey Lee authored
    Detail:
      s/ARMops - previous version of MMU_ChangingEntries_WB_CR7_Lx would behave improperly if cleaning the last page of the address map by neglecting to flush any more than one TLB entry
    Admin:
      Untested!
    
    
    Version 5.35, 4.79.2.98.2.28. Tagged as 'Kernel-5_35-4_79_2_98_2_28'
    119585a5
  • Jeffrey Lee's avatar
    Add GET Hdr:CPU.Arch to Kernel copy of Copro15ops, so I don't accidentally break the HAL again · 847a1275
    Jeffrey Lee authored
    Version 5.35, 4.79.2.98.2.29. Tagged as 'Kernel-5_35-4_79_2_98_2_29'
    847a1275
  • Jeffrey Lee's avatar
    Fix more issues caused by aborting MVA cache/TLB ops on ARMv7 · 9e6b9350
    Jeffrey Lee authored
    Detail:
      s/ARMops - Fixed an instance of 'invalidate branch predictor entry' that should have been 'invalidate all branch predictors'
      s/ChangeDyn - Avoid cleaning the Nowhere page when reallocating memory, to avoid incurring the performance hit of the abort handler, and to avoid AMBControl screwing things up by mapping in pages that we're trying to modify
      s/VMSAv6 - Move MVA cache/TLB abort handler to before ChocolateAMB code, to ensure AMBControl doesn't try mapping in pages for harmless cache/TLB op aborts. Also tweaked code to be a little bit faster.
    Admin:
      Tested on rev C2 beagleboard. No more lockups when moving screen memory around, for now at least.
    
    
    Version 5.35, 4.79.2.98.2.30. Tagged as 'Kernel-5_35-4_79_2_98_2_30'
    9e6b9350
  • Jeffrey Lee's avatar
    Fix ARMv7 MVA-based cache/TLB op abort handler to be re-entrant · 9aa05feb
    Jeffrey Lee authored
    Detail:
      s/VMSAv6 - The code in DAbPreVeneer that checks for aborting MVA-based cache/TLB ops is now re-entrant.
      This is to cope with the "strange but true" case where a data abort was being triggered by a load/store
      instruction that itself was in an unmapped page.
    Admin:
      Tested on rev C2 beagleboard. Fixes issue with StrongED crashing on load (see http://www.riscosopen.org/forum/forums/5/topics/453)
      Still need to work out why CPU was able to execute code from the unmapped page without triggering a prefetch abort (stale cache entries?)
    
    
    Version 5.35, 4.79.2.98.2.31. Tagged as 'Kernel-5_35-4_79_2_98_2_31'
    9aa05feb
  • Jeffrey Lee's avatar
    Fix some issues preventing the Cortex kernel from being used on non-Cortex machines · e718080c
    Jeffrey Lee authored
    Detail:
      hdr/Options - ARM6support and GetKernelMEMC values are now derived from the value of MEMM_Type
      s/ARMops, s/HAL - Code to detect and handle ARMv7 CPUs is now only enabled when using VMSAv6 MMU model. Saves us from having to deal with lack of myIMB, myDSB, etc. implementations on pre-ARMv6.
      s/HAL - Removed some debug code
      s/NewReset - Fix bug spotted by Tom Walker where R12 wasn't being restored by LookForHALRTC if a non-HAL RTC had already been found
      s/AMBControl/memmap - correct the assert clause that was checking that &FFE are the correct L2PT protection bits for non-VMSAv6 machines
    Admin:
      Tested this kernel on a rev C2 beagleboard & Iyonix softload. Also compiled it into an IOMD ROM, but didn't try running it.
    
    
    Version 5.35, 4.79.2.98.2.32. Tagged as 'Kernel-5_35-4_79_2_98_2_32'
    e718080c
  • Jeffrey Lee's avatar
    Update OS_IICOp to support multiple IIC buses · 327d3980
    Jeffrey Lee authored
    Detail:
      OS_IICOp (and in turn, RISCOS_IICOpV) now treat the top byte of R1 as containing the IIC bus number, allowing multiple buses to be used.
      hdr/KernelWS - Changed workspace a bit so that the kernel can support up to IICBus_Count buses (currently 3), each with its own IICBus_* block.
      s/HAL - Update Reset_IRQ_Handler to cope with interrupts from all IIC buses instead of just the first. Fix/update RISCOS_IICOpV description.
      s/NewIRQs - Update InitialiseIRQ1Vtable to set up interrupt handlers for all IRQ-supporting IIC buses
      s/NewReset - Get rid of the IICAbort call that was just before IICInit. IICInit now calls IICAbort itself.
      s/PMF/IIC - Bulk of the changes. Code now uses the IICBus_ structures instead of the IICStatus and IICType variables. Re-entrancy code has been updated to take into account the possiblity of multiple buses; when OS_IICOp calls are nested, the IIC transfers will be added to bus-specific queues instead of all going in the same queue. However only one queue will be processed at a time.
      s/ChangeDyn - Workspace shuffling means a couple of MOV's needed to be swapped with LDR's when getting immediate constants
    Admin:
      Tested with OMAP & IOMD ROM builds.
      Both high & low-level bus types seem to work OK, along with re-entrancy, both on the same bus and on a different bus.
    
    
    Version 5.35, 4.79.2.98.2.33. Tagged as 'Kernel-5_35-4_79_2_98_2_33'
    327d3980
  • Jeffrey Lee's avatar
    Add OS_ReadSysInfo reason codes 11 (read debug info) & 12 (read extended machine ID) · e42119c8
    Jeffrey Lee authored
    Detail:
      OS_ReadSysInfo 10 is left unimplemented since it's a bit fiddly for us.
      OS_ReadSysInfo 11 is compatible with ROL's implementation, exposing HAL_DebugTX and HAL_DebugRX if the HAL provides them.
      See here for 10,11 docs: http://select.riscos.com/prm/core/osreadsysinfo.html
      OS_ReadSysInfo 12 is a new call to return the 'extended machine ID', to allow the HAL to specify the format & validity of the ID.
      If the HAL responds to the new HAL_ExtMachineID call then it's assumed that no old-style machine ID is present. The Kernel will generate an old-style ID using the contents of the extended ID, and use that with OS_ReadSysInfo 2/5.
      New software should use OS_ReadSysInfo 12 in preference to 2/5.
      s/Middle - Updated OS_ReadSysInfo SWI
      s/PMF/osinit - New old-style machine ID initialisation code
      hdr/HALEntries - Added new HAL_ExtMachineID entry
    Admin:
      Tested on rev A2 BB-xM
    
    
    Version 5.35, 4.79.2.98.2.34. Tagged as 'Kernel-5_35-4_79_2_98_2_34'
    e42119c8
  • Jeffrey Lee's avatar
    Tweak HAL_ExtMachineID to take the buffer pointer in R0 instead of R1 · 23c9ffec
    Jeffrey Lee authored
    Detail:
      s/Middle, s/PMF/osinit - Kernel now passes the buffer pointer to the HAL in R0 instead of R1, for ATPCS compliance.
    Admin:
      Tested on rev A2 BB-xM
    
    
    Version 5.35, 4.79.2.98.2.35. Tagged as 'Kernel-5_35-4_79_2_98_2_35'
    23c9ffec
  • Jeffrey Lee's avatar
    Add ID's for CPUClk HAL device. Trim dead code. · 2f8b5459
    Jeffrey Lee authored
    Detail:
      hdr/HALDevice - Added device type & ID for new CPUClk device, as used by the new OMAP3 HAL/PortableHAL versions.
      s/PMF/osinit - Disable a block of dead code that was getting compiled in.
    Admin:
      Tested on rev C2 BB, rev A2 BB-xM, rev C1 TouchBook
      These changes are needed by the latest OMAP3 HAL & PortableHAL versions.
    
    
    Version 5.35, 4.79.2.98.2.36. Tagged as 'Kernel-5_35-4_79_2_98_2_36'
    2f8b5459
  • Jeffrey Lee's avatar
    Update Cortex branch of kernel to support HALSize env variable. Export C version of hdr.OSEntries. · 1bd9c9e0
    Jeffrey Lee authored
    Detail:
      Makefile - Now exports a C version of hdr.OSEntries, for use by the new HAL USB drivers
      s/GetAll, s/Kernel - The HALSize env variable is now used in place of hard-coded values for the HAL size
      s/HAL - Reset_IRQ_Handler now switches to SVC mode before calling HAL_KbdScanInterrupt, to allow the HAL USB drivers to re-enable interrupts if they wish.
      s/VMSAv6 - Deleted some obsolete definitions
    Admin:
      Tested on rev C2 BB, A2 BB-xM, C1 TouchBook
      Needs latest BuildSys, Env, HdrSrc
    
    
    Version 5.35, 4.79.2.98.2.37. Tagged as 'Kernel-5_35-4_79_2_98_2_37'
    1bd9c9e0
  • Jeffrey Lee's avatar
    Add C version of Hdr.OSEntries to HAL kernel header export · 77d5848c
    Jeffrey Lee authored
    Detail:
      Makefile - now exports a C version of hdr.OSEntries
    Admin:
      Tested in Iyonix ROM softload.
      Needed for latest USB drivers to build.
    
    
    Version 5.35, 4.79.2.112. Tagged as 'Kernel-5_35-4_79_2_112'
    77d5848c
  • Jeffrey Lee's avatar
    Add hdr.Variables to C header export · 819b8458
    Jeffrey Lee authored
    Detail:
      Makefile - Added hdr.Variables to the C header export list
    Admin:
      Fixes build errors with the latest Draw module
    
    
    Version 5.35, 4.79.2.113. Tagged as 'Kernel-5_35-4_79_2_113'
    819b8458
  • Jeffrey Lee's avatar
    Add hdr.Variables to the C header export, fix ARMv6 issues · b8267d5d
    Jeffrey Lee authored
    Detail:
      Makefile - Added hdr.Variables to the C header export list
      hdr/ARMops, s/ARMops - Added ARM1176JZF-S to the list of known CPUs
      s/ARMops - Fix unaligned memory access in ARM_PrintProcessorType
      hdr/Copro15ops, s/ARMops, s/HAL, s/VMSAv6, s/AMBControl/memmap - Fixed all myDSB/myISB/etc. macro instances to specify a temp register, so that they work properly when building an ARMv6 version of the kernel
    Admin:
      Fixes build errors with the latest Draw module.
      Should also allow the kernel to work properly with the new S3C6410 port.
      ARMv6 version builds OK, but no other builds or runtime tests have been made.
    
    
    Version 5.35, 4.79.2.98.2.38. Tagged as 'Kernel-5_35-4_79_2_98_2_38'
    b8267d5d
  • Jeffrey Lee's avatar
    Kernel fixes for ARMv6 · e5f1d1e5
    Jeffrey Lee authored
    Detail:
      hdr/ARMops - Amended ARMvF description to state that an ARMvF CPU can be ARMv6 or ARMv7
      s/ARMops - Move ARM11JZF_S CPUDesc to KnownCPUTable_Fancy, since it's ARMvF. Update ARM_Analyse_Fancy to detect whether ARMv6 or ARMv7 style cache control is in use, and react accordingly.
      s/HAL - Simplified system control register/MMUC initialisation. There are now just two types of setup - one for ARMv3-ARMv5 and one for ARMv6-ARMv7. Modified HAL_InvalidateCache_ARMvF to use the appropriate cache flush instructions depending on whether it's an ARMv6 or ARMv7 style cache.
    Admin:
      S3C6410 and other ARMv6 machines should work now.
      Tested on BB-xM rev A2.
    
    
    Version 5.35, 4.79.2.98.2.39. Tagged as 'Kernel-5_35-4_79_2_98_2_39'
    e5f1d1e5
  • Jeffrey Lee's avatar
    Update list of OS_Memory 9 controllers · e339bdd5
    Jeffrey Lee authored
    Detail:
      s/MemInfo - List of OS_Memory 9 controllers now updated to include details of the ones that ROL are using, along with which numbers should/shouldn't be safe for us to expand into in the future.
    Admin:
      Tested in ROM softload on RiscPC
    
    
    Version 5.35, 4.79.2.114. Tagged as 'Kernel-5_35-4_79_2_114'
    e339bdd5
  • Jeffrey Lee's avatar
    Tweak data abort handler to try and avoid recusrive aborts confusing AMBControl · 8df5d3f5
    Jeffrey Lee authored
    Detail:
      s/VMSAv6 - The code to detect aborting MVA ops now only runs if the aborting instruction wasn't located in application space.
      This is a workaround for an issue where:
      (a) The aborting instruction is in application space
      (b) The aborting instruction is attempting to access memory located in the same page as itself
      (c) That page is not mapped in (despite the fact that code is being executed from it)
      Originally attempting to load the aborting the instruction would have triggered another abort, causing AMBControl to map in the page and resume the first abort handler. The first abort handler would then have determined that it wasn't an MVA op and called AMBControl, only to be told by AMBControl that it wasn't a lazy fixup abort (even though it really was), thus triggering the abort environment handler.
      By ignoring instructions located in application space the second abort is avoided, allowing AMBControl to correctly process the abort.
    Admin:
      Tested on rev A2 BB-xM.
      Fixes issue with DPScan crashing - http://www.freelists.org/post/davidpilling/DPScan-ARMini-crash
      Still need to determine how the ICache is able to become so out of sync with the DCache & page tables.
    
    
    Version 5.35, 4.79.2.98.2.40. Tagged as 'Kernel-5_35-4_79_2_98_2_40'
    8df5d3f5
  • Jeffrey Lee's avatar
    Update the method the Cortex kernel uses to determine the UtilityModule & ROM dates · daa8607f
    Jeffrey Lee authored
    Detail:
      Three main changes:
      * On odd-numbered (i.e. development) versions of the module, the UtilityModule will now take its date from the VersionNum file instead of using a hard-coded date.
      * All build versions now look for the new "extended ROM footer" (as created by romlinker 0.04+) at the end of the ROM image and use it to determine the ROM build date for return by OS_ReadSysInfo 9,2. Failing to find the build date in the footer will cause OS_ReadSysInfo 9,2 to return 0.
      * On odd-numbered versions, OS_Byte 0 will now use the ROM build date (as found in the extended footer) to generate the error block that's returned to the user. This seems OK as the PRM describes OS_Byte 0 as returning the "creation date of the operation system". Plus it's a convenient way of getting the ROM build date into the Switcher, since the switcher uses OS_Byte 0. If the extended footer can't be found (or if the string hasn't been initialised yet, e.g. before Service_PostInit) the code falls back to a hard-coded string containing the date from the VersionNum file.
      File changes:
      Makefile - Updated to not create the obsolete Time+Date file (previously used for the ROM build date)
      Version - Use date from VersionNum file for development builds
      hdr/Options - New UseNewFX0Error variable/option to make it easy to check which OS_Byte 0 variant should be enabled
      hdr/KernelWS - Added new string buffers & extended ROM footer pointer to workspace
      s/Middle - Updated OS_ReadSysInfo 9 code, and added utility functions for searching the extended ROM footer for certain tags
      s/NewReset - Added a couple of calls to initialise the new string buffers just prior to Service_PostInit. This is required since OS_Byte/OS_ReadSysInfo shouldn't enable interrupts, but date conversion relies on the Territory module, which may enable interrupts.
      s/PMF/osbyte - Updated OS_Byte 0 code
    Admin:
      Tested in OMAP ROM, with and without the extended footer present.
    
    
    Version 5.35, 4.79.2.98.2.41. Tagged as 'Kernel-5_35-4_79_2_98_2_41'
    daa8607f
  • Jeffrey Lee's avatar
    Update the method the HAL kernel uses to determine the UtilityModule & ROM dates · e249f5da
    Jeffrey Lee authored
    Detail:
      Three main changes:
      * On odd-numbered (i.e. development) versions of the module, the UtilityModule will now take its date from the VersionNum file instead of using a hard-coded date
      * All build versions now look for the new "extended ROM footer" (as created by romlinker 0.04+) at the end of the ROM image and use it to determine the ROM build date for return by OS_ReadSysInfo 9,2. Failing to find the build date in the footer will cause OS_ReadSysInfo 9,2 to return 0.
      * On odd-numbered versions, OS_Byte 0 will now use the ROM build date (as found in the extended footer) to generate the error block that's returned to the user. This seems OK as the PRM describes OS_Byte 0 as returning the "creation date of the operating system". Plus it's a convenient way of getting the ROM build date into the Switcher, since the switcher uses OS_Byte 0. If the extended footer can't be found (or if the string isn't initialised yet, e.g. before Service_PostInit) the code falls back to a hard-coded string containing the date from the VersionNum file.
      File changes:
      Makefile - Updated to not create the obsolete Time+Date file (previously used for the ROM build date)
      Version - Use date from VersionNum file for development builds
      hdr/Options - New UseNewFX0Error variable/option to make it easy to check which OS_Byte 0 variant should be enabled
      hdr/KernelWS - Added new string buffers & extended ROM footer pointer to workspace
      s/Middle - Updated OS_ReadSysInfo 9 code, and added utility functions for searching the extended ROM footer for certain tags
      s/NewReset - Added a couple of calls to initialise the new string buffers just prior to Service_PostInit. This is required since OS_Byte/OS_ReadSysInfo shouldn't enable interrupts, but date conversion relies on the Territory module, which may enable interrupts.
      s/PMF/osbyte - Updated OS_Byte 0 code
    Admin:
      Tested in Tungsten ROM, with and without the extended footer present.
    
    
    Version 5.35, 4.79.2.115. Tagged as 'Kernel-5_35-4_79_2_115'
    e249f5da
  • Jeffrey Lee's avatar
    Add new GPIO device type & OMAP3 GPIO device ID · e14282c7
    Jeffrey Lee authored
    Detail:
      hdr/HALDevice - Added GPIO device type in the Comms group, and an ID for a generic OMAP3 GPIO device
      hdr/GPIODevice - Definition of GPIO device structure. Currently only used to store the type and revision of the main board, so the GPIO manager module can tailor its features appropriately.
      Makefile - Export hdr/GPIODevice
    Admin:
      Tested on rev A2 BB-xM
    
    
    Version 5.35, 4.79.2.98.2.42. Tagged as 'Kernel-5_35-4_79_2_98_2_42'
    e14282c7
  • Jeffrey Lee's avatar
    Keep hdr/HALDevice & hdr/HALEntries in sync with Cortex branch · afae51e2
    Jeffrey Lee authored
    Detail:
      hdr/HALDevice - Device types & IDs for CPU clock generator and GPIO interface
      hdr/HALEntries - HAL_ExtMachineID entry (but not used by this kernel yet)
    Admin:
      Tungsten ROM built OK, but untested at runtime.
    
    
    Version 5.35, 4.79.2.116. Tagged as 'Kernel-5_35-4_79_2_116'
    afae51e2
  • Jeffrey Lee's avatar
    Update 'perl' to '${PERL}' · 7f86b773
    Jeffrey Lee authored
    Detail:
      Makefile - A couple of makefile rules were invoking perl directly instead of using the more preferential ${PERL}. Fixed.
    Admin:
      Tungsten ROM compiles OK, untested at runtime.
    
    
    Version 5.35, 4.79.2.117. Tagged as 'Kernel-5_35-4_79_2_117'
    7f86b773
  • Jeffrey Lee's avatar
    Bring Cortex kernel branch in line with HAL branch · c79c1310
    Jeffrey Lee authored
    Detail:
      Makefile - Now uses ${PERL} for running perl
      s/Kernel - Now uses correct "Bad OS_PlatformFeatures reason code" error number
      s/MemInfo - Updated list of OS_Memory 9 controllers
    Admin:
      OMAP3 ROM compiles OK; untested at runtime
    
    
    Version 5.35, 4.79.2.98.2.43. Tagged as 'Kernel-5_35-4_79_2_98_2_43'
    c79c1310
  • Jeffrey Lee's avatar
    Add new OS_ReadSysInfo 6 items codes. Change naming of PublicWS values. · b1bc3052
    Jeffrey Lee authored
    Detail:
      s/Middle - Added some new OS_ReadSysInfo 6 items which are needed by the zero page relocation kernel. Also duplicated some existing entries to avoid conflicts with ROL's allocations.
      hdr/OSRSI6, Makefile - New header listing OS_ReadSysInfo 6 items
      hdr/PublicWS - Duplicated the workspace definitions for &0-&4000, but with a 'Legacy_' prefix to their names. Also added some new entries as needed by the zero page relocation kernel. Once existing modules have been updated to use OS_ReadSysInfo & the Legacy_ definitions, the old defs will be removed.
      hdr/KernelWS - Removed 'Export_' prefix from all the exported workspace values, since the kernel can now use the original names directly
      hdr/Options - Dummy HiProcVecs option so merging things will be a bit cleaner
    Admin:
      Tested in ROM softload on Iyonix
    
    
    Version 5.35, 4.79.2.118. Tagged as 'Kernel-5_35-4_79_2_118'
    b1bc3052
  • Jeffrey Lee's avatar
    Add new OS_ReadSysInfo 6 items. Change naming of PublicWS values. · d2c62e16
    Jeffrey Lee authored
    Detail:
      s/Middle - Added some new OS_ReadSysInfo 6 items which are needed by the zero page relocation kernel. Also duplicated some existing entries to avoid conflicts with ROL's allocations.
      hdr/OSRSI6, Makefile - New header listing OS_ReadSysInfo 6 items
      hdr/PublicWS - Duplicated the workspace definitions for &0-&4000, but with a 'Legacy_' prefix to their names. Also added some new entries as needed by the zero page relocation kernel. Once existing modules have been updated to use OS_ReadSysInfo 6 & the Legacy_ definitions, the old defs will be removed.
      hdr/KernelWS - Removed 'Export_' prefix from all the exported workspace values, since the kernel can now use the original names directly
      hdr/Options - Dummy HiProcVecs option so merging things will be a bit cleaner
    Admin:
      Tested on rev A2 BB-xM
    
    
    Version 5.35, 4.79.2.98.2.44. Tagged as 'Kernel-5_35-4_79_2_98_2_44'
    d2c62e16
  • Jeffrey Lee's avatar
    Correct new OS_ReadSysInfo 6 item numbers · e4f162a3
    Jeffrey Lee authored
    Detail:
      s/Middle - Correct the actual item numbers to match those defined in the header 9and those used in the HAL branch)
      hdr/OSRSI6 - Corrected ROM version numbere where the new items are available from
    Admin:
      Untested!
    
    
    Version 5.35, 4.79.2.98.2.45. Tagged as 'Kernel-5_35-4_79_2_98_2_45'
    e4f162a3
  • Jeffrey Lee's avatar
    Correct version number in header comment · 61428ee7
    Jeffrey Lee authored
    Detail:
      hdr/OSRSI6 - Corrected RO version number from 5.19 to 5.17
    Admin:
      Untested, but testing shouldn't be needed anyway
    
    
    Version 5.35, 4.79.2.119. Tagged as 'Kernel-5_35-4_79_2_119'
    61428ee7
  • Jeffrey Lee's avatar
    Misc kernel updates · 6f468193
    Jeffrey Lee authored
    Detail:
      hdr/ARMops - Reserve OS_PlatformFeatures 0 bit 20 for indicating whether high processor vectors are in use
      s/Kernel - Add local definitions of BYTEWS, LDROSB, STROSB, VDWS macros (previously in Hdr:Macros)
      s/MoreComms - Fix potential buffer overflow when filling error buffer (although GSTrans shouldn't overflow the buffer in the first place?)
    Admin:
      Tested on rev A2 BB-xM
      Requires HdrSrc 1.86
    
    
    Version 5.35, 4.79.2.98.2.46. Tagged as 'Kernel-5_35-4_79_2_98_2_46'
    6f468193
  • Jeffrey Lee's avatar
    Merge over some changes from the Cortex branch · fef39aba
    Jeffrey Lee authored
    Detail:
      hdr/ARMops - Reserve OS_PlatformFeatures 0 bit 20 for indicating whether high processor vectors are in use
      s/Kernel - Add local definitions of BYTEWS, LDROSB, STROSB, VDWS macros (previously in Hdr:Macros)
      s/MoreComms - Fix potential buffer overflow when filling error buffer (although GSTrans shouldn't overflow the buffer in the first place?)
      s/Arthur2 - GSRead number detection fix
      s/ArthurSWIs - Updated OS_ReadUnsigned to support reading 64bit numbers
      Docs/ReadUnsigned - Docs for the updated OS_ReadUnsigned interface
    Admin:
      Untested!
      Needs HdrSrc 1.86
    
    
    Version 5.35, 4.79.2.120. Tagged as 'Kernel-5_35-4_79_2_120'
    fef39aba
  • Jeffrey Lee's avatar
    Add ESC_Status to list of OS_ReadSysInfo 6 items · 26a09556
    Jeffrey Lee authored
    Detail:
      hdr/OSRSI6, s/Middle - Added ESC_Status to the list of items that OS_ReadSysInfo 6 exports
    Admin:
      Tested on rev A2 BB-xM
    
    
    Version 5.35, 4.79.2.98.2.47. Tagged as 'Kernel-5_35-4_79_2_98_2_47'
    26a09556
  • Jeffrey Lee's avatar
    Add ESC_Status to list of OS_ReadSysInfo 6 items · 37162926
    Jeffrey Lee authored
    Detail:
      hdr/OSRSI6, s/Middle - Added ESC_Status to the list of items that OS_ReadSysInfo 6 exports
    Admin:
      Tested in ROM softload on Iyonix
    
    
    Version 5.35, 4.79.2.121. Tagged as 'Kernel-5_35-4_79_2_121'
    37162926
  • Jeffrey Lee's avatar
    Add zero page relocation support · 2247d8e9
    Jeffrey Lee authored
    Detail:
      A whole mass of changes to add high processor vectors + zero page relocation support to the Cortex branch of the kernel
      At the moment the code can only cope with two ZeroPage locations, &0 and &FFFF0000. But with a bit more tweaking those restrictions can probably be lifted, allowing ZeroPage to be hidden at almost any address (assuming it's fixed at compile time). If I've done my job right, these restrictions should all be enforced by asserts.
      There's a new option, HiProcVecs, in hdr/Options to control whether high processor vectors are used. When enabling it and building a ROM, remember:
      * FPEmulator needs to be built with the FPEAnchor=High option specified in the components file (not FPEAnchorType=High as my FPEmulator commit comments suggested)
      * ShareFS needs unplugging/removing since it can't cope with it yet
      * Iyonix users will need to use the latest ROOL boot sequence, to ensure the softloaded modules are compatible (OMAP, etc. don't really softload much so they're OK with older sequences)
      * However VProtect also needs patching to fix a nasty bug there - http://www.riscosopen.org/tracker/tickets/294
      The only other notable thing I can think of is that the ProcessTransfer code in s/ARM600 & s/VMSAv6 is disabled if high processor vectors are in use (it's fairly safe to say that code is obsolete in HAL builds anyway?)
      Fun challenge for my successor: Try setting ZeroPage to &FFFF00FF (or similar) so its value can be loaded with MVN instead of LDR. Then use positive/negative address offsets to access the contents.
      File changes:
      - hdr/ARMops - Modified ARMop macro to take the ZeroPage pointer as a parameter instead of 'zero'
      - hdr/Copro15ops - Corrected $quick handling in myISB macro
      - hdr/Options - Added ideal setting for us to use for HiProcVecs
      - s/AMBControl/allocate, s/AMBControl/growp, s/AMBControl/mapslot, s/AMBControl/memmap, s/AMBControl/service, s/AMBControl/shrinkp, s/Arthur2, s/Arthur3, s/ArthurSWIs, s/ChangeDyn, s/ExtraSWIs, s/HAL, s/HeapMan, s/Kernel, s/MemInfo, s/Middle, s/ModHand, s/MoreSWIs, s/MsgCode, s/NewIRQs, s/NewReset, s/Oscli, s/PMF/buffer, s/PMF/IIC, s/PMF/i2cutils, s/PMF/key, s/PMF/mouse, s/PMF/osbyte, s/PMF/oseven, s/PMF/osinit, s/PMF/osword, s/PMF/oswrch, s/SWINaming, s/Super1, s/SysComms, s/TickEvents, s/Utility, s/vdu/vdu23, s/vdu/vdudriver, s/vdu/vdugrafl, s/vdu/vdugrafv, s/vdu/vdupalxx, s/vdu/vdupointer, s/vdu/vduswis, s/vdu/vduwrch - Lots of updates to deal with zero page relocation
      - s/ARM600 - UseProcessTransfer option. Zero page relocation support. Deleted pre-HAL ClearPhysRAM code to tidy the file up a bit.
      - s/ARMops - Zero page relocation support. Set CPUFlag_HiProcVecs when high vectors are in use.
      - s/KbdResPC - Disable compilation of dead code
      - s/VMSAv6 - UseProcessTransfer option. Zero page relocation support.
    Admin:
      Tested with OMAP & Iyonix ROM softloads, both with high & low zero page.
      High zero page hasn't had extensive testing, but boot sequence + ROM apps seem to work.
    
    
    Version 5.35, 4.79.2.98.2.48. Tagged as 'Kernel-5_35-4_79_2_98_2_48'
    2247d8e9
  • Jeffrey Lee's avatar
    Improve Reset_IRQ_Handler · 20c93a96
    Jeffrey Lee authored
    Detail:
      s/HAL - Reset_IRQ_Handler now uses HAL_IRQSource to determine the cause of the interrupt, using that value to work out which IIC bus (if any) generated the IRQ. If it's unrecognised it passes it to HAL_KbdScanInterrupt, and if that fails to do anything it'll disable the IRQ.
      This aims to fix the spurious "No XStart!" debug spam that the OMAP IIC drivers produce when the keyboard scan is running, and to fix the potential IIC breakage that could occur by the IIC code trying to clear the non-existant interrupt.
      Note that behaviour of HAL_KbdScanInterrupt has now been changed; it now accepts the device number in a1, and is expected to return either -1 (if the interrupt was handled) or the device number given as input (if the interrupt wasn't handled, e.g. not from a device managed by the keyboard scan code).
    Admin:
      Tested on rev C2 BB
    
    
    Version 5.35, 4.79.2.98.2.49. Tagged as 'Kernel-5_35-4_79_2_98_2_49'
    20c93a96
  • Ben Avison's avatar
    Kernel updates to support Cortex-A9 CPUs · 0ff2f2dd
    Ben Avison authored
    Detail:
      hdr.ARMops
        added Cortex_A9
      hdr.HALDevice
        added OMAP4 specific device IDs
      hdr.KernelWS
        changed definition of DefIRQ1Vspace for M_CortexA9
      s.ARMops
        added CortexA9 specific code for enabling L2 cache
        added CPUDesc Cortex_A9
      s.NewIRQs
        added CortexA9 specific definition of MaxInterrupts
      s.NewReset
        added M_CortexA9 options
        line 1444: corrected typo
        line 187: commented out unnecessary operation
    Admin:
      Submission from Willi Theiß
    
    Version 5.35, 4.79.2.98.2.50. Tagged as 'Kernel-5_35-4_79_2_98_2_50'
    0ff2f2dd
  • Jeffrey Lee's avatar
    ARMv7 fixes · 2dfd92c1
    Jeffrey Lee authored
    Detail:
      hdr/Copro15ops:
        - Fixed incorrect encodings of ISH/ISHST variants of DMB/DSB instructions
      s/ARMops, s/HAL, hdr/KernelWS:
        - Replace the ARMv7 cache maintenance code with the example code from the ARMv7 ARM. This allows it to deal with caches with non power-of-two set/way counts, and caches with only one way.
        - Fixed Analyse_WB_CR7_Lx to use the cache level ID register to work out how many caches to query instead of just looking for a 0 result from CSSIDR.
        - Also only look for 7 cache levels, since level 8 doesn't exist according to the ARMv7 ARM.
      s/NewReset:
        - Removed some incorrect/misleading debug output
    Admin:
      Tested on rev A2 BB-xM
    
    
    Version 5.35, 4.79.2.98.2.51. Tagged as 'Kernel-5_35-4_79_2_98_2_51'
    2dfd92c1
  • Jeffrey Lee's avatar
    Fix Cache_InvalidateAll_WB_CR7_Lx to do what it says on the tin · af172483
    Jeffrey Lee authored
    Detail:
      s/ARMops - My previous checkin mistakenly changed Cache_InvalidateAll_WB_CR7_Lx so that it cleans and invalidates the cache instead of just invalidating it. This fixes that.
      Also fixed a warning caused by the trailing space going AWOL from the 'cache type register fields' comment.
    Admin:
      Tested on rev A2 BB-xM
    
    
    Version 5.35, 4.79.2.98.2.52. Tagged as 'Kernel-5_35-4_79_2_98_2_52'
    af172483
  • Jeffrey Lee's avatar
    Fix objasm 4 warnings · 6d052230
    Jeffrey Lee authored
    Detail:
      s/Arthur3, s/ChangeDyn, s/HAL, s/HeapMan, s/Middle, s/MoreSWIs, s/NewIRQs, s/Utility, s/VMSAv6, s/PMF/key, s/PMF/osbyte, s/PMF/osword, s/vdu/vdudecl, s/vdu/vdudriver, s/vdu/vduplot, s/vdu/vduwrch - Tweaked lots of LDM/STM instructions in order to get rid of the depracation/performance warnings
    Admin:
      Tested on rev A2 BB-xM
    
    
    Version 5.35, 4.79.2.98.2.53. Tagged as 'Kernel-5_35-4_79_2_98_2_53'
    6d052230
  • Ben Avison's avatar
    Added definitions to Hdr:HALDevice required by SDIODriver · e4f67669
    Ben Avison authored
    Version 5.35, 4.79.2.98.2.54. Tagged as 'Kernel-5_35-4_79_2_98_2_54'
    e4f67669
  • Ben Avison's avatar
    Resync Hdr:HALDevice on HAL branch (nominally the master copy) with the Cortex branch · 987a3ec3
    Ben Avison authored
    Version 5.35, 4.79.2.122. Tagged as 'Kernel-5_35-4_79_2_122'
    987a3ec3
  • Jeffrey Lee's avatar
    Merge Cortex kernel into HAL branch · 50f95feb
    Jeffrey Lee authored
    Detail:
      This is a full merge of the Cortex kernel back into the HAL branch. Since the Cortex kernel is/was just a superset of the HAL branch, at this point in time both branches are identical.
      Main features the HAL branch gains from this merge:
      - ARMv6/ARMv7 support
      - High processor vectors/zero page relocation support
      - objasm 4 warning fixes
      - Improved HAL related functionality:
        - Support for HAL-driven RTCs instead of kernel-driven IIC based ones
        - Support for arbitrary size machine IDs
        - Support for multiple IIC busses
        - Support for any HAL size, instead of hardcoded 64k size
        - Probably some other stuff I've forgotten
      - Probably a few bug fixes here and there
    Admin:
      Tested on BB-xM & Iyonix.
      Was successfully flashed to ROM on an Iyonix to test the Cortex branch implementation of the 2010 RTC bug fix.
      IOMD build untested - but has been known to work in the past.
    
    
    Version 5.35, 4.79.2.123. Tagged as 'Kernel-5_35-4_79_2_123'
    50f95feb
OS_ReadUnsigned
(SWI &21)
On entry
R0 bits 0-7 = base in the range 2-36 (else 10 assumed)
bits 8-27 reserved, should be 0
bit 28 set => read a 64-bit value to r2,r3
bit 29 set => restrict range to 0 - R2 (or if bit 28 set, R2+(R3<<32))
bit 30 set => restrict range to 0- 255
bit 31 set => check terminator is a control character or space
R1 = pointer to string
R2 = least significant word of maximum value if R0 bit 29 set
R3 = most significant word of maximum value if R0 bits 28 and 29 both set
R4 = &45444957 ("WIDE") if this API applies, otherwise see PRM 1-448
On exit
R0 preserved
R1 = pointer to terminator character
R2 = least significant word of value
R3 = most significant word of value if R0 bit 28 set on entry
R4 = bitmask of R0 flags understood by current kernel (currently &F0000000)
Suggestions for future flag uses:
* permit "0x" (hexadecimal), "0" (octal) and "0b" or "%" (binary) prefixes
* signed numbers
* floating point numbers
* negative bases
......@@ -38,9 +38,10 @@ LD = link
CP = copy
RM = remove
WIPE = -wipe
PERL = do <Perl$Dir>.perl
CCFLAGS = -c -depend !Depend -IC:
ASFLAGS = -depend !Depend ${THROWBACK} -Stamp -quit -To $@ -From
ARMASMFLAGS = -depend !Depend -g ${THROWBACK} -cpu 5TE
ARMASMFLAGS = -depend !Depend -g ${THROWBACK}
CPFLAGS = ~cfr~v
WFLAGS = ~cfr~v
......@@ -64,10 +65,17 @@ EXPORTS = ${EXP_HDR}.EnvNumbers \
${EXP_HDR}.VduExt \
${EXP_HDR}.HALEntries \
${EXP_HDR}.HALDevice \
${EXP_HDR}.RTCDevice \
${EXP_HDR}.VideoDevice \
${EXP_HDR}.GPIODevice \
${EXP_HDR}.OSEntries \
${EXP_HDR}.OSRSI6 \
${C_EXP_HDR}.RISCOS \
${C_EXP_HDR}.HALEntries \
${C_EXP_HDR}.HALDevice
${C_EXP_HDR}.HALDevice \
${C_EXP_HDR}.OSEntries \
${C_EXP_HDR}.Variables \
${C_EXP_HDR}.OSRSI6
#
# Generic rules:
......@@ -129,12 +137,11 @@ ${GPADBG}: ${AIFDBG}
s.TMOSHelp: ${TOKENS} HelpStrs
${TOKENISE} ${TOKENS} HelpStrs $@
s.Time+Date:
@echo |IGBLS Builddate|JBuilddate SETS "<Sys$Date> <Sys$Year>.<Sys$Time>" |J|IEND { > s.Time+Date }
settype s.Time+Date FFF
#s.Time+Date:
# @echo |IGBLS Builddate|JBuilddate SETS "<Sys$Date> <Sys$Year>.<Sys$Time>" |J|IEND { > s.Time+Date }
# settype s.Time+Date FFF
o.GetAll: s.TMOSHelp \
s.Time+Date
o.GetAll: s.TMOSHelp
#
# Exported interface headers
......@@ -163,25 +170,49 @@ ${EXP_HDR}.HALEntries: hdr.HALEntries
${EXP_HDR}.HALDevice: hdr.HALDevice
${CP} hdr.HALDevice $@ ${CPFLAGS}
${EXP_HDR}.RTCDevice: hdr.RTCDevice
${CP} hdr.RTCDevice $@ ${CPFLAGS}
${EXP_HDR}.OSEntries: hdr.OSEntries
${CP} hdr.OSEntries $@ ${CPFLAGS}
${EXP_HDR}.VideoDevice: hdr.VideoDevice
${CP} hdr.VideoDevice $@ ${CPFLAGS}
${EXP_HDR}.GPIODevice: hdr.GPIODevice
${CP} hdr.GPIODevice $@ ${CPFLAGS}
${EXP_HDR}.OSRSI6: hdr.OSRSI6
${CP} hdr.OSRSI6 $@ ${CPFLAGS}
${C_EXP_HDR}.RISCOS: hdr.RISCOS
${MKDIR} ${C_EXP_HDR}
perl Build:Hdr2H hdr.RISCOS $@
${PERL} Build:Hdr2H hdr.RISCOS $@
${C_EXP_HDR}.HALEntries: hdr.HALEntries
${MKDIR} ${C_EXP_HDR}
perl Build:Hdr2H hdr.HALEntries $@
${PERL} Build:Hdr2H hdr.HALEntries $@
${C_EXP_HDR}.HALDevice: o.Global.h.HALDevice h.HALDevice
${CP} h.HALDevice $@ ${CPFLAGS}
print o.Global.h.HALDevice { >> $@ }
${C_EXP_HDR}.OSEntries: hdr.OSEntries
${MKDIR} ${C_EXP_HDR}
${PERL} Build:Hdr2H hdr.OSEntries $@
${C_EXP_HDR}.Variables: hdr.Variables
${MKDIR} ${C_EXP_HDR}
${PERL} Build:Hdr2H hdr.Variables $@
${C_EXP_HDR}.OSRSI6: hdr.OSRSI6
${MKDIR} ${C_EXP_HDR}
${PERL} Build:Hdr2H hdr.OSRSI6 $@
o.Global.h.HALDevice: hdr.HALDevice
${MKDIR} o.Global.h
dir o
perl Build:Hdr2H ^.hdr.HALDevice Global.h.HALDevice
${PERL} Build:Hdr2H ^.hdr.HALDevice Global.h.HALDevice
back
BBETYPE = kernel
......
......@@ -14,14 +14,19 @@ Version SETA Module_Version
VString SETS Module_MajorVersion
Date SETS Module_Date ; version for STB/NC OS
|
Version SETA 514
VString SETS "5.14"
Date SETS "03 Dec 2008" ; version for RISC OS on desktop computers
Version SETA 517
VString SETS "5.17"
[ (Version :AND: 1) = 1
Date SETS Module_Date ; Odd-numbered (i.e. development) build, use
; date of last source checkin
|
Date SETS "19 Jan 2010" ; version for RISC OS on desktop computers
; you may also wish to update the welcome
; and OS information dialogue box templates
; in the sources for Desktop and Switcher
; (especially for year change)
]
]
END
......@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.98"
Module_Date SETS "22 Dec 2008"
Module_ApplicationDate SETS "22-Dec-08"
Module_MinorVersion SETS "4.79.2.123"
Module_Date SETS "26 Nov 2011"
Module_ApplicationDate SETS "26-Nov-11"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.98)"
Module_HelpVersion SETS "5.35 (22 Dec 2008) 4.79.2.98"
Module_FullVersion SETS "5.35 (4.79.2.123)"
Module_HelpVersion SETS "5.35 (26 Nov 2011) 4.79.2.123"
END
......@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.98
#define Module_Date_CMHG 22 Dec 2008
#define Module_MinorVersion_CMHG 4.79.2.123
#define Module_Date_CMHG 26 Nov 2011
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.98"
#define Module_Date "22 Dec 2008"
#define Module_MinorVersion "4.79.2.123"
#define Module_Date "26 Nov 2011"
#define Module_ApplicationDate "22-Dec-08"
#define Module_ApplicationDate "26-Nov-11"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.98)"
#define Module_HelpVersion "5.35 (22 Dec 2008) 4.79.2.98"
#define Module_FullVersion "5.35 (4.79.2.123)"
#define Module_HelpVersion "5.35 (26 Nov 2011) 4.79.2.123"
#define Module_LibraryVersionInfo "5:35"
......@@ -32,7 +32,8 @@ struct device
int32_t (*Sleep)(struct device *, int32_t state);
int32_t devicenumber;
bool (*TestIRQ)(struct device *);
uint32_t reserved2[2];
void (*ClearIRQ)(struct device *);
uint32_t reserved2[1];
};
#endif
......
......@@ -13,12 +13,17 @@
; limitations under the License.
;
ARMv3 * 0
ARMv4 * 1
ARMv4T * 2
ARMv5 * 3
ARMv5T * 4
ARMv5TE * 5
ARMv3 * 0
ARMv4 * 1
ARMv4T * 2
ARMv5 * 3
ARMv5T * 4
ARMv5TE * 5
ARMv5TEJ * 6
ARMv6 * 7
ARMvF * &F ; 'Fancy' ARM that describes its features in the feature registers.
; Generally this implies ARMv7+, but there are also a few ARMv6 CPUs with this value
; (e.g. ARM1176JZF-S)
^ 0
ARM600 # 1
......@@ -37,6 +42,9 @@ ARM920T # 1
ARM922T # 1
X80200 # 1
X80321 # 1
Cortex_A8 # 1
Cortex_A9 # 1
ARM1176JZF_S # 1
ARMunk * 255
; These flags are stored in ProcessorFlags and returned by OS_PlatformFeatures 0 (Read code features)
......@@ -57,30 +65,31 @@ CPUFlag_NoWBDrain * 1:SHL:16 ; CPU does not support Drain Wri
CPUFlag_AbortRestartBroken * 1:SHL:17 ; Aborts do not correctly follow documented abort model
CPUFlag_XScale * 1:SHL:18 ; it's an XScale, so weird debug etc
CPUFlag_XScaleJTAGconnected * 1:SHL:19 ; JTAG has been connected
CPUFlag_HiProcVecs * 1:SHL:20 ; High processor vectors are in use
; The macro to do an ARM operation. All ARM operations are expected
; to corrupt a1 only
; This macro corrupts ip unless $zero reg is supplied
; This macro corrupts ip unless $zeropage reg is supplied
MACRO
ARMop $op, $cond, $tailcall, $zero
[ "$zero" = ""
MOV$cond ip, #ZeroPage
ARMop $op, $cond, $tailcall, $zeropage
[ "$zeropage" = ""
LDR$cond ip, =ZeroPage
]
[ "$tailcall" = ""
MOV$cond lr, pc
]
[ "$zero" = ""
[ "$zeropage" = ""
LDR$cond pc, [ip, #Proc_$op]
|
LDR$cond pc, [$zero, #Proc_$op]
LDR$cond pc, [$zeropage, #Proc_$op]
]
MEND
MACRO
ChangedProcVecs $tmp
[ XScaleJTAGDebug
MOV $tmp, #0
LDR $tmp, =ZeroPage
LDR $tmp, [$tmp, #ProcessorFlags]
TST $tmp, #CPUFlag_XScaleJTAGconnected
BEQ %FT01
......
......@@ -22,6 +22,11 @@
; 07-10-96 MJS Updated for proper ARM 810 support (not needed for RO 3.70)
; 10-03-97 MJS A few additions for chocolate flavour screen handling (possible
; Domain and FSR register use) in Phoebe OS
; 05-02-09 JL Disable ARM_flush_* when compiling OS for HAL. OS now supports
; too many ARM versions for cache/TLB flushing to be implemented in
; simple macros.
GET Hdr:CPU.Arch
ARM_config_cp CP 15 ;coprocessor number for configuration control
......@@ -51,7 +56,7 @@ ARM8_CTC_reg CN 15 ;Clock and test configuration
ARMA_TCI_reg CN 15 ;Test,Clock and Idle control
;so that AASM will accept the general value for MCR CRm field
;so that bleedin' AASM will accept the general value for MCR CRm field
C0 CN 0
C1 CN 1
C2 CN 2
......@@ -161,6 +166,7 @@ C15 CN 15
TEQ$cond $tmp,#1
MEND
[ :LNOT: HAL
;flush whole TLB (both data and instruction for StrongARM)
;trashes $temp
MACRO
......@@ -200,6 +206,7 @@ C15 CN 15
MCREQ ARM_config_cp,0,R0,ARM8A_cache_reg,C7,0
MCREQ ARM_config_cp,0,R0,ARM8A_TLB_reg,C7,0
MEND
]
;
; -------------- ARM 6,7 only --------------------------------------------
......@@ -545,5 +552,139 @@ C15 CN 15
MCR$cond ARM_config_cp,0,R0,ARMA_TCI_reg,C2,2
MEND
;
; -------------- Additional ARMv7 stuff -----------------------------------
;
; Provided here are ISB, DSB and DMB macros suitable for ARMv6+
; Although ARMv4 & v5 do provide CP15 ops that are compatible with the ARMv6 ops, it's implementation defined whether each processor implements the ops or not (and the ops are unpredictable if unimplemented)
; So to play it safe these macros will complain if used on pre-ARMv6
; For all the macros, set the $quick to something if the value of $temp is
; already zero (this will cut out a pointless MOV)
; Instruction Synchronisation Barrier - required on ARMv6+ to ensure the effects of the following are visible to following instructions:
; * Completed cache, TLB & branch predictor maintenance operations
; * CP14/CP15 writes
MACRO
myISB $cond,$temp,$option,$quick
[ NoARMv6
! 1, "Don't know what to do on pre-ARMv6!"
|
[ NoARMv7
; ARMv6, use legacy MCR op
[ "$quick"=""
MOV$cond $temp,#0
]
MCR$cond p15,0,$temp,c7,c5,4
|
; ARMv7+, use ISB instruction (saves on temp register, but instruction is unconditional)
; Shouldn't hurt too much if we just ignore the condition code
DCI &F57FF06F ; ISB SY
]
]
MEND
; Data Synchronisation Barrier - aka drain write buffer/data write barrier. Stalls pipeline until all preceeding memory accesses (including cache/TLB/BTC ops complete.
MACRO
myDSB $cond,$temp,$option,$quick
[ NoARMv6
! 1, "Don't know what to do on pre-ARMv6!"
|
[ NoARMv7
; pre-ARMv7, use legacy MCR op
[ "$quick"=""
MOV$cond $temp,#0
]
MCR$cond p15,0,$temp,c7,c10,4
|
; ARMv7+, use DSB instruction
[ "$option"="SY" :LOR: "$option"=""
DCI &F57FF04F ; DSB SY
|
[ "$option"="ST" :LOR: "$option"="SYST"
DCI &F57FF04E ; DSB ST
|
[ "$option"="ISH"
DCI &F57FF04B ; DSB ISH
|
[ "$option"="ISHST"
DCI &F57FF04A ; DSB ISHST
|
[ "$option"="NSH"
DCI &F57FF047 ; DSB NSH
|
[ "$option"="NSHST"
DCI &F57FF046 ; DSB NSHST
|
[ "$option"="OSH"
DCI &F57FF043 ; DSB OSH
|
[ "$option"="OSHST"
DCI &F57FF042 ; DSB OSHST
|
! 1, "Unrecognised DSB option"
]
]
]
]
]
]
]
]
]
]
MEND
; Data Memory Barrier - More lightweight DSB, ensures memory accesses behave correctly without stalling the pipeline to wait for preceeding accesses to complete. I.e. it's only good for synchronising load/store instructions.
MACRO
myDMB $cond,$temp,$option,$quick
[ NoARMv6
! 1, "Don't know what to do on pre-ARMv6!"
|
[ NoARMv7
; ARMv6, use legacy MCR op
[ "$quick"=""
MOV$cond $temp,#0
]
MCR$cond p15,0,$temp,c7,c10,5
|
; ARMv7+, use DMB instruction
[ "$option"="SY" :LOR: "$option"=""
DCI &F57FF05F ; DMB SY
|
[ "$option"="ST" :LOR: "$option"="SYST"
DCI &F57FF05E ; DMB ST
|
[ "$option"="ISH"
DCI &F57FF05B ; DMB ISH
|
[ "$option"="ISHST"
DCI &F57FF05A ; DMB ISHST
|
[ "$option"="NSH"
DCI &F57FF057 ; DMB NSH
|
[ "$option"="NSHST"
DCI &F57FF056 ; DMB NSHST
|
[ "$option"="OSH"
DCI &F57FF053 ; DMB OSH
|
[ "$option"="OSHST"
DCI &F57FF052 ; DMB OSHST
|
! 1, "Unrecognised DMB option"
]
]
]
]
]
]
]
]
]
]
MEND
END
; Copyright 2011 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; Public interface of GPIO HAL devices
GET hdr:HALDevice
OldOpt SETA {OPT}
OPT OptNoList+OptNoP1List
[ :LNOT: :DEF: Included_Hdr_GPIODevice
GBLL Included_Hdr_GPIODevice
Included_Hdr_GPIODevice SETL {TRUE}
; Device for GPIO devices
; This device just reports the board type and revision, so that the GPIO manager
; knows how everything is set up and which bits should be off-limits.
^ 0
# HALDeviceSize
HALDevice_GPIOType # 4
HALDevice_GPIORevision # 4
HALDevice_GPIO_Size * :INDEX: @
; Type & revision values specific to HALDeviceID_GPIO_OMAP3:
^ 0
GPIOType_OMAP3_BeagleBoard # 1 ; It's a BeagleBoard or BB-xM
GPIOType_OMAP3_DevKit8000 # 1 ; It's a DevKit 8000
GPIOType_OMAP3_IGEPv2 # 1 ; It's an IGEP v2
; BeagleBoard revision values:
^ 0
; BeagleBoard:
GPIORevision_BeagleBoard_AB # 1 ; Rev A or B
GPIORevision_BeagleBoard_C123 # 1 ; Rev C1, C2 or C3
GPIORevision_BeagleBoard_C4 # 1 ; Rev C4
; BeagleBoard-xM:
GPIORevision_BeagleBoard_xMA # 1 ; Rev A
GPIORevision_BeagleBoard_xMB # 1 ; Rev B
GPIORevision_BeagleBoard_xMC # 1 ; Rev C
; DevKit revision values:
^ 0
GPIORevision_DevKit8000_Unknown # 1
; IGEP revision values:
^ 0
GPIORevision_IGEPv2_BC # 1 ; Rev B or C (B-compatible)
GPIORevision_IGEPv2_C # 1 ; Rev C (not a B-compatible one)
]
OPT OldOpt
END
......@@ -37,7 +37,8 @@ HALDevice_Reset # 4
HALDevice_Sleep # 4
HALDevice_Device # 4
HALDevice_TestIRQ # 4
HALDevice_Reserved2 # 8
HALDevice_ClearIRQ # 4
HALDevice_Reserved2 # 4
HALDeviceSize * :INDEX: @
......@@ -56,11 +57,19 @@ HALDeviceSysPeri_IntC # 1 ; Interrupt controller
HALDeviceSysPeri_DMAC # 1 ; DMA controller
HALDeviceSysPeri_DMAB # 1 ; DMA channel - buffer type
HALDeviceSysPeri_DMAL # 1 ; DMA channel - list type
HALDeviceSysPeri_RTC # 1 ; RTCDevice
HALDeviceSysPeri_CPUClk # 1 ; CPU clock generator
HALDeviceType_Comms * 4 :SHL: 8
^ 1
HALDeviceComms_UART # 1 ; UART
HALDeviceComms_EtherNIC # 1 ; Ethernet NIC
HALDeviceComms_GPIO # 1 ; GPIO interface
HALDeviceType_ExpCtl * 5 :SHL: 8
^ 1
HALDeviceExpCtl_SDIO # 1 ; SD/SDIO host controller
; things like USB, FireWire, SATA, SAS controllers might go here
HALDeviceBus_Pro * 0 :SHL: 28
......@@ -76,6 +85,7 @@ HALDeviceSysBus_PXBus * 2 :SHL: 24
HALDeviceBus_Peri * 2 :SHL: 28
HALDevicePeriBus_APB * 0 :SHL: 24
HALDevicePeriBus_GPMC * 1 :SHL: 24
HALDeviceBus_Exp * 3 :SHL: 28
......@@ -86,25 +96,61 @@ HALDeviceExpBus_PCI * 2 :SHL: 24
HALDeviceBus_Ser * 4 :SHL: 28
HALDeviceSerBus_ACLink * 0 :SHL: 24
HALDeviceSerBus_IIC * 1 :SHL: 24
HALDeviceBus_Interconnect * 5 :SHL: 28 ; Not really a bus type, but the OMAP stuff had to go somewhere!
HALDeviceInterconnectBus_L3 * 0 :SHL: 24
HALDeviceInterconnectBus_L4 * 1 :SHL: 24
^ 0
HALDeviceID_AudC_M5451 # 1
HALDeviceID_AudC_TPS65950 # 1
HALDeviceID_AudC_TWL6040 # 1
^ 0
HALDeviceID_Mixer_STAC9750 # 1
HALDeviceID_Mixer_TPS65950 # 1
HALDeviceID_Mixer_TWL6040 # 1
^ 0
HALDeviceID_DMAC_M1535 # 1
HALDeviceID_DMAC_M5229 # 1
HALDeviceID_DMAC_OMAP3 # 1
HALDeviceID_DMAC_OMAP4 # 1
^ 0
HALDeviceID_DMAB_M1535 # 1
HALDeviceID_DMAB_OMAP3 # 1
HALDeviceID_DMAB_OMAP4 # 1
^ 0
HALDeviceID_DMAL_M5229 # 1
]
^ 0
HALDeviceID_RTC_TPS65950 # 1
HALDeviceID_RTC_TWL6030 # 1
^ 0
HALDeviceID_CPUClk_OMAP3 # 1
HALDeviceID_CPUClk_OMAP4 # 1
^ 0
HALDeviceID_VDU_OMAP3 # 1
HALDeviceID_VDU_OMAP4 # 1
^ 0
HALDeviceID_EtherNIC_SMSC9221 # 1
HALDeviceID_EtherNIC_DM9000 # 1
^ 0
HALDeviceID_GPIO_OMAP3 # 1
HALDeviceID_GPIO_OMAP4 # 1
^ 0
HALDeviceID_SDIO_SDHCI # 1
] ; Included_Hdr_HALDevice
OPT OldOpt
END
......@@ -168,6 +168,8 @@ EntryNo_HAL_Video_IICOp # 1
EntryNo_HAL_TimerIRQClear # 1
EntryNo_HAL_TimerIRQStatus # 1
EntryNo_HAL_ExtMachineID # 1 ; ReadSysInfo 10
KnownHALEntries # 0 ; Used inside Kernel
; Various flags and constants
......
......@@ -231,7 +231,11 @@ DANode_NodeSize # 0
; The addresses below are only temporary; eventually most of them will be allocated at run time (we hope!)
[ HiProcVecs
ZeroPage * &FFFF0000
|
ZeroPage * &00000000
]
[ HAL
; Sort out 26/32 bit versions
......@@ -819,20 +823,18 @@ TextExpandArea_Size * (8*1024)
# 2*4 ; SPARE (avoiding changes of exported addresses for now)
;ScreenBlankFlag # 1 ; 0 => unblanked, 1 => blanked
ScreenBlankFlag # 1 ; 0 => unblanked, 1 => blanked
Export_ScreenBlankFlag # 1
ASSERT Export_ScreenBlankFlag = ScreenBlankFlag
ASSERT ?Export_ScreenBlankFlag = ?ScreenBlankFlag
ASSERT ScreenBlankFlag = Legacy_ScreenBlankFlag
ASSERT ?ScreenBlankFlag = ?Legacy_ScreenBlankFlag
;ScreenBlankDPMSState # 1 ; 0 => just blank video
; 1 => blank to stand-by (hsync off)
; 2 => blank to suspend (vsync off)
; 3 => blank to off (H+V off)
ScreenBlankDPMSState # 1 ; 0 => just blank video
; 1 => blank to stand-by (hsync off)
; 2 => blank to suspend (vsync off)
; 3 => blank to off (H+V off)
Export_ScreenBlankDPMSState # 1
ASSERT Export_ScreenBlankDPMSState = ScreenBlankDPMSState
ASSERT ?Export_ScreenBlankDPMSState = ?ScreenBlankDPMSState
ASSERT ScreenBlankDPMSState = Legacy_ScreenBlankDPMSState
ASSERT ?ScreenBlankDPMSState = ?Legacy_ScreenBlankDPMSState
[ AssemblingArthur :LAND: :DEF: ShowWS
......@@ -840,13 +842,13 @@ Export_ScreenBlankDPMSState # 1
]
AlignSpace 64
Export_FgEcfOraEor # 4*16 ; Interleaved zgora & zgeor
ASSERT Export_FgEcfOraEor = FgEcfOraEor
ASSERT ?Export_FgEcfOraEor = ?FgEcfOraEor
FgEcfOraEor # 4*16 ; Interleaved zgora & zgeor
ASSERT FgEcfOraEor = Legacy_FgEcfOraEor
ASSERT ?FgEcfOraEor = ?Legacy_FgEcfOraEor
Export_BgEcfOraEor # 4*16 ; Interleaved zgora & zgeor
ASSERT Export_BgEcfOraEor = BgEcfOraEor
ASSERT ?Export_BgEcfOraEor = ?BgEcfOraEor
BgEcfOraEor # 4*16 ; Interleaved zgora & zgeor
ASSERT BgEcfOraEor = Legacy_BgEcfOraEor
ASSERT ?BgEcfOraEor = ?Legacy_BgEcfOraEor
BgEcfStore # 4*16 ; Interleaved zgora & zgeor to store background
......@@ -991,6 +993,14 @@ VDWSSize # 0
ASSERT VDWSSize <= 12 * 1024
; IIC bus info block
^ 0
IICBus_Type # 4 ; Bus type (HAL_IICType)
IICBus_Status # 4 ; Bus status (HAL_IICMonitorTransfer)
IICBus_Device # 4 ; Bus device (HAL_IICDevice)
IICBus_Size # 0
; *****************************************************************************
; Space in the first 32K is allocated below
; *****************************************************************************
......@@ -999,7 +1009,9 @@ VDWSSize # 0
; locations used during reset only. Not cleared by ClearPhysRAM, but
; cleared later (just before DEFHAN).
^ ZeroPage+&80 ; steer clear of FIQ code
; Note that these are all relative to ZeroPage!
^ &80 ; steer clear of FIQ code
InitIRQHandler # 4 ; pointer to IRQ handler (LDR PC'ed from IRQ HW vector)
InitIRQWs # 16 ; workspace for IRQ handler
InitUsedStart # 4 ; start of used pages (L2PT etc) not to be cleared
......@@ -1011,33 +1023,36 @@ InitWsEnd # 0
; Basic kernel space - defined locations for external modules
^ ZeroPage+&100
^ &100
IRQ1V # 4 ; &100
Export_ESC_Status # 1 ; &104
ASSERT Export_ESC_Status = ESC_Status
ASSERT ?Export_ESC_Status = ?ESC_Status
ESC_Status # 1 ; &104
ASSERT ESC_Status = Legacy_ESC_Status
ASSERT ?ESC_Status = ?Legacy_ESC_Status
Export_LatchBSoftCopy # 1 ; &105
ASSERT Export_LatchBSoftCopy = LatchBSoftCopy
ASSERT ?Export_LatchBSoftCopy = ?LatchBSoftCopy
LatchBSoftCopy # 1 ; &105
ASSERT LatchBSoftCopy = Legacy_LatchBSoftCopy
ASSERT ?LatchBSoftCopy = ?Legacy_LatchBSoftCopy
IOCControlSoftCopy # 1 ; &106
Export_CannotReset # 1 ; &107
ASSERT Export_CannotReset = CannotReset
ASSERT ?Export_CannotReset = ?CannotReset
CannotReset # 1 ; &107
ASSERT CannotReset = Legacy_CannotReset
ASSERT ?CannotReset = ?Legacy_CannotReset
Export_IRQsema # 4 ; &108
ASSERT Export_IRQsema = IRQsema
ASSERT ?Export_IRQsema = ?IRQsema
IRQsema # 4 ; &108
ASSERT IRQsema = Legacy_IRQsema
ASSERT ?IRQsema = ?Legacy_IRQsema
MetroGnome # 4 ; &10C
ASSERT MetroGnome = Legacy_MetroGnome
ASSERT ?MetroGnome = ?Legacy_MetroGnome
MemorySpeed # 4 ; &110
Export_MEMC_CR_SoftCopy # 4 ; &114
ASSERT Export_MEMC_CR_SoftCopy = MEMC_CR_SoftCopy
ASSERT ?Export_MEMC_CR_SoftCopy = ?MEMC_CR_SoftCopy
MEMC_CR_SoftCopy # 4 ; &114
ASSERT MEMC_CR_SoftCopy = Legacy_MEMC_CR_SoftCopy
ASSERT ?MEMC_CR_SoftCopy = ?Legacy_MEMC_CR_SoftCopy
ResetIndirection # 4 ; &118
......@@ -1267,27 +1282,37 @@ ProcVec_End # 0
ProcVecPreVeneersSize * 4*4 ; Space for preveneers for loading handler addresses from 0 page.
ProcVecPreVeneers # ProcVecPreVeneersSize
RTCFitted # 4 ; =0 no RTC, <2048 = address of I2C RTC, >=2048 = HALDevice_RTC ptr
[ :DEF: ShowWS
! 0, "Free space before DebuggerSpace = ":CC::STR:(&300-@)
]
ASSERT @ <= &300
# (&300-@)
Export_DebuggerSpace # 16*8 ; Debugger module needs some zero page
[ :LNOT: HiProcVecs
DebuggerSpace # 16*8 ; Debugger module needs some zero page
DebuggerSpace_Size * ?DebuggerSpace
ASSERT DebuggerSpace = Legacy_DebuggerSpace
ASSERT ?DebuggerSpace = ?Legacy_DebuggerSpace
|
DebuggerSpace * &2000 ; Debugger gets a page all to itself!
DebuggerSpace_Size * &1000
]
; NVRAM support
NVRamSize # 1 ; Size of NVRam (E2ROM & CMOS) fitted in 256byte units
RTCFitted # 1 ; flag non zero if RTC is fitted
NVRamBase # 1 ; Base of NVRam
NVRamSpeed # 1 ; Clock hold time in 0.5s units
NVRamSpeed # 1 ; Clock hold time in 0.5us units
NVRamPageSize # 1 ; Page size for writing (log2)
NVRamWriteSize # 1 ; Size of writable region (256byte units)
AlignSpace
IICType # 4
IICStatus # 4
IICBus_Count * 3 ; 3 busses is enough for all current machines
IICBus_Base # IICBus_Size*IICBus_Count
AppSpaceDANode # DANode_NodeSize ; Dummy area node for application space (not on list)
FreePoolDANode # DANode_NodeSize ; Area node for free pool
......@@ -1297,6 +1322,9 @@ MMUControlSoftCopy # 4 ; Soft copy of ARM control register
[ HAL
DeviceCount # 4 ; size of our table of devices in the system heap
DeviceTable # 4 ; pointer to table
Cache_Lx_Info # 4 ; Cache level ID register
Cache_Lx_DTable # 4*7 ; Data/unified cache layout for all 7 levels
Cache_Lx_ITable # 4*7 ; Instruction cache layout for all 7 levels
]
AplWorkSize * AppSpaceDANode + DANode_Size
......@@ -1305,6 +1333,8 @@ AplWorkSize * AppSpaceDANode + DANode_Size
EnvString # 256
]
ExtendedROMFooter # 4 ; Pointer to the extended ROM footer structure. 0 if not initialised, -1 if not found.
[ :DEF: ShowWS
! 0, "Free space after EnvString = ":CC::STR:(&500-@)
]
......@@ -1467,13 +1497,13 @@ PFIQasIRQ_Chain # 4
EnvTime # 5
Export_RedirectInHandle # 1
ASSERT Export_RedirectInHandle = RedirectInHandle
ASSERT ?Export_RedirectInHandle = ?RedirectInHandle
RedirectInHandle # 1
ASSERT RedirectInHandle = Legacy_RedirectInHandle
ASSERT ?RedirectInHandle = ?Legacy_RedirectInHandle
Export_RedirectOutHandle # 1
ASSERT Export_RedirectOutHandle = RedirectOutHandle
ASSERT ?Export_RedirectOutHandle = ?RedirectOutHandle
RedirectOutHandle # 1
ASSERT RedirectOutHandle = Legacy_RedirectOutHandle
ASSERT ?RedirectOutHandle = ?Legacy_RedirectOutHandle
MOShasFIQ # 1
FIQclaim_interlock # 1
......@@ -1611,6 +1641,8 @@ CachedErrorBlocks # 4 ; pointer to sysheap node holding the er
^ &FE8
CLibCounter # 1 ; Counter for Shared C Library tmpnam function
ASSERT CLibCounter = Legacy_CLibCounter
ASSERT ?CLibCounter = ?Legacy_CLibCounter
AlignSpace
......@@ -1620,18 +1652,26 @@ CLibCounter # 1 ; Counter for Shared C Library t
; ROM libraries. They cannot use the private word since the block pointed
; to by this will be freed.
RISCOSLibWord # 4
ASSERT RISCOSLibWord = Legacy_RISCOSLibWord
ASSERT ?RISCOSLibWord = ?Legacy_RISCOSLibWord
CLibWord # 4
ASSERT CLibWord = Legacy_CLibWord
ASSERT ?CLibWord = ?Legacy_CLibWord
FPEAnchor # 4
ASSERT FPEAnchor = Legacy_FPEAnchor
ASSERT ?FPEAnchor = ?Legacy_FPEAnchor
Export_DomainId # 4 ; SKS added for domain identification
ASSERT Export_DomainId = DomainId
ASSERT ?Export_DomainId = ?DomainId
DomainId # 4 ; SKS added for domain identification
ASSERT DomainId = Legacy_DomainId
ASSERT ?DomainId = ?Legacy_DomainId
Modula2_Private # 4 ; MICK has FFC and uses it it in USR mode
Export_VduDriverWorkSpace # VDWSSize
ASSERT Export_VduDriverWorkSpace = VduDriverWorkSpace
ASSERT ?Export_VduDriverWorkSpace = ?VduDriverWorkSpace
VduDriverWorkSpace # VDWSSize
ASSERT VduDriverWorkSpace = Legacy_VduDriverWorkSpace
ASSERT ?VduDriverWorkSpace = ?Legacy_VduDriverWorkSpace
ASSERT (VduDriverWorkSpace :AND: 63) = 0 ; For Tim (VDU5)
......@@ -1807,7 +1847,11 @@ SvcTable |#| &400
ASSERT SvcTable = &01F033FC ; Required for SVC table pokers, 1.20 compatible
]
[ No26bitCode
[ ZeroPage = 0
SWIDespatch_Size * 32*4
|
SWIDespatch_Size * 33*4
]
|
SWIDespatch_Size * 30*4 ; can save 2 instructions if 26-bit (no Thumb)
]
......@@ -1853,11 +1897,15 @@ RedirectBuff |#| OscliBuffSize
; 6 interrupts for I/O and sound DMA (this is really IOMD specific, not
; ARM600/700 specific but for the moment it is assumed that they are
; used on the same machines).
[ HAL :LAND: M_CortexA9
DefIRQ1Vspace * 12*160+128
|
[ MorrisSupport
DefIRQ1Vspace * 12*4+12*23+2*256+64 + 7*4+12*16+32+256 ;Morris adds 2 more IRQ registers
|
DefIRQ1Vspace * 12*4+12*23+2*256+64 ; for size checking in MOS
]
] ; HAL :LAND: M_CortexA9
DefaultIRQ1V |#| DefIRQ1Vspace
[ AssemblingArthur :LAND: :DEF: ShowWS
......@@ -1927,6 +1975,11 @@ GSVarWSpace # GSVarWSpace_Size
SysVarWorkSpace # 40 ; used by the sys$* variables for reading the current time into
]
ROMBuildDate # 128
[ UseNewFX0Error
NewFX0Error # 64
]
KbuffsEnd # 0
KbuffsSize * KbuffsEnd - KbuffsBaseAddress ;size of Kernel buffers area
......
; Copyright 2011 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; OS_ReadSysInfo 6 values
OSRSI6_CamEntriesPointer * 0
OSRSI6_MaxCamEntry * 1
OSRSI6_PageFlags_Unavailable * 2
OSRSI6_PhysRamTable * 3
OSRSI6_ARMA_Cleaner_flipflop * 4 ; Unused in HAL kernels
OSRSI6_TickNodeChain * 5
OSRSI6_ROMModuleChain * 6
OSRSI6_DAList * 7
OSRSI6_AppSpaceDANode * 8
OSRSI6_Module_List * 9
OSRSI6_ModuleSHT_Entries * 10
OSRSI6_ModuleSWI_HashTab * 11
OSRSI6_IOSystemType * 12
OSRSI6_L1PT * 13
OSRSI6_L2PT * 14
OSRSI6_UNDSTK * 15
OSRSI6_SVCSTK * 16
OSRSI6_SysHeapStart * 17
; These are used by ROL, but conflict with our allocations
OSRSI6_ROL_KernelMessagesBlock * 18
OSRSI6_ROL_ErrorSemaphore * 19
OSRSI6_ROL_MOSdictionary * 20
OSRSI6_ROL_Timer_0_Latch_Value * 21
OSRSI6_ROL_FastTickerV_Counts_Per_Second * 22
OSRSI6_ROL_VecPtrTab * 23
OSRSI6_ROL_NVECTORS * 24
OSRSI6_ROL_IRQSTK * 25
OSRSI6_ROL_SWIDispatchTable * 26 ; JTABLE-SWIRelocation?
OSRSI6_ROL_SWIBranchBack * 27 ; DirtyBranch?
; Our allocations which conflict with the above
OSRSI6_Danger_SWIDispatchTable * 18 ; JTABLE-SWIRelocation (Relocated base of OS SWI dispatch table)
OSRSI6_Danger_Devices * 19 ; Relocated base of IRQ device head nodes
OSRSI6_Danger_DevicesEnd * 20 ; Relocated end of IRQ device head nodes
OSRSI6_Danger_IRQSTK * 21
OSRSI6_Danger_SoundWorkSpace * 22 ; workspace (8K) and buffers (2*4K)
OSRSI6_Danger_IRQsema * 23
; Safe versions of the danger allocations
; Only supported by OS 5.17+, so if backwards compatability is required code
; should (safely!) fall back on the danger versions
OSRSI6_SWIDispatchTable * 64 ; JTABLE-SWIRelocation (Relocated base of OS SWI dispatch table)
OSRSI6_Devices * 65 ; Relocated base of IRQ device head nodes
OSRSI6_DevicesEnd * 66 ; Relocated end of IRQ device head nodes
OSRSI6_IRQSTK * 67
OSRSI6_SoundWorkSpace * 68 ; workspace (8K) and buffers (2*4K)
OSRSI6_IRQsema * 69
; New ROOL allocations
OSRSI6_DomainId * 70 ; current Wimp task handle
OSRSI6_OSByteVars * 71 ; OS_Byte vars (previously available via OS_Byte &A6/VarStart)
OSRSI6_FgEcfOraEor * 72
OSRSI6_BgEcfOraEor * 73
OSRSI6_DebuggerSpace * 74
OSRSI6_DebuggerSpace_Size * 75
OSRSI6_CannotReset * 76
OSRSI6_MetroGnome * 77 ; OS_ReadMonotonicTime
OSRSI6_CLibCounter * 78
OSRSI6_RISCOSLibWord * 79
OSRSI6_CLibWord * 80
OSRSI6_FPEAnchor * 81
OSRSI6_ESC_Status * 82
END
......@@ -90,7 +90,7 @@ ParallelFlashUpgrade SETL {FALSE}
;whether we support running on the (Risc PC) emulator
GBLL EmulatorSupport
EmulatorSupport SETL {TRUE}
EmulatorSupport SETL {FALSE} ; Disabled; QEMU doesn't like it
[ :LNOT: RO371Timings
......@@ -219,7 +219,7 @@ SAcleanflushbroken SETL {TRUE} :LAND: StrongARM
SASTMhatbroken SETL {TRUE} :LAND: StrongARM
StrongARM_POST SETL {TRUE} :LAND: StrongARM
ARM6support SETL {TRUE}
ARM6support SETL (MEMM_Type = "ARM600") ; Needs updating for VMSAv6 compatability
XScaleMiniCache SETL {FALSE}
......@@ -302,19 +302,19 @@ RMTidyDoesNowt SETL {TRUE} ; should really be "machine has
RogerEXEY SETL {FALSE} ; Marketing don't like it!
GBLL DebugROMInit
DebugROMInit SETL {FALSE}
DebugROMInit SETL {TRUE}
GBLL DebugROMPostInit ; Displays when the PostInit service call is sent to each ROM module (currently works on vanilla service call handling only)
DebugROMPostInit SETL (:LNOT: ChocolateService) :LAND: {FALSE}
GBLL DebugROMErrors
DebugROMErrors SETL {FALSE}
DebugROMErrors SETL {TRUE}
GBLL DebugTerminal ; default WRCH and RDCH through HAL
DebugTerminal SETL {FALSE}
GBLL DebugHALTX
DebugHALTX SETL {FALSE}
DebugHALTX SETL {TRUE}
GBLL DebugHeaps ; initialise claimed and freed blocks
DebugHeaps SETL {FALSE} ; (may slow things down unacceptably)
......@@ -356,6 +356,11 @@ GetMessages SETS "GET s.MsgCode"
GetMessages SETS ""
]
GBLL HiProcVecs ; Relocate processor vectors and first 16K of workspace to &FFFF0000
HiProcVecs SETL {FALSE} ; Leave off for now
; In an ideal world, we'd use something like this:
; HiProcVecs SETL M_Tungsten :LOR: :LNOT: NoARMv6
GBLL DebugForcedReset ; debug forced hard resets
DebugForcedReset SETL {FALSE}
......@@ -390,6 +395,9 @@ PollMouse SETL {FALSE} ; Poll mouse.
GBLL ProcessorVectors
ProcessorVectors SETL {TRUE} ; Processor vectors indirected through 0 page.
GBLL UseNewFX0Error
UseNewFX0Error SETL (:LNOT: Embedded_UI) :LAND: ((Version :AND: 1) = 1) ; Whether *FX 0 should show the ROM link date instead of the UtilityModule date
GBLS GetUnsqueeze
[ SqueezeMods
GetUnsqueeze SETS "GET s.Unsqueeze"
......@@ -406,7 +414,7 @@ GetFlashROM SETS ""
GBLS GetPalette
GBLS GetMemInfo
GBLS GetHAL
GetKernelMEMC SETS "GET s.ARM600"
GetKernelMEMC SETS "GET s." :CC: MEMM_Type
GetMemInfo SETS "GET s.MemInfo"
GetPalette SETS "GET s.vdu.vdupalxx"
......
......@@ -31,6 +31,16 @@ OldOpt SETA {OPT}
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Memory map values: (in address order)
; These old definitions will be gone soon.
GBLL OldKernelWorkSpace
[ :DEF: AssemblingArthur
OldKernelWorkSpace SETL :LNOT: AssemblingArthur
|
OldKernelWorkSpace SETL {TRUE}
]
[ OldKernelWorkSpace :LAND: {TRUE}
^ &00000104
ESC_Status # 1
......@@ -75,6 +85,69 @@ DomainId # 4 ; domain identification
^ &00001000
VduDriverWorkSpace # &3000
]
; New 'legacy' definitions
^ &00000104
Legacy_ESC_Status # 1
^ &00000105
Legacy_LatchBSoftCopy # 1
^ &00000107
Legacy_CannotReset # 1
^ &00000108
Legacy_IRQsema # 4
^ &0000010C
Legacy_MetroGnome # 4
^ &00000114
Legacy_MEMC_CR_SoftCopy # 4
^ &00000300
Legacy_DebuggerSpace # 8*16
^ &0000047C
Legacy_ScreenBlankFlag # 1 ; 0 => unblanked, 1 => blanked
^ &0000047D
Legacy_ScreenBlankDPMSState # 1 ; 0 => just blank video
; 1 => blank to stand-by (hsync off)
; 2 => blank to suspend (vsync off)
; 3 => blank to off (H+V off)
^ &00000480
Legacy_FgEcfOraEor # 4*16 ; Interleaved zgora & zgeor (from Vdu Driver Workspace)
^ &000004C0
Legacy_BgEcfOraEor # 4*16 ; Interleaved zgora & zgeor (from Vdu Driver Workspace)
^ &00000AE1 ; RedirectInHandle
Legacy_RedirectInHandle # 1
^ &00000AE2 ; RedirectOutHandle
Legacy_RedirectOutHandle # 1
^ &00000FE8
Legacy_CLibCounter # 1
^ &00000FEC
Legacy_RISCOSLibWord # 4
^ &00000FF0
Legacy_CLibWord # 4
^ &00000FF4
Legacy_FPEAnchor # 4
^ &00000FF8
Legacy_DomainId # 4 ; domain identification
^ &00001000
Legacy_VduDriverWorkSpace # &3000
^ &00004000
ScratchSpace # &4000
......
; Copyright 2009 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;