Commits (249)
# Copyright 1997 Acorn Computers Ltd
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# Makefile for IICTest
#
#
# Paths
#
EXP_HDR = <export$dir>
#
# Generic options:
#
MKDIR = cdir
AS = aasm
CP = copy
RM = remove
CCFLAGS = -c -depend !Depend -IC:
ASFLAGS = -depend !Depend -Stamp -quit -module -To $@ -From
CPFLAGS = ~cfr~v
#
# Program specific options:
#
COMPONENT = IICTest
SOURCE = s.IICTest
TARGET = rm.IICTest
EXPORTS = ${EXP_HDR}.${COMPONENT}
#
# Generic rules:
#
rom: ${TARGET}
@echo ${COMPONENT}: rom module built
export: ${EXPORTS}
@echo ${COMPONENT}: export complete
install_rom: ${TARGET}
${CP} ${TARGET} ${INSTDIR}.${COMPONENT} ${CPFLAGS}
@echo ${COMPONENT}: rom module installed
clean:
${RM} ${TARGET}
@echo ${COMPONENT}: cleaned
resources:
# ${MKDIR} ${RESDIR}.${COMPONENT}
# ${CP} Resources.${LOCALE}.Messages ${RESDIR}.${COMPONENT}.Messages ${CPFLAGS}
# @echo ${COMPONENT}: resource files copied
${TARGET}: ${SOURCE}
${AS} ${ASFLAGS} ${SOURCE}
${EXP_HDR}.${COMPONENT}: hdr.${COMPONENT}
# ${CP} hdr.${COMPONENT} $@ ${CPFLAGS}
# Dynamic dependencies:
; Copyright 1997 Acorn Computers Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; > s.IICTest
GET Hdr:ListOpts
GET Hdr:Macros
GET Hdr:System
GET Hdr:Machine.<Machine>
GET Hdr:ImageSize.<ImageSize>
$GetCPU
$GetIO
$GetMEMC
$GetMEMM
$GetVIDC
GBLL med_00001_debug
med_00001_debug SETL {FALSE}
AssemblingArthur SETL {TRUE}
GBLL Module
Module SETL {FALSE}
GBLL ChecksumCMOS
ChecksumCMOS SETL {TRUE}
GBLL CacheCMOSRAM ; Whether to keep a RAM copy of CMOS RAM for faster access
CacheCMOSRAM SETL MEMM_Type = "ARM600" :LAND: {TRUE} ; (Space only allocated on ARM600 versions)
GBLL ProtectStationID ; if TRUE, disallow OSBYTE &A2,0,n
ProtectStationID SETL {TRUE}
GBLL TestHarness
TestHarness SETL {TRUE}
GET Hdr:ModHand
GET Hdr:Proc
GET Hdr:CMOS
GET ^.^.hdr.PublicWS
GET ^.^.hdr.KernelWS
! 0, "NVRAMSize at ":CC::STR:(NVRamSize)
LEADR Module_LoadAddr
TAB * 9
; Module workspace allocation
^ 0, R12
i2cWorkSpace # 256
corruption_test # 4
NVSize # 1
NVSpeed # 1
RTCFlag # 1
NVBase # 1
IIC_WorkspaceSize * :INDEX: @
; **************** Module code starts here **********************
Module_BaseAddr
DCD 0
DCD IIC_Init -Module_BaseAddr
DCD IIC_Die -Module_BaseAddr
DCD IIC_Service -Module_BaseAddr
DCD IIC_Title -Module_BaseAddr
DCD IIC_HelpStr -Module_BaseAddr
DCD IIC_HC_Table-Module_BaseAddr
DCD 0
DCD 0
DCD 0
DCD 0 ; Code to manually decode swi name (not needed)
IIC_Title
DCB "IICTest",0
IIC_HelpStr
= "IICTest"
= TAB, TAB
= "0.01 (06 Mar 1997)", 0
ALIGN
; *****************************************************************************
IIC_HC_Table * Module_BaseAddr
IIC_Service * Module_BaseAddr
IIC_Init
ENTRY
LDR r2, [r12] ; Hard or soft init ?
TEQ r2, #0
BNE %FT00
; Hard init
LDR r3, =IIC_WorkspaceSize
TEQ r3, #0
BEQ %FT00
MOV r0, #ModHandReason_Claim
SWI XOS_Module
LDMVSIA sp!, {pc}
STR r2, [r12]
00 MOV r12, r2
LDR R0, =&5C5C5C5C
STR R0, corruption_test
[ CacheCMOSRAM
BL InitCMOSCache
]
BL ClaimByteV
EXIT
IIC_Die ENTRY
TEQ r12, #0
LDRNE r12, [r12]
BL ReleaseByteV
EXITS
; *****************************************************************************
; ByteV handling routines.
ClaimByteV
ENTRY "r1,r2"
MOV r0, #ByteV
ADR r1, ByteVHandler
MOV r2, r12
SWI XOS_Claim
EXIT
ReleaseByteV
ENTRY "r1,r2"
MOV r0, #ByteV
ADR r1, ByteVHandler
MOV r2, r12
SWI XOS_Release
EXIT
ByteVHandler
Push "r0,r1"
TEQ r0, #&A2
BEQ OsbyteA2
TEQ r0, #&A1
Pull "r0,r1",NE
MOVNES pc, lr
; If &A1 then drop through to...
; *****************************************************************************
; OS_Byte &A1 and &A2 handlers pulled from s.PMF.osbyte. We declare our own
; MyOsbyte macro to exit our handler by claiming the ByteV call.
MACRO
MyOsbyte $cond
Pull "r0,r1,pc",$cond,^
MEND
; Read CMOS RAM
OsbyteA1 ; R1 = address , R2 = result
CLRPSR I_bit, R0 ; this may take some time
MOV R0, R1
BL Read ; Read CMOS ram at address <R0>
MOV R2, R0 ; Result in R0, return in R2
MyOsbyte
; Write CMOS RAM
OsbyteA2
CLRPSR I_bit, R0 ; this may take some time
[ E2ROMSupport
MOVS R0, R1
|
ANDS R0, R1, #&FF ; only look at bottom byte
]
[ ProtectStationID
MyOsbyte EQ
]
; This bit is conditioned out to make life easier...
;
[ {FALSE}
; Protect machine address CMOS (if not corrupt)
ASSERT EtherCheckCMOS = EtherAddrCMOS+6
CMP r0, #EtherAddrCMOS
BLT %FT10
CMP r0, #EtherCheckCMOS
BGT %FT10
Push "r0,r1"
BL GetMachineAddressCMOS
Pull "r0,r1"
MyOsbyte EQ ; don't allow write if address is valid
10
]
MOV R1, R2
BL Write
MOV R1, R0 ; R1 is supposed to be preserved
MyOsbyte
; *****************************************************************************
; Include the i2cutils source file from the Kernel sources.
GET ^.^.s.PMF.i2cutils
END
| Copyright 1997 Acorn Computers Ltd
| Copyright 2012 Castle Technology Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
......
......@@ -196,11 +196,9 @@ in the 32-bit case:
ADR R14, saveblock ; get address of saved registers
LDR R0, [R14, #16*4] ; get user PSR
[ :LNOT: NoSPSRcorruption
MRS R1, CPSR ; get current PSR
ORR R1, R1, #&80 ; disable interrupts to prevent
MSR CPSR_c, R1 ; SPSR_SVC corruption by IRQ code (yuck)
]
MSR SPSR_cxsf, R0 ; put it into SPSR_SVC
LDMIA R14, {R0-R14}^ ; load user registers
MOV R0, R0 ; no-op after forcing user mode
......@@ -342,6 +340,21 @@ exit with:
Such code will not need altering between 26 and 32-bit versions.
A similar change will be made to the structure of the stack during ErrorV:
SVCSTK-4 Caller's R12
-8 Caller's R11
-12 Caller's R10
-16 Return R14 (26-bit - including flags)
will become:
SVCSTK-4 Caller's R12
-8 Caller's R11
-12 Caller's R10
-16 Return R14 (32-bit - no flags)
-20 Return PSR (32-bit)
MEMORY MAP
==========
......
......@@ -202,6 +202,25 @@ that are not involved in any currently active interrupts. In other words, it
is expected and desirable that interrupts remain enabled during any extended
clean operation, in order to avoid impact on interrupt latency.
-- Cache_CleanInvalidateRange
The cache or caches are to be invalidated for (at least) the given range, with
cleaning of any writeback data being properly performed.
entry: r0 = logical address of start of range
r1 = logical address of end of range (exclusive)
Note that r0 and r1 are aligned on cache line boundaries
exit: -
Note that any write buffer draining should also be performed by this
operation, so that memory is fully updated with respect to any writeaback
data.
The OS only expects the invalidation to be with respect to instructions/data
that are not involved in any currently active interrupts. In other words, it
is expected and desirable that interrupts remain enabled during any extended
clean operation, in order to avoid impact on interrupt latency.
-- Cache_CleanAll
The unified cache or data cache are to be globally cleaned (any writeback data
......@@ -249,16 +268,136 @@ the parameter more directly).
The exact value is unlikely to be critical, but a sensible value may depend
on both the ARM and external factors such as memory bus speed.
-- Cache_Examine
Return information about a given cache level
entry: r1 = cache level (0-based)
exit: r0 = Flags
bits 0-2: cache type:
000 -> none
001 -> instruction
010 -> data
011 -> split
100 -> unified
1xx -> reserved
Other bits: reserved
r1 = D line length
r2 = D size
r3 = I line length
r4 = I size
r0-r4 = zero if cache level not present
For unified caches, r1-r2 will match r3-r4. This call mainly exists for the
benefit of OS_PlatformFeatures 33.
Memory barrier ARMops
=====================
-- DSB_ReadWrite (previously, WriteBuffer_Drain)
This call is roughly equivalent to the ARMv7 "DSB SY" instruction:
* Writebuffers are drained
* Full read/write barrier - no data load/store will cross the instruction
* Instructions following the barrier will only begin execution once the
barrier is passed - but any prefetched instructions are not flushed
entry: -
exit: -
-- DSB_Write
This call is roughly equivalent to the ARMv7 "DSB ST" instruction:
* Writebuffers are drained
* Write barrier - reads may cross the instruction
* Instructions following the barrier will only begin execution once the
barrier is passed - but any prefetched instructions are not flushed
entry: -
exit: -
-- DSB_Read
-- WriteBuffer_Drain
There is no direct equivalent to this in ARMv7 (barriers are either W or RW).
However it's useful to define a read barrier, as (e.g.) on Cortex-A9 a RW
barrier would require draining the write buffer of the external PL310 cache,
while a R barrier can simply be an ordinary DSB instruction.
Any writebuffers are to be drained so that any pending writes are guaranteed
completed to memory.
* Read barrier - writes may cross the instruction
* Instructions following the barrier will only begin execution once the
barrier is passed - but any prefetched instructions are not flushed
entry: -
exit: -
-- DMB_ReadWrite
This call is roughly equivalent to the ARMv7 "DMB SY" instruction:
* Ensures in-order operation of data load/store instructions
* Does not stall instruction execution
* Does not guarantee that any preceeding memory operations complete in a
timely manner (or at all)
entry: -
exit: -
Although this call doesn't guarantee that any memory operation completes, it's
usually all that's required when interacting with hardware devices which use
memory-mapped IO. E.g. fill a buffer with data, issue a DMB, then write to a
hardware register to start some external DMA. The writes to the buffer will
have been guaranteed to complete by the time the write to the hardware register
completes.
-- DMB_Write
This call is roughly equivalent to the ARMv7 "DMB ST" instruction:
* Ensures in-order operation of data store instructions
* Does not stall instruction execution
* Does not guarantee that any preceeding memory operations complete in a
timely manner (or at all)
entry: -
exit: -
Although this call doesn't guarantee that any memory operation completes, it's
usually all that's required when interacting with hardware devices which use
memory-mapped IO. E.g. fill a buffer with data, issue a DMB, then write to a
hardware register to start some external DMA. The writes to the buffer will
have been guaranteed to complete by the time the write to the hardware register
completes.
-- DMB_Read
There is no direct equivalent to this in ARMv7 (barriers are either W or RW).
However it's useful to define a read barrier, as (e.g.) on Cortex-A9 a RW
barrier would require draining the write buffer of the external PL310 cache,
while a R barrier can simply be an ordinary DMB instruction.
* Ensures in-order operation of data load instructions
* Does not stall instruction execution
* Does not guarantee that any preceeding memory operations complete in a
timely manner (or at all)
entry: -
exit: -
Although this call doesn't guarantee that any memory operation completes, it's
usually all that's required when interacting with hardware devices which use
memory-mapped IO. E.g. after reading a hardware register to detect that a DMA
write to RAM has completed, issue a read barrier to ensure that any reads from
the data buffer see the final data.
TLB ARMops
----------
......@@ -337,6 +476,24 @@ typically expected to use a threshold (related to Cache_RangeThreshold) to
decide when to perform IMB_Full instead, being faster for large ranges.
-- IMB_List
A variant of IMB_Range that accepts a list of address ranges.
entry: r0 = pointer to word-aligned list of (start, end) address pairs
r1 = pointer to end of list (past last valid entry)
r2 = total amount of memory to be synchronised
If you have several areas to synchronise then using this call may result in
significant performance gains, both from reducing the function call overhead
and from optimisations in the algorithm itself (e.g. only flushing instruction
cache once for StrongARM).
As with IMB_Range, start & end addresses are inclusive-exclusive and must be
cache line aligned. The list must contain at least one entry, and must not
contain zero-length entries.
MMU mapping ARMops
------------------
......
......@@ -29,49 +29,6 @@ HAL_FIQDisable
HAL_FIQClear
HAL_FIQDisableAll
Interrupt specifications are generally described by a 3-word structure.
The 3 words correspond directly to the contents of registers R0,R3 and R4
on entry to OS_ClaimDeviceVector.
typedef struct irq_descriptor
{
int device;
union {
struct {
unsigned char *addr;
int maskandpolarity;
} bit;
struct {
int (*forme)(void *handle);
void *handle;
} func;
} sub;
} irq_descriptor;
OS_ClaimDeviceVector changes:
R3 and R4 must always be supplied. Set R3=R4=0 to claim "all" of an interrupt.
Bit 31 of the device number indicates that a routine is being supplied instead
of an address and a mask.
When supplying a bit mask, your handler is called if
([addr] AND maskandpolarity) EOR (maskandpolarity >> 8)
is nonzero. This is a RISC OS 3.8+ backwards-compatible extension to the original
check:
[addr] AND maskandpolarity
When supplying a routine, your handler is called if
forme(handle)
returns nonzero.
if
Timers
======
......
......@@ -28,14 +28,13 @@ A simple call to a activate a device from assembler might look like:
If an assembler device driver module is using a lot of device calls, it
might be preferable to move the workspace pointer from the traditional R12
to R11.
The device descriptor
=====================
The device descriptor starts with a fixed format header, as described
below. Following this header are more function pointers providing device-specific
calls.
below. Following this header are more function pointers providing device-specific calls.
struct device
{
......@@ -95,16 +94,27 @@ The location describes the location of the device in terms of the bus architectu
of the computer. Again, it is grouped by bytes.
Bits 31-28: Bus type
0 => processor (0 = core, 1 = coprocessor)
1 => main system bus (0 = AHB, 1 = ASB, 2 = PXBus)
2 => peripheral bus (0 = APB)
3 => expansion bus (0 = Acorn Expansion Card, 1 = ISA, 2 = PCI)
4 => serial bus (0 = AC-Link)
Bits 27-24: Bus sub-type (see above)
0 => processor
eg. timer TCR0 on XScale coprocessor CP6
1 => main system bus
eg. DMA controller on OMAP3
2 => peripheral bus
eg. on chip UART on iMx6
3 => expansion bus
eg. UART inside the southbridge over PCI
4 => serial bus
eg. audio codec fed by a southbridge over PCI
Bits 27-24: Bus sub-type (see Hdr:HALDevice for definitions)
Bits 23-16: Bus number
Bits 15-8: Card number (PCI, expansion card etc) / chip select number
Bits 7-0: Unit number
The bus type fields are broadly ordered by access cost. Therefore peripherals directly attached to the ARM core are first, then on-chip buses typically at the same clock speed as the caches, then low bandwidth on chip peripheral buses, off chip expansion via circuit board tracks, and lastly the slowest/narrowest serial bus class.
Each step down the heirarchy typically involves a bridge component to translate the bus transactions. The processor bus, for example, has no translation as it is accessed using native ARM instructions.
Note that the field is describing the location of the device being described, which may itself emit another bus type. For example an APB connected IIC controller is on the peripheral bus (not the serial bus).
Version
-------
The version describes the version of the device API implemented. It consists of a
......@@ -175,6 +185,40 @@ Returns 0 if the device is not interrupting, or 1 if the device is interrupting.
When DeviceNumber is -1, this must be a null pointer.
Workspace
=========
As noted in the overview, a device may be implemented either in the HAL
or supplemented after the kernel starts through RISC OS modules.
The HAL uses the ATPCS assigned static base (sb/r9) to access position
independent data, while traditional modules use the workspace pointer (wp/r12).
Assembler modules use r12 directly, for C modules CMHG arranges this to keep
track of position independent data as r12 may be corrupted across function
calls as the ATPCS uses it as scratch register 'ip'.
When designing device specific extensions to the basic device descriptor, do
not create a dependence on the data pointer that would preclude implementing
the device in the HAL or a RISC OS module.
Each device specific extension takes a
struct device *
as its first argument. This is the structure which is defined as part of the
client API. You are free to keep other unrelated private data or state in
addition to this structure, typically this would be implemented as:
a) For a HAL based device, the device structure is typically allocated from
the global HAL workspace, so it is possible to compute the base of that
workspace (and hence recover sb) by subtraction.
Alternatively, keep a larger version of the structure internally, and
keep the original sb in a private area off the end or the one seen by
the client.
In both cases the original sb was known at the point the HAL device was
registered.
b) For a RISC OS module based device, keep private data in global variables
associated with your module. CMHG will dereference these automatically
by deriving offsets from the R12 value passed to the CMHG veneers.
Creation and removal of devices
===============================
......
......@@ -252,6 +252,13 @@ Build_Syntax
= "Syntax: *",TokenEscapeChar,Token0
= " <filename>", 0
Cache_Help
= "*",TokenEscapeChar,Token0
= " turns the cache on or off, or gives the cache state.",13
Cache_Syntax
= "Syntax: *",TokenEscapeChar,Token0
= " [On|Off]", 0
Close_Help
= "*",TokenEscapeChar,Token0
= " closes all files on the current filing system.",13
......@@ -372,11 +379,7 @@ Save_Help
= " Length and addresses are in hexadecimal.",13
Save_Syntax
= "Syntax: *",TokenEscapeChar,Token0
= " <filename> <start addr>"
= " <end addr> [<exec addr> [<load addr>]]",13
= 31, 31, 31, 31, " or *",TokenEscapeChar,Token0
= " <filename> <start addr>"
= " + <length> [<exec addr> [<load addr>]]", 0
= " <filename> <start addr> <+length|end addr> [<exec addr> [<load addr>]]",0
Shadow_Help
= "*",TokenEscapeChar,Token0
......@@ -407,12 +410,11 @@ SpoolOn_Syntax
TV_Help
= "*",TokenEscapeChar,Token0
= " [<vertical position> [[,] <interlace>]]"
= " sets the position of the display on the screen.", 0
= " controls interlacing and sets the position of the display on the screen.", 0
TV_Syntax
= "*",TokenEscapeChar,Token0
= " needs 0 to 2 parameters.", 0
= " [<vertical position> [[,] <interlace>]]", 0
Type_Help
= "*",TokenEscapeChar,Token0
......@@ -499,6 +501,8 @@ Append_Help DCB "HUTMAPP", 0
Append_Syntax DCB "SUTMAPP", 0
Build_Help DCB "HUTMBUI", 0
Build_Syntax DCB "SUTMBUI", 0
Cache_Help DCB "HUTMCAC", 0
Cache_Syntax DCB "SUTMCAC", 0
Close_Help DCB "HUTMCLO", 0
Close_Syntax DCB "SUTMCLO", 0
Create_Help DCB "HUTMCRE", 0
......
......@@ -14,143 +14,122 @@
#
# Makefile for Kernel
#
# ***********************************
# *** C h a n g e L i s t ***
# ***********************************
# Date Name Description
# ---- ---- -----------
# 25-May-94 AMcC Created.
#
#
# Paths
#
EXP_HDR = <export$dir>
C_EXP_HDR = <cexport$dir>.Global.h
COMPONENT = Kernel
ifeq (${MAKECMDGOALS},install)
EXP_HDR = ${INSTDIR}.Hdr.Interface
C_EXP_HDR = ${INSTDIR}.C.Global.h
else
C_EXP_HDR = <cexport$dir>.Global.h
endif
TOKHELPSRC = ${TOKENSOURCE}
HELPSRC = HelpStrs
ROM_SOURCE = GetAll.s
KERNEL_MODULE = bin${SEP}${COMPONENT}
ASFLAGS += -PD "FreezeDevRel SETL {${FREEZE_DEV_REL}}"
CUSTOMROM = custom
CUSTOMEXP = custom
EXPORTS = ${EXP_HDR}.EnvNumbers \
${EXP_HDR}.AHCIDevice \
${EXP_HDR}.EtherDevice \
${EXP_HDR}.HALDevice \
${EXP_HDR}.HALEntries \
${EXP_HDR}.ModHand \
${EXP_HDR}.OSEntries \
${EXP_HDR}.OSMisc \
${EXP_HDR}.OSRSI6 \
${EXP_HDR}.PL310 \
${EXP_HDR}.PublicWS \
${EXP_HDR}.RISCOS \
${EXP_HDR}.Variables \
${EXP_HDR}.VduExt \
${EXP_HDR}.VIDCList \
${EXP_HDR}.VideoDevice \
${C_EXP_HDR}.HALDevice \
${C_EXP_HDR}.HALEntries \
${C_EXP_HDR}.ModHand \
${C_EXP_HDR}.OSEntries \
${C_EXP_HDR}.OSMisc \
${C_EXP_HDR}.OSRSI6 \
${C_EXP_HDR}.RISCOS \
${C_EXP_HDR}.Variables \
${C_EXP_HDR}.VduExt \
${C_EXP_HDR}.VIDCList
CUSTOMSA=custom
include StdTools
include AAsmModule
# Override this to "TRUE" in the components file if
# you want an odd-numbered (development) build to be
# a 'freezable' build - e.g. with no ROM debug output
FREEZE_DEV_REL ?= FALSE
#
# Custom ROM:
#
rom: ${KERNEL_MODULE}
@${ECHO} ${COMPONENT}: rom module built
install_rom: ${KERNEL_MODULE}
${CP} ${KERNEL_MODULE} ${INSTDIR}${SEP}${TARGET} ${CPFLAGS}
${CP} ${KERNEL_MODULE}_gpa ${INSTDIR}${SEP}${TARGET}_gpa ${CPFLAGS}
@${ECHO} ${COMPONENT}: rom module installed
inst_dirs:
${MKDIR} ${EXP_HDR}
${MKDIR} ${C_EXP_HDR}
#
# Generic options:
#
MKDIR = mkdir -p
AS = aasm
ARMASM = objasm
LD = link
CP = copy
RM = remove
XWIPE = x wipe
PERL = do <Perl$Dir>.perl
CCFLAGS = -c -depend !Depend -IC:
ASFLAGS = -depend !Depend ${THROWBACK} -Stamp -quit -To $@ -From
ARMASMFLAGS = -depend !Depend -g ${THROWBACK}
CPFLAGS = ~cfr~v
WFLAGS = ~cfr~v
TOKENISE = tokenise
TOKENS = Hdr:Tokens
install: ${EXPORTS} inst_dirs
@${ECHO} ${COMPONENT}: header files installed
#
# Program specific options:
#
COMPONENT = Kernel
SOURCE = s.GetAll
TARGET = rm.Kernel
AIFDBG = aif.Kernel
GPADBG = GPA
OBJECTS = o.GetAll #o.ARMops o.End
EXPORTS = ${EXP_HDR}.EnvNumbers \
${EXP_HDR}.ModHand \
${EXP_HDR}.PublicWS \
${EXP_HDR}.RISCOS \
${EXP_HDR}.Variables \
${EXP_HDR}.VduExt \
${EXP_HDR}.HALEntries \
${EXP_HDR}.HALDevice \
${EXP_HDR}.RTCDevice \
${EXP_HDR}.VideoDevice \
${EXP_HDR}.GPIODevice \
${EXP_HDR}.OSEntries \
${EXP_HDR}.OSRSI6 \
${C_EXP_HDR}.RISCOS \
${C_EXP_HDR}.HALEntries \
${C_EXP_HDR}.HALDevice \
${C_EXP_HDR}.OSEntries \
${C_EXP_HDR}.Variables \
${C_EXP_HDR}.OSRSI6
${KERNEL_MODULE}: ${ROM_OBJECT} ${DIRS}
${MKDIR} bin
${LD} -bin -o $@ ${ROM_OBJECT}
${LD} -aif -bin -d -o ${KERNEL_MODULE}_aif ${ROM_OBJECT}
${TOGPA} -s ${KERNEL_MODULE}_aif ${KERNEL_MODULE}_gpa
#
# Generic rules:
# Custom exports:
#
.SUFFIXES: .o .s
.s.o:; ${ARMASM} ${ARMASMFLAGS} -o $@ $< #-list list.$*
rom: ${TARGET}
@echo ${COMPONENT}: rom module built
debug: ${GPADBG}
@echo ${COMPONENT}: debug image built
install_rom: ${TARGET}
${CP} ${TARGET} ${INSTDIR}.${COMPONENT} ${CPFLAGS}
@echo ${COMPONENT}: rom module installed
clean:
${RM} s.TMOSHelp
${RM} s.Time+Date
${XWIPE} o.* ${WFLAGS}
${RM} ${TARGET}
${XWIPE} aif ${WFLAGS}
${RM} ${GPADBG}
${XWIPE} list.* ${WFLAGS}
@echo ${COMPONENT}: cleaned
export: ${EXPORTS}
@echo ${COMPONENT}: export complete
@${ECHO} ${COMPONENT}: export complete
resources: resources-${CMDHELP}
@echo ${COMPONENT}: resource files copied
${EXP_HDR}.EnvNumbers: hdr.EnvNumbers
${CP} hdr.EnvNumbers $@ ${CPFLAGS}
resources_common:
${MKDIR} ${RESDIR}.${COMPONENT}
Set Kernel$Messages LocalRes:Messages
IfThere LocalRes:<UserIF>.Messages Then Set Kernel$Messages LocalRes:<UserIF>.Messages
TokenCheck LocalRes:<UserIF>.Messages
${CP} <Kernel$Messages> ${RESDIR}.${COMPONENT}.Messages ${CPFLAGS}
UnSet Kernel$Messages
${EXP_HDR}.SPIDevice: hdr.SPIDevice
${CP} hdr.SPIDevice $@ ${CPFLAGS}
resources-None: resources_common
@
${EXP_HDR}.AHCIDevice: hdr.AHCIDevice
${CP} hdr.AHCIDevice $@ ${CPFLAGS}
resources-: resources_common
TokenCheck LocalRes:Messages
print LocalRes:CmdHelp { >> ${RESDIR}.${COMPONENT}.Messages }
${EXP_HDR}.EtherDevice: hdr.EtherDevice
${CP} hdr.EtherDevice $@ ${CPFLAGS}
${TARGET}: ${OBJECTS}
${LD} -bin -o ${TARGET} ${OBJECTS}
${EXP_HDR}.HALDevice: hdr.HALDevice
${CP} hdr.HALDevice $@ ${CPFLAGS}
${AIFDBG}: ${OBJECTS}
${MKDIR} aif
${LD} -aif -bin -d -o ${AIFDBG} ${OBJECTS}
${EXP_HDR}.HALEntries: hdr.HALEntries
${CP} hdr.HALEntries $@ ${CPFLAGS}
${GPADBG}: ${AIFDBG}
ToGPA -s ${AIFDBG} ${GPADBG}
${EXP_HDR}.ModHand: hdr.ModHand
${CP} hdr.ModHand $@ ${CPFLAGS}
s.TMOSHelp: ${TOKENS} HelpStrs
${TOKENISE} ${TOKENS} HelpStrs $@
${EXP_HDR}.OSEntries: hdr.OSEntries
${CP} hdr.OSEntries $@ ${CPFLAGS}
#s.Time+Date:
# @echo |IGBLS Builddate|JBuilddate SETS "<Sys$Date> <Sys$Year>.<Sys$Time>" |J|IEND { > s.Time+Date }
# settype s.Time+Date FFF
o.GetAll: s.TMOSHelp
${EXP_HDR}.OSMisc: hdr.OSMisc
${CP} hdr.OSMisc $@ ${CPFLAGS}
#
# Exported interface headers
#
${EXP_HDR}.EnvNumbers: hdr.EnvNumbers
${CP} hdr.EnvNumbers $@ ${CPFLAGS}
${EXP_HDR}.OSRSI6: hdr.OSRSI6
${CP} hdr.OSRSI6 $@ ${CPFLAGS}
${EXP_HDR}.ModHand: hdr.ModHand
${CP} hdr.ModHand $@ ${CPFLAGS}
${EXP_HDR}.PL310: hdr.PL310
${CP} hdr.PL310 $@ ${CPFLAGS}
${EXP_HDR}.PublicWS: hdr.PublicWS
${CP} hdr.PublicWS $@ ${CPFLAGS}
......@@ -158,68 +137,69 @@ ${EXP_HDR}.PublicWS: hdr.PublicWS
${EXP_HDR}.RISCOS: hdr.RISCOS
${CP} hdr.RISCOS $@ ${CPFLAGS}
${EXP_HDR}.Variables: hdr.Variables
${CP} hdr.Variables $@ ${CPFLAGS}
${EXP_HDR}.VduExt: hdr.VduExt
${CP} hdr.VduExt $@ ${CPFLAGS}
${EXP_HDR}.Variables: hdr.Variables
${CP} hdr.Variables $@ ${CPFLAGS}
${EXP_HDR}.HALEntries: hdr.HALEntries
${CP} hdr.HALEntries $@ ${CPFLAGS}
${EXP_HDR}.HALDevice: hdr.HALDevice
${CP} hdr.HALDevice $@ ${CPFLAGS}
${EXP_HDR}.RTCDevice: hdr.RTCDevice
${CP} hdr.RTCDevice $@ ${CPFLAGS}
${EXP_HDR}.OSEntries: hdr.OSEntries
${CP} hdr.OSEntries $@ ${CPFLAGS}
${EXP_HDR}.VIDCList: hdr.VIDCList
${CP} hdr.VIDCList $@ ${CPFLAGS}
${EXP_HDR}.VideoDevice: hdr.VideoDevice
${CP} hdr.VideoDevice $@ ${CPFLAGS}
${EXP_HDR}.GPIODevice: hdr.GPIODevice
${CP} hdr.GPIODevice $@ ${CPFLAGS}
${EXP_HDR}.OSRSI6: hdr.OSRSI6
${CP} hdr.OSRSI6 $@ ${CPFLAGS}
${C_EXP_HDR}.RISCOS: hdr.RISCOS
${MKDIR} ${C_EXP_HDR}
${PERL} Build:Hdr2H hdr.RISCOS $@
${C_EXP_HDR}.HALDevice: Global.h.HALDevice h.HALDevice
${FAPPEND} $@ h.HALDevice Global.h.HALDevice
${C_EXP_HDR}.HALEntries: hdr.HALEntries
${MKDIR} ${C_EXP_HDR}
${PERL} Build:Hdr2H hdr.HALEntries $@
${HDR2H} hdr.HALEntries $@
${C_EXP_HDR}.ModHand: hdr.ModHand
${MKDIR} ${C_EXP_HDR}
${HDR2H} hdr.ModHand $@
${C_EXP_HDR}.OSEntries: Global.h.OSEntries h.OSEntries
${FAPPEND} $@ h.OSEntries Global.h.OSEntries
${C_EXP_HDR}.HALDevice: o.Global.h.HALDevice h.HALDevice
${CP} h.HALDevice $@ ${CPFLAGS}
print o.Global.h.HALDevice { >> $@ }
${C_EXP_HDR}.OSMisc: hdr.OSMisc
${MKDIR} ${C_EXP_HDR}
${HDR2H} hdr.OSMisc $@
${C_EXP_HDR}.OSEntries: hdr.OSEntries
${C_EXP_HDR}.OSRSI6: hdr.OSRSI6
${MKDIR} ${C_EXP_HDR}
${PERL} Build:Hdr2H hdr.OSEntries $@
${HDR2H} hdr.OSRSI6 $@
${C_EXP_HDR}.RISCOS: hdr.RISCOS
${MKDIR} ${C_EXP_HDR}
${HDR2H} hdr.RISCOS $@
${C_EXP_HDR}.Variables: hdr.Variables
${MKDIR} ${C_EXP_HDR}
${PERL} Build:Hdr2H hdr.Variables $@
${HDR2H} hdr.Variables $@
${C_EXP_HDR}.OSRSI6: hdr.OSRSI6
${C_EXP_HDR}.VduExt: hdr.VduExt
${MKDIR} ${C_EXP_HDR}
${PERL} Build:Hdr2H hdr.OSRSI6 $@
o.Global.h.HALDevice: hdr.HALDevice
${MKDIR} o.Global.h
dir o
${PERL} Build:Hdr2H ^.hdr.HALDevice Global.h.HALDevice
back
BBETYPE = kernel
bbe-kernel: bbe-generic-resources-get-alias
BBE_Export_File_In_Dir Resources.${LOCALE} CmdHelp
BBE_Export_File_In_Dir Resources.${LOCALE} Messages
BBE_Export_Dir Resources.${LOCALE}.${USERIF}
BBE_Export_File VersionNum
${HDR2H} hdr.VduExt $@
${C_EXP_HDR}.VIDCList: Global.h.VIDCList h.VIDCList
${FAPPEND} $@ h.VIDCList Global.h.VIDCList
Global.h.HALDevice: hdr.HALDevice
${MKDIR} Global.h
${HDR2H} hdr.HALDevice $@
Global.h.OSEntries: hdr.OSEntries
${MKDIR} Global.h
${HDR2H} hdr.OSEntries $@
Global.h.VIDCList: hdr.VIDCList
${MKDIR} Global.h
${HDR2H} hdr.VIDCList $@
clean::
${XWIPE} Global ${WFLAGS}
${XWIPE} bin ${WFLAGS}
# Dynamic dependencies:
| Copyright 1997 Acorn Computers Ltd
| Copyright 2014 Castle Technology Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
......@@ -13,4 +13,4 @@
| limitations under the License.
|
Dir <Obey$Dir>
amu_machine rom
amu_machine install INSTDIR=Install:DDE.AcornC/C++.Export.<APCS>
......@@ -13,6 +13,4 @@
| limitations under the License.
|
Dir <Obey$Dir>
time
do amu_machine rom debug THROWBACK=-throwback
time
amu_machine rom THROWBACK=-throwback
| Copyright 1997 Acorn Computers Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
| You may obtain a copy of the License at
|
| http://www.apache.org/licenses/LICENSE-2.0
|
| Unless required by applicable law or agreed to in writing, software
| distributed under the License is distributed on an "AS IS" BASIS,
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
| See the License for the specific language governing permissions and
| limitations under the License.
|
Dir <Obey$Dir>
time
amu_machine rom
time
amu_machine install_rom INSTDIR=<install$dir>.<Build>.RISC_OS
time
| Copyright 1996 Acorn Computers Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
| You may obtain a copy of the License at
|
| http://www.apache.org/licenses/LICENSE-2.0
|
| Unless required by applicable law or agreed to in writing, software
| distributed under the License is distributed on an "AS IS" BASIS,
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
| See the License for the specific language governing permissions and
| limitations under the License.
|
| > NewModes.Make
WimpSlot -min 1024k -max 1024k
AASM <Obey$Dir>.PSSrc <Obey$Dir>.PSModule -module -quit
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; general purpose mode macros
ClockShift * 9
SyncShift * 11
; pixel rate specifiers
CRPix_24000 * 3 :OR: (0 :SHL: ClockShift)
CRPix_16000 * 2 :OR: (0 :SHL: ClockShift)
CRPix_12000 * 1 :OR: (0 :SHL: ClockShift)
CRPix_8000 * 0 :OR: (0 :SHL: ClockShift)
CRPix_25175 * 3 :OR: (1 :SHL: ClockShift)
CRPix_36000 * 3 :OR: (2 :SHL: ClockShift)
MACRO
VIDC_List $lbpp,$hsync,$hbpch,$hlbdr,$hdisp,$hrbdr,$hfpch, $vsync,$vbpch,$vlbdr,$vdisp,$vrbdr,$vfpch,$pixrate,$sp
LCLA sub
LCLA syncpol
[ $lbpp = 3
sub SETA 5
]
[ $lbpp = 2
sub SETA 7
]
[ $lbpp = 1
sub SETA 11
]
[ $lbpp = 0
sub SETA 19
]
[ "$sp"=""
syncpol SETA 0 :SHL: SyncShift ; normal sync polarity
|
ASSERT $sp<=3
syncpol SETA $sp :SHL: SyncShift
]
ASSERT ($hsync :AND: 1)=0
ASSERT ($hbpch :AND: 1)=1
ASSERT ($hlbdr :AND: 1)=0
ASSERT ($hdisp :AND: 1)=0
ASSERT ($hrbdr :AND: 1)=0
ASSERT ($hfpch :AND: 1)=1
[ (($hsync+$hbpch+$hlbdr+$hdisp+$hrbdr+$hfpch) :AND: 3)<>0
! 0, "Warning: mode unsuitable for interlaced use"
]
; Horizontal
& (&80:SHL:24) :OR: ((($hsync+$hbpch+$hlbdr+$hdisp+$hrbdr+$hfpch -2 )/2) :SHL: 14) ; HCR
& (&84:SHL:24) :OR: ((($hsync -2 )/2) :SHL: 14) ; HSWR
& (&88:SHL:24) :OR: ((($hsync+$hbpch -1 )/2) :SHL: 14) ; HBSR
& (&8C:SHL:24) :OR: ((($hsync+$hbpch+$hlbdr -sub)/2) :SHL: 14) ; HDSR
& (&90:SHL:24) :OR: ((($hsync+$hbpch+$hlbdr+$hdisp -sub)/2) :SHL: 14) ; HDER
& (&94:SHL:24) :OR: ((($hsync+$hbpch+$hlbdr+$hdisp+$hrbdr -1 )/2) :SHL: 14) ; HBER
& (&9C:SHL:24) :OR: (((($hsync+$hbpch+$hlbdr+$hdisp+$hrbdr+$hfpch-2)/2+1)/2):SHL:14); HIR
; Vertical
& (&A0:SHL:24) :OR: (($vsync+$vbpch+$vlbdr+$vdisp+$vrbdr+$vfpch -1) :SHL: 14) ; VCR
& (&A4:SHL:24) :OR: (($vsync -1) :SHL: 14) ; VSWR
& (&A8:SHL:24) :OR: (($vsync+$vbpch -1) :SHL: 14) ; VBSR
& (&AC:SHL:24) :OR: (($vsync+$vbpch+$vlbdr -1) :SHL: 14) ; VDSR
& (&B0:SHL:24) :OR: (($vsync+$vbpch+$vlbdr+$vdisp -1) :SHL: 14) ; VDER
& (&B4:SHL:24) :OR: (($vsync+$vbpch+$vlbdr+$vdisp+$vrbdr -1) :SHL: 14) ; VBER
; Control Register
& (&E0:SHL:24) :OR: (CRPix_$pixrate) :OR: ($lbpp :SHL: 2) :OR: syncpol
& -1
MEND
MACRO
VIDC_WS $bpp,$hpix,$vpix,$multx,$multy, $dht
& VduExt_XWindLimit, $hpix-1
& VduExt_ScrRCol, ($hpix/8)-1
& VduExt_LineLength, $hpix*$bpp/8
[ "$dht" <> ""
& VduExt_ModeFlags, Flag_DoubleVertical
& VduExt_ScrBRow, ($vpix/16)-1
|
& VduExt_ScrBRow, ($vpix/8)-1
]
& VduExt_YWindLimit, $vpix-1
& VduExt_ScreenSize, $hpix*$vpix*$bpp/8
& VduExt_XEigFactor, $multx
& VduExt_YEigFactor, $multy
MEND
VLN_0 VIDC_List 0, 72,145, 48, 640, 48, 71, 3,18,18,256,17, 0,16000,0 ; MODE 0
VLN_1 VIDC_List 1, 36, 73, 24, 320, 24, 35, 3,18,18,256,17, 0, 8000,0 ; MODE 1
VLN_2 VIDC_List 2, 36, 73, 24, 320, 24, 35, 3,18,18,256,17, 0, 8000,0 ; MODE 2
VLN_3 VIDC_List 1, 72,145, 48, 640, 48, 71, 3,18,22,250,19, 0,16000,0 ; MODE 3
VLN_4 VIDC_List 0, 72,145, 48, 640, 48, 71, 3,18,18,256,17, 0,16000,0 ; MODE 4
VLN_5 VIDC_List 1, 36, 73, 24, 320, 24, 35, 3,18,18,256,17, 0, 8000,0 ; MODE 5
VLN_6 VIDC_List 1, 36, 73, 24, 320, 24, 35, 3,18,22,250,19, 0, 8000,0 ; MODE 6
VLN_7 VIDC_List 2, 36, 73, 24, 320, 24, 35, 3,18,22,250,19, 0, 8000,0 ; MODE 7
VLN_8 VIDC_List 1, 72,145, 48, 640, 48, 71, 3,18,18,256,17, 0,16000,0 ; MODE 8
VLN_9 VIDC_List 2, 36, 73, 24, 320, 24, 35, 3,18,18,256,17, 0, 8000,0 ; MODE 9
VLN_10 VIDC_List 3, 36, 73, 24, 320, 24, 35, 3,18,18,256,17, 0, 8000,0 ; MODE 10
VLN_11 VIDC_List 1, 72,145, 48, 640, 48, 71, 3,18,22,250,19, 0,16000,0 ; MODE 11
VLN_12 VIDC_List 2, 72,145, 48, 640, 48, 71, 3,18,18,256,17, 0,16000,0 ; MODE 12
VLN_13 VIDC_List 3, 36, 73, 24, 320, 24, 35, 3,18,18,256,17, 0, 8000,0 ; MODE 13
VLN_14 VIDC_List 2, 72,145, 48, 640, 48, 71, 3,18,22,250,19, 0,16000,0 ; MODE 14
VLN_15 VIDC_List 3, 72,145, 48, 640, 48, 71, 3,18,18,256,17, 0,16000,0 ; MODE 15
VLN_16 VIDC_List 2, 72,215, 46,1056, 46,101, 3,18,18,256,17, 0,24000,0 ; MODE 16
VLN_17 VIDC_List 2, 72,215, 46,1056, 46,101, 3,18,22,250,19, 0,24000,0 ; MODE 17
;VLN_18 VIDC_List 0, 56,183, 2, 640, 2, 13, 3,17, 1,512, 1, 0,24000,0 ; MODE 18
;VLN_19 VIDC_List 1, 56,183, 2, 640, 2, 13, 3,17, 1,512, 1, 0,24000,0 ; MODE 19
;VLN_20 VIDC_List 2, 56,183, 2, 640, 2, 13, 3,17, 1,512, 1, 0,24000,0 ; MODE 20
;VLN_21 VIDC_List 3, 56,183, 2, 640, 2, 13, 3,17, 1,512, 1, 0,24000,0 ; MODE 21
VLN_24 VIDC_List 3, 72,215, 46,1056, 46,101, 3,18,18,256,17, 0,24000,0 ; MODE 24
VLN_33 VIDC_List 3, 74,127, 0, 768, 0, 55, 3,18, 0,288, 0, 3,16000,0 ; MODE 33
VLN_34 VIDC_List 3, 74, 87, 0, 832, 0, 31, 3,18, 0,288, 0, 3,16000,0 ; MODE 34
VLM_0 VIDC_List 0, 72, 63, 88, 640, 88, 73, 3,16,17,256,17, 3,16000,0 ; MODE 0
VLM_1 VIDC_List 1, 36, 33, 44, 320, 44, 35, 3,16,17,256,17, 3, 8000,0 ; MODE 1
VLM_2 VIDC_List 2, 36, 33, 44, 320, 44, 35, 3,16,17,256,17, 3, 8000,0 ; MODE 2
VLM_3 VIDC_List 1, 72, 63, 88, 640, 88, 73, 3,16,20,250,20, 3,16000,0 ; MODE 3
VLM_4 VIDC_List 0, 72, 63, 88, 640, 88, 73, 3,16,17,256,17, 3,16000,0 ; MODE 4
VLM_5 VIDC_List 1, 36, 51, 24, 320, 24, 57, 3,16,17,256,17, 3, 8000,0 ; MODE 5
VLM_6 VIDC_List 1, 36, 33, 44, 320, 44, 35, 3,16,20,250,20, 3, 8000,0 ; MODE 6
VLM_7 VIDC_List 2, 36, 31, 44, 320, 44, 37, 3,18,22,250,16, 3, 8000,0 ; MODE 7
VLM_8 VIDC_List 1, 72, 63, 88, 640, 88, 73, 3,16,17,256,17, 3,16000,0 ; MODE 8
VLM_9 VIDC_List 2, 36, 33, 44, 320, 44, 35, 3,16,17,256,17, 3, 8000,0 ; MODE 9
VLM_10 VIDC_List 3, 36, 33, 44, 320, 44, 35, 3,16,17,256,17, 3, 8000,0 ; MODE 10
VLM_11 VIDC_List 1, 72, 63, 88, 640, 88, 73, 3,16,20,250,20, 3,16000,0 ; MODE 11
VLM_12 VIDC_List 2, 72, 63, 88, 640, 88, 73, 3,16,17,256,17, 3,16000,0 ; MODE 12
VLM_13 VIDC_List 3, 36, 33, 44, 320, 44, 35, 3,16,17,256,17, 3, 8000,0 ; MODE 13
VLM_14 VIDC_List 2, 72, 63, 88, 640, 88, 73, 3,16,20,250,20, 3,16000,0 ; MODE 14
VLM_15 VIDC_List 3, 72, 63, 88, 640, 88, 73, 3,16,17,256,17, 3,16000,0 ; MODE 15
VLM_16 VIDC_List 2,112, 47,132,1056,132, 57, 3,16,17,256,17, 3,24000,0 ; MODE 16
VLM_17 VIDC_List 2,112, 47,132,1056,132, 57, 3,16,20,250,20, 3,24000,0 ; MODE 17
VLM_18 VIDC_List 0, 56,111, 2, 640, 2, 85, 3,17, 1,512, 1, 0,24000,0 ; MODE 18
VLM_19 VIDC_List 1, 56,111, 2, 640, 2, 85, 3,17, 1,512, 1, 0,24000,0 ; MODE 19
VLM_20 VIDC_List 2, 56,111, 2, 640, 2, 85, 3,17, 1,512, 1, 0,24000,0 ; MODE 20
VLM_21 VIDC_List 3, 56,111, 2, 640, 2, 85, 3,17, 1,512, 1, 0,24000,0 ; MODE 21
VLM_24 VIDC_List 3,112, 47,132,1056,132, 57, 3,16,17,256,17, 3,24000,0 ; MODE 24
VLM_25 VIDC_List 0, 96, 47, 0, 640, 0, 15, 2,32, 0,480, 0,11,25175,3 ; MODE 25
VLM_26 VIDC_List 1, 96, 47, 0, 640, 0, 15, 2,32, 0,480, 0,11,25175,3 ; MODE 26
VLM_27 VIDC_List 2, 96, 47, 0, 640, 0, 15, 2,32, 0,480, 0,11,25175,3 ; MODE 27
VLM_28 VIDC_List 3, 96, 47, 0, 640, 0, 15, 2,32, 0,480, 0,11,25175,3 ; MODE 28
VLM_31 VIDC_List 2, 72,129, 0, 800, 0, 23, 2,22, 0,600, 0, 1,36000,0 ; MODE 31
VLH_23 VIDC_List 2, 52, 47, 2, 288, 2, 1, 3,43, 4,896, 4, 0,24000,0 ; MODE 23
[ {FALSE} ; This mode not supported by VIDC, so not used
V32tab1
VIDC_List 0,36,73,24,320,24,35, 3,18,18,256,17,0,8000,0
]
V32tab2 ; MODES 1,5
VIDC_List 1,36,73,24,320,24,35, 3,18,18,256,17,0,8000,0
V32tab2T ; MODE 6
VIDC_List 1,36,73,24,320,24,35, 3,18,22,250,19,0,8000,0
V32tab4 ; MODES 2,9
VIDC_List 2,36,73,24,320,24,35, 3,18,18,256,17,0,8000,0
V32tab4T ; MODE 7
VIDC_List 2,36,73,24,320,24,35, 3,18,22,250,19,0,8000,0
V32tab8 ; MODES 10,13
VIDC_List 3,36,73,24,320,24,35, 3,18,18,256,17,0,8000,0
V64tab1 ; MODES 0,4
VIDC_List 0,72,145,48,640,48,71, 3,18,18,256,17,0,16000,0
V64tab2 ; MODE 8
VIDC_List 1,72,145,48,640,48,71, 3,18,18,256,17,0,16000,0
V64tab2T ; MODES 3,11
VIDC_List 1,72,145,48,640,48,71, 3,18,22,250,19,0,16000,0
V64tab4 ; MODE 12
VIDC_List 2,72,145,48,640,48,71, 3,18,18,256,17,0,16000,0
V64tab4T ; MODE 14
VIDC_List 2,72,145,48,640,48,71, 3,18,22,250,19,0,16000,0
V64tab8 ; MODE 15
VIDC_List 3,72,145,48,640,48,71, 3,18,18,256,17,0,16000,0
V132tab4 ; MODE 16
VIDC_List 2,72,215,46,1056,46,101, 3,18,18,256,17,0,24000,0
V132tab4T ; MODE 17
VIDC_List 2,72,215,46,1056,46,101, 3,18,22,250,19,0,24000,0
[ {TRUE}
V64tab1D ; MODE 18
VIDC_List 0,56,183,2,640,2,13, 3,17,1,512,1,0,24000,0
V64tab2D ; MODE 19
VIDC_List 1,56,183,2,640,2,13, 3,17,1,512,1,0,24000,0
V64tab4D ; MODE 20
VIDC_List 2,56,183,2,640,2,13, 3,17,1,512,1,0,24000,0
V64tab8D ; MODE 21 (NEW)
VIDC_List 3,56,183,2,640,2,13, 3,17,1,512,1,0,24000,0
[ {FALSE} ; not used any more
V128tab1 ; MODE 22
VIDC_List 2,54,39,2,320,2,7, 2,44,1,976,1,0,24000,0
]
V115tab1 ; MODE 23 new Unoid monitor style, 1152x896
; changed again 29-Jul-88 to give 64.4Hz
VIDC_List 2,52,47,2,288,2,1, 3,43,4,896,4,0,24000,0
|
V64tab1D ; MODE 18 (old)
VIDC_List 0,56,199,2,640,2,1, 3,17,1,512,1,0,24000,0
V64tab2D ; MODE 19 (old)
VIDC_List 1,56,199,2,640,2,1, 3,17,1,512,1,0,24000,0
V64tab4D ; MODE 20 (old)
VIDC_List 2,56,199,2,640,2,1, 3,17,1,512,1,0,24000,0
V128tab1 ; MODE 22 (old)
VIDC_List 2,60,41,0,320,0,3, 2,44,1,976,1,0,24000,0
V115tab1 ; MODE 23
VIDC_List 2,60,41,16,288,16,3, 2,44,57,864,57,0,24000,0
]
V132tab8 ; MODE 24 (NEW)
VIDC_List 3,72,215,46,1056,46,101, 3,18,18,256,17,0,24000,0
[ {FALSE} ; This mode not supported by VIDC, so not used
V32tab1
& &803FC000
& &84044000
& &880D8000
& &8C0E4000
& &90364000
& &943B8000
& &9C200000
& &A04DC000
& &A4008000
& &A8050000
& &AC098000
& &B0498000
& &B44DC000
& &E0000030
& -1
]
V32tab2 ; MODES 1,5
& &803FC000
& &84044000
& &880D8000
& &8C0F4000
& &90374000
& &943B8000
& &9C200000
& &A04DC000
& &A4008000
& &A8050000
& &AC098000
& &B0498000
& &B44DC000
& &E0000034
& -1
V32tab2T ; MODE 6
& &803FC000
& &84044000
& &880D8000
& &8C0F4000
& &90374000
& &943B8000
& &9C200000
& &A04DC000
& &A4008000
& &A8050000
& &AC0A8000 ; start 4 pixels down
& &B0490000 ; end 2 pixels up
& &B44DC000
& &E0000034
& -1
V32tab4 ; MODES 2,9
& &803FC000
& &84044000
& &880D8000
& &8C0FC000
& &9037C000
& &943B8000
& &9C200000
& &A04DC000
& &A4008000
& &A8050000
& &AC098000
& &B0498000
& &B44DC000
& &E0000038
& -1
V32tab4T ; MODE 7
& &803FC000
& &84044000
& &880D8000
& &8C0FC000
& &9037C000
& &943B8000
& &9C200000
& &A04DC000
& &A4008000
& &A8050000
& &AC0A8000 ; start 4 pixels down
& &B0490000 ; end 2 pixels up
& &B44DC000
& &E0000038
& -1
V32tab8 ; MODES 10,13
& &803FC000
& &84044000
& &880D8000
& &8C100000
& &90380000
& &943B8000
& &9C200000
& &A04DC000
& &A4008000
& &A8050000
& &AC098000
& &B0498000
& &B44DC000
& &E000002C
& -1
V64tab1 ; MODES 0,4
& &807FC000
& &8408C000
& &881B0000
& &8C1EC000
& &906EC000
& &94770000
& &9C400000
& &A04DC000
& &A4008000
& &A8050000
& &AC098000
& &B0498000
& &B44DC000
& &E0000032
& -1
V64tab2 ; MODE 8
& &807FC000
& &8408C000
& &881B0000
& &8C1FC000
& &906FC000
& &94770000
& &9C400000
& &A04DC000
& &A4008000
& &A8050000
& &AC098000
& &B0498000
& &B44DC000
& &E0000036
& -1
V64tab2T ; MODES 3,11
& &807FC000
& &8408C000
& &881B0000
& &8C1FC000
& &906FC000
& &94770000
& &9C400000
& &A04DC000
& &A4008000
& &A8050000
& &AC0A8000 ; Start 4 pixels down
& &B0490000 ; End 2 pixels up
& &B44DC000
& &E0000036
& -1
V64tab4 ; MODE 12
& &807FC000
& &8408C000
& &881B0000
& &8C204000
& &90704000
& &94770000
& &9C400000
& &A04DC000
& &A4008000
& &A8050000
& &AC098000
& &B0498000
& &B44DC000
& &E000002A
& -1
V64tab4T ; MODE 14
& &807FC000
& &8408C000
& &881B0000
& &8C204000
& &90704000
& &94770000
& &9C400000
& &A04DC000
& &A4008000
& &A8050000
& &AC0A8000 ; Start 4 pixels down
& &B0490000 ; End 2 pixels up
& &B44DC000
& &E000002A
& -1
V64tab8 ; MODE 15
& &807FC000
& &8408C000
& &881B0000
& &8C208000
& &90708000
& &94770000
& &9C400000
& &A04DC000
& &A4008000
& &A8050000
& &AC098000
& &B0498000
& &B44DC000
& &E000001E
& -1
V132tab4 ; MODE 16
& &80BFC000
& &8408C000
& &8823C000 ; 1B0000