Commits (29)
  • Ben Avison's avatar
    "Unknown OS_PlatformFeatures reason code" now has a non-zero error number. · b2c2bc9e
    Ben Avison authored
    Detail:
      Error number &1F3 allocated.
    Admin:
      Requires HdrSrc 1.63.
      Fix supplied by Rob Sprowson.
    
    Version 5.35, 4.79.2.99. Tagged as 'Kernel-5_35-4_79_2_99'
    b2c2bc9e
  • John Ballance's avatar
    Datestamp of kernel for 5.15 build · fdebe479
    John Ballance authored
    Detail:
        Version file updated
    Admin:
        John Ballance, Castle
    
    Version 5.35, 4.79.2.100. Tagged as 'Kernel-5_35-4_79_2_100'
    fdebe479
  • Ben Avison's avatar
    Increased Kernel version number to 5.15. · 40949773
    Ben Avison authored
    Detail:
      Castle seems to have settled on an official 5.14 build, so changed our
      version to distinguish our test builds from the official one.
    Admin:
      No testing required
    
    Version 5.35, 4.79.2.101. Tagged as 'Kernel-5_35-4_79_2_101'
    40949773
  • Ben Avison's avatar
    Build fix · 0538bbba
    Ben Avison authored
    Detail:
      Some users reported problems building the sources if they had other
      installations of perl on their build machine. The build system was using a
      mixture of "perl" and "<Perl$Dir>.perl" to invoke the interpreter, and
      sometimes but not always using "do" to expand system variables on the
      command line. This has now been standardised to use "do <Perl$Dir>.perl in
      all cases, and where possible, to use the makefile macro ${PERL}.
    Admin:
      Checked that a Tungsten build still works on a build machine with no other
      perl installation. "perl" was aliased to an error to ensure it wasn't used.
    
    Version 5.35, 4.79.2.102. Tagged as 'Kernel-5_35-4_79_2_102'
    0538bbba
  • Ben Avison's avatar
    Added comment · 9e7233fb
    Ben Avison authored
    Detail:
      Noted reservation of IO controller type  passed to OS_Memory 9 used when
      system is running as a coprocessor. Not used by current code but we need to
      make sure that any future reservations use different numbers.
    Admin:
      No functional change. Brought to our attention by Rob Sprowson.
    
    Version 5.35, 4.79.2.103. Tagged as 'Kernel-5_35-4_79_2_103'
    9e7233fb
  • Jeffrey Lee's avatar
    Fix error handling for sparse dynamic area resize operations (for main HAL branch) · d0ddc243
    Jeffrey Lee authored
    Detail:
      s/ChangeDyn - Swap CMP with TEQ to avoid accidental clobbering of V flag before its state is checked on return from a SWI. Errors encounterd during sparse dynamic area resize operations (OS_DynamicArea 9 & 10) should now be reported properly.
    Admin:
      Not tested, but the same fix has been proven to work on the Cortex branch.
    
    
    Version 5.35, 4.79.2.104. Tagged as 'Kernel-5_35-4_79_2_104'
    d0ddc243
  • Ben Avison's avatar
    Build fix · 62fb1997
    Ben Avison authored
    Detail:
      Hdr:Macros has just been changed on the trunk in such a way that you now
      need to include Hdr:CPU.Arch as well. Previously this include file was only
      referenced by the Cortex branch kernel - now mirrored on the HAL branch
      kernel too.
    Admin:
      Verified that IOMD ROM now builds again - should fix Tungsten ROM build too.
    
    Version 5.35, 4.79.2.105. Tagged as 'Kernel-5_35-4_79_2_105'
    62fb1997
  • Jeffrey Lee's avatar
    Fix bug when creating code variables via OS_SetVarVal (HAL branch) · 9fe47897
    Jeffrey Lee authored
    Detail:
      OS_SetVarVal was failing to call XOS_SynchroniseCodeAreas after copying the code variables code block into the system heap. This has now been fixed.
    Admin:
      Fix tested in Cortex branch on rev C2 beagleboard. Debugger module now shows the right register names instead of ofla!
    
    
    Version 5.35, 4.79.2.106. Tagged as 'Kernel-5_35-4_79_2_106'
    9fe47897
  • John Ballance's avatar
    modified s.PMF.osword to cope with the iyonix RTC operating in BCD · 23e2c1e0
    John Ballance authored
    Also upissued to RISC OS 5.16 to release this in ROM
    Detail:
      (list files and functions that have changed)
    Admin:
    tested at Castle (JB)
      (highlight level of testing that has taken place)
      (bugfix number if appropriate)
    
    
    Version 5.35, 4.79.2.107. Tagged as 'Kernel-5_35-4_79_2_107'
    23e2c1e0
  • Steve Revill's avatar
    Incremented RISC OS version for the HAL branch to next development number (5.17). · dc03d9c3
    Steve Revill authored
    Version 5.35, 4.79.2.108. Tagged as 'Kernel-5_35-4_79_2_108'
    dc03d9c3
  • Jeffrey Lee's avatar
    Fix bug in InitCMOSCache that could cause CMOS to be errouneously reset if... · ed3cc555
    Jeffrey Lee authored
    Fix bug in InitCMOSCache that could cause CMOS to be errouneously reset if NVRAM is of type 'MaybeIIC'
    
    Detail:
      s/PMF/i2cutils - Kernel was checking if the full IIC flags word was equal to MaybeIIC instead of just checking if the Provision bits equalled MaybeIIC. Thus if any of the additional flags were set along with MaybeIIC the kernel would have skipped the probing code, skipped the IIC code, and fallen through to using the (likely unimplemented) HAL interface for initialising the NVRAM cache.
    Admin:
      Tested in IOMD build under RPCemu; kernel now takes the correct path for MaybeIIC + ProtectAtEnd.
    
    
    Version 5.35, 4.79.2.109. Tagged as 'Kernel-5_35-4_79_2_109'
    ed3cc555
  • Jeffrey Lee's avatar
    Fix detection of Philips RTC/NVRAM when MaybeIIC is in use · a6492b14
    Jeffrey Lee authored
    Detail:
      s/PMF/i2cutils - Although the code will detect the Philips RTC correctly, it was failing to set the device size in R4, causing CMOS RAM to be misread. This change fixes that.
    Admin:
      Tested in IOMD HAL build on development version of RPCEmu.
    
    
    Version 5.35, 4.79.2.110. Tagged as 'Kernel-5_35-4_79_2_110'
    a6492b14
  • Jeffrey Lee's avatar
    Bring HAL branch of hdr/HALDevice, h/HALDevice in line with Cortex branch · ff0710fa
    Jeffrey Lee authored
    Detail:
      A fair number of bus/device types and IDs have been added to the Cortex branch since the branch was created.
      Now that the ClearIRQ entry has also been added, it's about time that the HAL branch was brought up to date.
    Admin:
      Untested, but should be fine.
    
    
    Version 5.35, 4.79.2.111. Tagged as 'Kernel-5_35-4_79_2_111'
    ff0710fa
  • Jeffrey Lee's avatar
    Add C version of Hdr.OSEntries to HAL kernel header export · 77d5848c
    Jeffrey Lee authored
    Detail:
      Makefile - now exports a C version of hdr.OSEntries
    Admin:
      Tested in Iyonix ROM softload.
      Needed for latest USB drivers to build.
    
    
    Version 5.35, 4.79.2.112. Tagged as 'Kernel-5_35-4_79_2_112'
    77d5848c
  • Jeffrey Lee's avatar
    Add hdr.Variables to C header export · 819b8458
    Jeffrey Lee authored
    Detail:
      Makefile - Added hdr.Variables to the C header export list
    Admin:
      Fixes build errors with the latest Draw module
    
    
    Version 5.35, 4.79.2.113. Tagged as 'Kernel-5_35-4_79_2_113'
    819b8458
  • Jeffrey Lee's avatar
    Update list of OS_Memory 9 controllers · e339bdd5
    Jeffrey Lee authored
    Detail:
      s/MemInfo - List of OS_Memory 9 controllers now updated to include details of the ones that ROL are using, along with which numbers should/shouldn't be safe for us to expand into in the future.
    Admin:
      Tested in ROM softload on RiscPC
    
    
    Version 5.35, 4.79.2.114. Tagged as 'Kernel-5_35-4_79_2_114'
    e339bdd5
  • Jeffrey Lee's avatar
    Update the method the HAL kernel uses to determine the UtilityModule & ROM dates · e249f5da
    Jeffrey Lee authored
    Detail:
      Three main changes:
      * On odd-numbered (i.e. development) versions of the module, the UtilityModule will now take its date from the VersionNum file instead of using a hard-coded date
      * All build versions now look for the new "extended ROM footer" (as created by romlinker 0.04+) at the end of the ROM image and use it to determine the ROM build date for return by OS_ReadSysInfo 9,2. Failing to find the build date in the footer will cause OS_ReadSysInfo 9,2 to return 0.
      * On odd-numbered versions, OS_Byte 0 will now use the ROM build date (as found in the extended footer) to generate the error block that's returned to the user. This seems OK as the PRM describes OS_Byte 0 as returning the "creation date of the operating system". Plus it's a convenient way of getting the ROM build date into the Switcher, since the switcher uses OS_Byte 0. If the extended footer can't be found (or if the string isn't initialised yet, e.g. before Service_PostInit) the code falls back to a hard-coded string containing the date from the VersionNum file.
      File changes:
      Makefile - Updated to not create the obsolete Time+Date file (previously used for the ROM build date)
      Version - Use date from VersionNum file for development builds
      hdr/Options - New UseNewFX0Error variable/option to make it easy to check which OS_Byte 0 variant should be enabled
      hdr/KernelWS - Added new string buffers & extended ROM footer pointer to workspace
      s/Middle - Updated OS_ReadSysInfo 9 code, and added utility functions for searching the extended ROM footer for certain tags
      s/NewReset - Added a couple of calls to initialise the new string buffers just prior to Service_PostInit. This is required since OS_Byte/OS_ReadSysInfo shouldn't enable interrupts, but date conversion relies on the Territory module, which may enable interrupts.
      s/PMF/osbyte - Updated OS_Byte 0 code
    Admin:
      Tested in Tungsten ROM, with and without the extended footer present.
    
    
    Version 5.35, 4.79.2.115. Tagged as 'Kernel-5_35-4_79_2_115'
    e249f5da
  • Jeffrey Lee's avatar
    Keep hdr/HALDevice & hdr/HALEntries in sync with Cortex branch · afae51e2
    Jeffrey Lee authored
    Detail:
      hdr/HALDevice - Device types & IDs for CPU clock generator and GPIO interface
      hdr/HALEntries - HAL_ExtMachineID entry (but not used by this kernel yet)
    Admin:
      Tungsten ROM built OK, but untested at runtime.
    
    
    Version 5.35, 4.79.2.116. Tagged as 'Kernel-5_35-4_79_2_116'
    afae51e2
  • Jeffrey Lee's avatar
    Update 'perl' to '${PERL}' · 7f86b773
    Jeffrey Lee authored
    Detail:
      Makefile - A couple of makefile rules were invoking perl directly instead of using the more preferential ${PERL}. Fixed.
    Admin:
      Tungsten ROM compiles OK, untested at runtime.
    
    
    Version 5.35, 4.79.2.117. Tagged as 'Kernel-5_35-4_79_2_117'
    7f86b773
  • Jeffrey Lee's avatar
    Add new OS_ReadSysInfo 6 items codes. Change naming of PublicWS values. · b1bc3052
    Jeffrey Lee authored
    Detail:
      s/Middle - Added some new OS_ReadSysInfo 6 items which are needed by the zero page relocation kernel. Also duplicated some existing entries to avoid conflicts with ROL's allocations.
      hdr/OSRSI6, Makefile - New header listing OS_ReadSysInfo 6 items
      hdr/PublicWS - Duplicated the workspace definitions for &0-&4000, but with a 'Legacy_' prefix to their names. Also added some new entries as needed by the zero page relocation kernel. Once existing modules have been updated to use OS_ReadSysInfo & the Legacy_ definitions, the old defs will be removed.
      hdr/KernelWS - Removed 'Export_' prefix from all the exported workspace values, since the kernel can now use the original names directly
      hdr/Options - Dummy HiProcVecs option so merging things will be a bit cleaner
    Admin:
      Tested in ROM softload on Iyonix
    
    
    Version 5.35, 4.79.2.118. Tagged as 'Kernel-5_35-4_79_2_118'
    b1bc3052
  • Jeffrey Lee's avatar
    Correct version number in header comment · 61428ee7
    Jeffrey Lee authored
    Detail:
      hdr/OSRSI6 - Corrected RO version number from 5.19 to 5.17
    Admin:
      Untested, but testing shouldn't be needed anyway
    
    
    Version 5.35, 4.79.2.119. Tagged as 'Kernel-5_35-4_79_2_119'
    61428ee7
  • Jeffrey Lee's avatar
    Merge over some changes from the Cortex branch · fef39aba
    Jeffrey Lee authored
    Detail:
      hdr/ARMops - Reserve OS_PlatformFeatures 0 bit 20 for indicating whether high processor vectors are in use
      s/Kernel - Add local definitions of BYTEWS, LDROSB, STROSB, VDWS macros (previously in Hdr:Macros)
      s/MoreComms - Fix potential buffer overflow when filling error buffer (although GSTrans shouldn't overflow the buffer in the first place?)
      s/Arthur2 - GSRead number detection fix
      s/ArthurSWIs - Updated OS_ReadUnsigned to support reading 64bit numbers
      Docs/ReadUnsigned - Docs for the updated OS_ReadUnsigned interface
    Admin:
      Untested!
      Needs HdrSrc 1.86
    
    
    Version 5.35, 4.79.2.120. Tagged as 'Kernel-5_35-4_79_2_120'
    fef39aba
  • Jeffrey Lee's avatar
    Add ESC_Status to list of OS_ReadSysInfo 6 items · 37162926
    Jeffrey Lee authored
    Detail:
      hdr/OSRSI6, s/Middle - Added ESC_Status to the list of items that OS_ReadSysInfo 6 exports
    Admin:
      Tested in ROM softload on Iyonix
    
    
    Version 5.35, 4.79.2.121. Tagged as 'Kernel-5_35-4_79_2_121'
    37162926
  • Jeffrey Lee's avatar
    ARMv7 fixes · 2dfd92c1
    Jeffrey Lee authored
    Detail:
      hdr/Copro15ops:
        - Fixed incorrect encodings of ISH/ISHST variants of DMB/DSB instructions
      s/ARMops, s/HAL, hdr/KernelWS:
        - Replace the ARMv7 cache maintenance code with the example code from the ARMv7 ARM. This allows it to deal with caches with non power-of-two set/way counts, and caches with only one way.
        - Fixed Analyse_WB_CR7_Lx to use the cache level ID register to work out how many caches to query instead of just looking for a 0 result from CSSIDR.
        - Also only look for 7 cache levels, since level 8 doesn't exist according to the ARMv7 ARM.
      s/NewReset:
        - Removed some incorrect/misleading debug output
    Admin:
      Tested on rev A2 BB-xM
    
    
    Version 5.35, 4.79.2.98.2.51. Tagged as 'Kernel-5_35-4_79_2_98_2_51'
    2dfd92c1
  • Jeffrey Lee's avatar
    Fix Cache_InvalidateAll_WB_CR7_Lx to do what it says on the tin · af172483
    Jeffrey Lee authored
    Detail:
      s/ARMops - My previous checkin mistakenly changed Cache_InvalidateAll_WB_CR7_Lx so that it cleans and invalidates the cache instead of just invalidating it. This fixes that.
      Also fixed a warning caused by the trailing space going AWOL from the 'cache type register fields' comment.
    Admin:
      Tested on rev A2 BB-xM
    
    
    Version 5.35, 4.79.2.98.2.52. Tagged as 'Kernel-5_35-4_79_2_98_2_52'
    af172483
  • Jeffrey Lee's avatar
    Fix objasm 4 warnings · 6d052230
    Jeffrey Lee authored
    Detail:
      s/Arthur3, s/ChangeDyn, s/HAL, s/HeapMan, s/Middle, s/MoreSWIs, s/NewIRQs, s/Utility, s/VMSAv6, s/PMF/key, s/PMF/osbyte, s/PMF/osword, s/vdu/vdudecl, s/vdu/vdudriver, s/vdu/vduplot, s/vdu/vduwrch - Tweaked lots of LDM/STM instructions in order to get rid of the depracation/performance warnings
    Admin:
      Tested on rev A2 BB-xM
    
    
    Version 5.35, 4.79.2.98.2.53. Tagged as 'Kernel-5_35-4_79_2_98_2_53'
    6d052230
  • Ben Avison's avatar
    Added definitions to Hdr:HALDevice required by SDIODriver · e4f67669
    Ben Avison authored
    Version 5.35, 4.79.2.98.2.54. Tagged as 'Kernel-5_35-4_79_2_98_2_54'
    e4f67669
  • Ben Avison's avatar
    Resync Hdr:HALDevice on HAL branch (nominally the master copy) with the Cortex branch · 987a3ec3
    Ben Avison authored
    Version 5.35, 4.79.2.122. Tagged as 'Kernel-5_35-4_79_2_122'
    987a3ec3
  • Jeffrey Lee's avatar
    Merge Cortex kernel into HAL branch · 50f95feb
    Jeffrey Lee authored
    Detail:
      This is a full merge of the Cortex kernel back into the HAL branch. Since the Cortex kernel is/was just a superset of the HAL branch, at this point in time both branches are identical.
      Main features the HAL branch gains from this merge:
      - ARMv6/ARMv7 support
      - High processor vectors/zero page relocation support
      - objasm 4 warning fixes
      - Improved HAL related functionality:
        - Support for HAL-driven RTCs instead of kernel-driven IIC based ones
        - Support for arbitrary size machine IDs
        - Support for multiple IIC busses
        - Support for any HAL size, instead of hardcoded 64k size
        - Probably some other stuff I've forgotten
      - Probably a few bug fixes here and there
    Admin:
      Tested on BB-xM & Iyonix.
      Was successfully flashed to ROM on an Iyonix to test the Cortex branch implementation of the 2010 RTC bug fix.
      IOMD build untested - but has been known to work in the past.
    
    
    Version 5.35, 4.79.2.123. Tagged as 'Kernel-5_35-4_79_2_123'
    50f95feb
......@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.98.2.50"
Module_Date SETS "12 Sep 2011"
Module_ApplicationDate SETS "12-Sep-11"
Module_MinorVersion SETS "4.79.2.123"
Module_Date SETS "26 Nov 2011"
Module_ApplicationDate SETS "26-Nov-11"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.98.2.50)"
Module_HelpVersion SETS "5.35 (12 Sep 2011) 4.79.2.98.2.50"
Module_FullVersion SETS "5.35 (4.79.2.123)"
Module_HelpVersion SETS "5.35 (26 Nov 2011) 4.79.2.123"
END
......@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.98.2.50
#define Module_Date_CMHG 12 Sep 2011
#define Module_MinorVersion_CMHG 4.79.2.123
#define Module_Date_CMHG 26 Nov 2011
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.98.2.50"
#define Module_Date "12 Sep 2011"
#define Module_MinorVersion "4.79.2.123"
#define Module_Date "26 Nov 2011"
#define Module_ApplicationDate "12-Sep-11"
#define Module_ApplicationDate "26-Nov-11"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.98.2.50)"
#define Module_HelpVersion "5.35 (12 Sep 2011) 4.79.2.98.2.50"
#define Module_FullVersion "5.35 (4.79.2.123)"
#define Module_HelpVersion "5.35 (26 Nov 2011) 4.79.2.123"
#define Module_LibraryVersionInfo "5:35"
......@@ -605,10 +605,10 @@ C15 CN 15
DCI &F57FF04E ; DSB ST
|
[ "$option"="ISH"
DCI &F57FF04D ; DSB ISH
DCI &F57FF04B ; DSB ISH
|
[ "$option"="ISHST"
DCI &F57FF04C ; DSB ISHST
DCI &F57FF04A ; DSB ISHST
|
[ "$option"="NSH"
DCI &F57FF047 ; DSB NSH
......@@ -656,10 +656,10 @@ C15 CN 15
DCI &F57FF05E ; DMB ST
|
[ "$option"="ISH"
DCI &F57FF05D ; DMB ISH
DCI &F57FF05B ; DMB ISH
|
[ "$option"="ISHST"
DCI &F57FF05C ; DMB ISHST
DCI &F57FF05A ; DMB ISHST
|
[ "$option"="NSH"
DCI &F57FF057 ; DMB NSH
......
......@@ -66,6 +66,10 @@ HALDeviceComms_UART # 1 ; UART
HALDeviceComms_EtherNIC # 1 ; Ethernet NIC
HALDeviceComms_GPIO # 1 ; GPIO interface
HALDeviceType_ExpCtl * 5 :SHL: 8
^ 1
HALDeviceExpCtl_SDIO # 1 ; SD/SDIO host controller
; things like USB, FireWire, SATA, SAS controllers might go here
HALDeviceBus_Pro * 0 :SHL: 28
......@@ -143,6 +147,9 @@ HALDeviceID_EtherNIC_DM9000 # 1
HALDeviceID_GPIO_OMAP3 # 1
HALDeviceID_GPIO_OMAP4 # 1
^ 0
HALDeviceID_SDIO_SDHCI # 1
] ; Included_Hdr_HALDevice
OPT OldOpt
......
......@@ -1323,8 +1323,8 @@ MMUControlSoftCopy # 4 ; Soft copy of ARM control register
DeviceCount # 4 ; size of our table of devices in the system heap
DeviceTable # 4 ; pointer to table
Cache_Lx_Info # 4 ; Cache level ID register
Cache_Lx_DTable # 4*8 ; Data/unified cache layout for all 8 levels
Cache_Lx_ITable # 4*8 ; Instruction cache layout for all 8 levels
Cache_Lx_DTable # 4*7 ; Data/unified cache layout for all 7 levels
Cache_Lx_ITable # 4*7 ; Instruction cache layout for all 7 levels
]
AplWorkSize * AppSpaceDANode + DANode_Size
......
......@@ -529,29 +529,42 @@ Analyse_WB_CR7_Lx
MRC p15, 1, a1, c0, c0, 1 ; Cache level ID register
MOV v2, v6 ; Work around DTable/ITable alignment issues
STR a1, [v2, #Cache_Lx_Info]!
ADD a1, v2, #Cache_Lx_DTable-Cache_Lx_Info
ADD a2, v2, #Cache_Lx_ITable-Cache_Lx_Info
ADD a2, v2, #Cache_Lx_DTable-Cache_Lx_Info
MOV a3, #0
MOV a4, #256 ; Smallest instruction cache line length
MOV v2, #256 ; Smallest data/unified cache line length (although atm we only need this to be the smallest data cache line length)
10
MCR p15, 2, a3, c0, c0, 0 ; Program cache size selection register
MRC p15, 1, v1, c0, c0, 0 ; Get size info (data/unified)
STR v1, [a1],#4
CMP v1, #0 ; Does the cache exist?
ANDS v1, a1, #6 ; Data or unified cache at this level?
MCRNE p15, 2, a3, c0, c0, 0 ; Program cache size selection register
myISB ,v1
MRCNE p15, 1, v1, c0, c0, 0 ; Get size info (data/unified)
STR v1, [a2]
AND v1, v1, #7 ; Get line size
CMPNE v1, v2
MOVLT v2, v1 ; Earlier CMP will not set LE flags if v1=0
CMP v1, v2
MOVLT v2, v1
ADD a3, a3, #1
MCR p15, 2, a3, c0, c0, 0 ; Program cache size selection register
MRC p15, 1, v1, c0, c0, 0 ; Get size info (instruction)
STR v1, [a2],#4
CMP v1, #0 ; Does the cache exist?
ANDS v1, a1, #1 ; Instruction cache at this level?
MCRNE p15, 2, a3, c0, c0, 0 ; Program cache size selection register
myISB ,v1
MRCNE p15, 1, v1, c0, c0, 0 ; Get size info (instruction)
STR v1, [a2, #Cache_Lx_ITable-Cache_Lx_DTable]
AND v1, v1, #7 ; Get line size
CMPNE v1, a4
MOVLT a4, v1 ; Earlier CMP will not set LE flags if v1=0
CMP v1, a4
MOVLT a4, v1
; Shift the cache level ID register along to get the type of the next
; cache level
; However, we need to stop once we reach the first blank entry, because
; ARM have been sneaky and started to reuse some of the bits from the
; high end of the register (the Cortex-A8 TRM lists bits 21-23 as being
; for cache level 8, but the ARMv7 ARM lists them as being for the level
; of unification for inner shareable memory). The ARMv7 ARM does warn
; about making sure you stop once you find the first blank entry, but
; it doesn't say why!
TST a1, #7
ADD a3, a3, #1
CMP a3, #16
MOVNE a1, a1, LSR #3
CMP a3, #14 ; Stop after level 7 (even though an 8th level might exist on some CPUs?)
ADD a2, a2, #4
BLT %BT10
STRB a4, [v6, #ICache_LineLen] ; Store log2(line size)-2
STRB v2, [v6, #DCache_LineLen] ; log2(line size)-2
......@@ -711,7 +724,7 @@ $var SETA $var+(CT_M_$sz:SHL:CT_M_pos)
; CPUDesc table for ARMv3-ARMv6
KnownCPUTable
; /------Cache Type register fields-----\
; /------Cache Type register fields-----\.
; ID reg Mask Arch Type S Dsz Das Dln Isz Ias Iln
CPUDesc ARM600, &000600, &00FFF0, ARMv3, WT, 0, 4K, 64, 4
CPUDesc ARM610, &000610, &00FFF0, ARMv3, WT, 0, 4K, 64, 4
......@@ -1878,150 +1891,122 @@ MMU_ChangingUncachedEntries_WB_Cal_LD ROUT
; ICache_LineLen = log2(line len)-2 for smallest instruction cache line length
; DCache_RangeThreshold = clean threshold for data cache
; Cache_Lx_Info = Cache level ID register
; Cache_Lx_DTable = Cache size identification register for all 8 data/unified caches
; Cache_Lx_ITable = Cache size identification register for all 8 instruction caches
; Cache_Lx_DTable = Cache size identification register for all 7 data/unified caches
; Cache_Lx_ITable = Cache size identification register for all 7 instruction caches
Cache_CleanAll_WB_CR7_Lx ROUT
; Clean cache by traversing all sets and ways for all data caches
Push "a2,a3,a4,v1,v2,v3,v4,v5,lr"
; ARMv7 cache maintenance routines are a bit long-winded, so we use this macro
; to reduce the risk of mistakes creeping in due to code duplication
;
; $op: Operation to perform ('clean', 'invalidate', 'cleaninvalidate')
; $levels: Which levels to apply to ('lou', 'loc', 'louis')
; Uses r0-r8 & lr as temp
; Performs the indicated op on the indicated data & unified caches
;
; Code based around the alternate/faster code given in the ARMv7 ARM (section
; B2.2.4, alternate/faster code only in doc revision 9), but tightened up a bit
;
; Note that HAL_InvalidateCache_ARMvF uses its own implementation of this
; algorithm, since it must cope with different temporary registers and it needs
; to read the cache info straight from the CP15 registers
;
MACRO
MaintainDataCache_WB_CR7_Lx $op, $levels
LDR lr, =ZeroPage
LDR a1, [lr, #Cache_Lx_Info]!
LDR r0, [lr, #Cache_Lx_Info]!
ADD lr, lr, #Cache_Lx_DTable-Cache_Lx_Info
BIC a1, a1, #&FF000000 ; Discard unification/coherency bits
MOV a2, #0 ; Current cache level
20
TST a1, #7 ; Get flags
BEQ %FT10 ; Cache clean complete
LDR a3, [lr], #4 ; Get size info
AND v1, a3, #&7 ; log2(Line size)-2
BIC a3, a3, #&F0000007 ; Clear flags & line size
MOV v2, a3, LSL #19 ; Number of ways-1 in upper 10 bits
MOV v3, a3, LSR #13 ; Number of sets-1 in lower 15 bits
; Way number needs to be packed right up at the high end of the data word; shift it up
CLZ a4, v2
MOV v2, v2, LSL a4
; Set number needs to start at log2(Line size)+2
MOV v3, v3, LSL #4 ; Start at bit 4
MOV v3, v3, LSL v1 ; Start at log2(Line size)+2
; Now calculate the offset numbers we will use to increment sets & ways
BIC v4, v2, v2, LSL #1 ; Way increment
BIC v5, v3, v3, LSL #1 ; Set increment
; Now we can finally clean this cache!
ORR a3, a2, v3 ; Current way (0), set (max), and level
30
MCR p15, 0, a3, c7, c10, 2 ; Clean
ADDS a3, a3, v4 ; Increment way
BCC %BT30 ; Overflow will occur once ways are enumerated
TST a3, v3 ; Are set bits all zero?
SUBNE a3, a3, v5 ; No, so decrement set and loop around again
BNE %BT30
; This cache is now clean. Move on to the next level.
ADD a2, a2, #2
MOVS a1, a1, LSR #3
BNE %BT20
10
myDSB ,a1 ; Wait for cache cleaning to complete
Pull "a2,a3,a4,v1,v2,v3,v4,v5,pc"
[ "$levels"="lou"
ANDS r3, r0, #&38000000
MOV r3, r3, LSR #26 ; Cache level value (naturally aligned)
|
[ "$levels"="loc"
ANDS r3, r0, #&07000000
MOV r3, r3, LSR #23 ; Cache level value (naturally aligned)
|
[ "$levels"="louis"
ANDS r3, r0, #&00E00000
MOV r3, r3, LSR #20 ; Cache level value (naturally aligned)
|
! 1, "Unrecognised levels"
]
]
]
BEQ %FT50
MOV r8, #0 ; Current cache level
10 ; Loop1
ADD r2, r8, r8, LSR #1 ; Work out 3 x cachelevel
MOV r1, r0, LSR r2 ; bottom 3 bits are the Cache type for this level
AND r1, r1, #7 ; get those 3 bits alone
CMP r1, #2
BLT %FT40 ; no cache or only instruction cache at this level
LDR r1, [lr, r8, LSL #1] ; read CCSIDR to r1
AND r2, r1, #&7 ; extract the line length field
ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
LDR r7, =&3FF
AND r7, r7, r1, LSR #3 ; r7 is the max number on the way size (right aligned)
CLZ r5, r7 ; r5 is the bit position of the way size increment
LDR r4, =&7FFF
AND r4, r4, r1, LSR #13 ; r4 is the max number of the index size (right aligned)
20 ; Loop2
MOV r1, r4 ; r1 working copy of the max index size (right aligned)
30 ; Loop3
ORR r6, r8, r7, LSL r5 ; factor in the way number and cache number into r6
ORR r6, r6, r1, LSL r2 ; factor in the index number
[ "$op"="clean"
MCR p15, 0, r6, c7, c10, 2 ; Clean
|
[ "$op"="invalidate"
MCR p15, 0, r6, c7, c6, 2 ; Invalidate
|
[ "$op"="cleaninvalidate"
MCR p15, 0, r6, c7, c14, 2 ; Clean & invalidate
|
! 1, "Unrecognised op"
]
]
]
SUBS r1, r1, #1 ; decrement the index
BGE %BT30
SUBS r7, r7, #1 ; decrement the way number
BGE %BT20
40 ; Skip
ADD r8, r8, #2
CMP r3, r8
BGT %BT10
myDSB ,r0
50 ; Finished
MEND
Cache_CleanAll_WB_CR7_Lx ROUT
; Clean cache by traversing all sets and ways for all data caches
Push "r1-r8,lr"
MaintainDataCache_WB_CR7_Lx clean, loc
Pull "r1-r8,pc"
Cache_CleanInvalidateAll_WB_CR7_Lx ROUT
;
; similar to Cache_CleanAll, but does clean&invalidate of Dcache, and invalidates ICache
;
Push "a2,a3,a4,v1,v2,v3,v4,v5,lr"
LDR lr, =ZeroPage
LDR a1, [lr, #Cache_Lx_Info]!
ADD lr, lr, #Cache_Lx_DTable-Cache_Lx_Info
BIC a1, a1, #&FF000000 ; Discard unification/coherency bits
MOV a2, #0 ; Current cache level
20
TST a1, #7 ; Get flags
BEQ %FT10 ; Cache clean complete
LDR a3, [lr], #4 ; Get size info
AND v1, a3, #&7 ; log2(Line size)-2
BIC a3, a3, #&F0000007 ; Clear flags & line size
MOV v2, a3, LSL #19 ; Number of ways-1 in upper 10 bits
MOV v3, a3, LSR #13 ; Number of sets-1 in lower 15 bits
; Way number needs to be packed right up at the high end of the data word; shift it up
CLZ a4, v2
MOV v2, v2, LSL a4
; Set number needs to start at log2(Line size)+2
MOV v3, v3, LSL #4 ; Start at bit 4
MOV v3, v3, LSL v1 ; Start at log2(Line size)+2
; Now calculate the offset numbers we will use to increment sets & ways
BIC v4, v2, v2, LSL #1 ; Way increment
BIC v5, v3, v3, LSL #1 ; Set increment
; Now we can finally clean this cache!
ORR a3, a2, v3 ; Current way (0), set (max), and level
30
MCR p15, 0, a3, c7, c14, 2 ; Clean & invalidate
ADDS a3, a3, v4 ; Increment way
BCC %BT30 ; Overflow will occur once ways are enumerated
TST a3, v3 ; Are set bits all zero?
SUBNE a3, a3, v5 ; No, so decrement set and loop around again
BNE %BT30
; This cache is now clean. Move on to the next level.
ADD a2, a2, #2
MOVS a1, a1, LSR #3
BNE %BT20
10
MOV a1, #0
myDSB ,a1,,y ; Wait for cache clean to complete
Push "r1-r8,lr"
MaintainDataCache_WB_CR7_Lx cleaninvalidate, loc
MCR p15, 0, a1, c7, c5, 0 ; invalidate ICache
MCR p15, 0, a1, c7, c5, 6 ; invalidate branch predictors
myDSB ,a1,,y ; Wait for cache/branch invalidation to complete
myISB ,a1,,y ; Ensure that the effects of the completed cache/branch invalidation are visible
Pull "a2,a3,a4,v1,v2,v3,v4,v5,pc"
Pull "r1-r8,pc"
Cache_InvalidateAll_WB_CR7_Lx ROUT
;
; no clean, assume caller knows what's happening
;
Push "a2,a3,a4,v1,v2,v3,v4,v5,lr"
LDR lr, =ZeroPage
LDR a1, [lr, #Cache_Lx_Info]!
ADD lr, lr, #Cache_Lx_DTable-Cache_Lx_Info
BIC a1, a1, #&FF000000 ; Discard unification/coherency bits
MOV a2, #0 ; Current cache level
20
TST a1, #7 ; Get flags
BEQ %FT10 ; Cache clean complete
LDR a3, [lr], #4 ; Get size info
AND v1, a3, #&7 ; log2(Line size)-2
BIC a3, a3, #&F0000007 ; Clear flags & line size
MOV v2, a3, LSL #19 ; Number of ways-1 in upper 10 bits
MOV v3, a3, LSR #13 ; Number of sets-1 in lower 15 bits
; Way number needs to be packed right up at the high end of the data word; shift it up
CLZ a4, v2
MOV v2, v2, LSL a4
; Set number needs to start at log2(Line size)+2
MOV v3, v3, LSL #4 ; Start at bit 4
MOV v3, v3, LSL v1 ; Start at log2(Line size)+2
; Now calculate the offset numbers we will use to increment sets & ways
BIC v4, v2, v2, LSL #1 ; Way increment
BIC v5, v3, v3, LSL #1 ; Set increment
; Now we can finally clean this cache!
ORR a3, a2, v3 ; Current way (0), set (max), and level
30
MCR p15, 0, a3, c7, c6, 2 ; Invalidate
ADDS a3, a3, v4 ; Increment way
BCC %BT30 ; Overflow will occur once ways are enumerated
TST a3, v3 ; Are set bits all zero?
SUBNE a3, a3, v5 ; No, so decrement set and loop around again
BNE %BT30
; This cache is now clean. Move on to the next level.
ADD a2, a2, #2
MOVS a1, a1, LSR #3
BNE %BT20
10
MOV a1, #0
myDSB ,a1,,y ; Wait for invalidation to complete
Push "r1-r8,lr"
MaintainDataCache_WB_CR7_Lx invalidate, loc
MCR p15, 0, a1, c7, c5, 0 ; invalidate ICache
MCR p15, 0, a1, c7, c5, 6 ; invalidate branch predictors
myDSB ,a1,,y ; Wait for cache/branch invalidation to complete
myISB ,a1,,y ; Ensure that the effects of the completed cache/branch invalidation are visible
Pull "a2,a3,a4,v1,v2,v3,v4,v5,pc"
Pull "r1-r8,pc"
Cache_RangeThreshold_WB_CR7_Lx ROUT
......@@ -2073,51 +2058,13 @@ IMB_Full_WB_CR7_Lx ROUT
; do: clean DCache; drain WBuffer, invalidate ICache/branch predictor
; Luckily, we only need to clean as far as the level of unification
;
Push "a2,a3,a4,v1,v2,v3,v4,v5,lr"
LDR lr, =ZeroPage
LDR a1, [lr, #Cache_Lx_Info]!
ADD lr, lr, #Cache_Lx_DTable-Cache_Lx_Info
MOV a1, a1, LSR #27
AND a1, a1, #&7 ; Get level of unification
MOV a2, #0 ; Current cache level
SUBS a1, a1, #1
BLT %FT10 ; Cache clean complete
20
LDR a3, [lr], #4 ; Get size info
AND v1, a3, #&7 ; log2(Line size)-2
BIC a3, a3, #&F0000007 ; Clear flags & line size
MOV v2, a3, LSL #19 ; Number of ways-1 in upper 10 bits
MOV v3, a3, LSR #13 ; Number of sets-1 in lower 15 bits
; Way number needs to be packed right up at the high end of the data word; shift it up
CLZ a4, v2
MOV v2, v2, LSL a4
; Set number needs to start at log2(Line size)+2
MOV v3, v3, LSL #4 ; Start at bit 4
MOV v3, v3, LSL v1 ; Start at log2(Line size)+2
; Now calculate the offset numbers we will use to increment sets & ways
BIC v4, v2, v2, LSL #1 ; Way increment
BIC v5, v3, v3, LSL #1 ; Set increment
; Now we can finally clean this cache!
ORR a3, a2, v3 ; Current way (0), set (max), and level
30
MCR p15, 0, a3, c7, c10, 2 ; Clean
ADDS a3, a3, v4 ; Increment way
BCC %BT30 ; Overflow will occur once ways are enumerated
TST a3, v3 ; Are set bits all zero?
SUBNE a3, a3, v5 ; No, so decrement set and loop around again
BNE %BT30
; This cache is now clean. Move on to the next level.
ADD a2, a2, #2
SUBS a1, a1, #1
BGE %BT20
10
MOV a1, #0
myDSB ,a1,,y ; Wait for clean to complete
Push "r1-r8,lr"
MaintainDataCache_WB_CR7_Lx clean, lou
MCR p15, 0, a1, c7, c5, 0 ; invalidate ICache
MCR p15, 0, a1, c7, c5, 6 ; invalidate branch predictors
myDSB ,a1,,y ; Wait for cache/branch invalidation to complete
myISB ,a1,,y ; Ensure that the effects of the completed cache/branch invalidation are visible
Pull "a2,a3,a4,v1,v2,v3,v4,v5,pc"
Pull "r1-r8,pc"
; a1 = start address (inclusive, cache line aligned)
; a2 = end address (exclusive, cache line aligned)
......@@ -2160,7 +2107,7 @@ MMU_Changing_WB_CR7_Lx ROUT
BL Cache_CleanInvalidateAll_WB_CR7_Lx
MOV a1, #0
MCR p15, 0, a1, c8, c7, 0 ; invalidate ITLB and DTLB
myDSB ,a1,,y ; Wait TLB invalidation to complete
myDSB ,a1,,y ; Wait for TLB invalidation to complete
myISB ,a1,,y ; Ensure that the effects are visible
Pull "pc"
......
......@@ -201,18 +201,50 @@ op_UnaryMinus * 67 ; unary minus
MACRO
$label ePush $reglist
LCLS temps
LCLL onereg
temps SETS "$reglist"
onereg SETL {TRUE}
WHILE onereg :LAND: :LEN: temps > 0
[ temps :LEFT: 1 = "," :LOR: temps :LEFT: 1 = "-"
onereg SETL {FALSE}
]
temps SETS temps :RIGHT: (:LEN: temps - 1)
WEND
[ onereg
$label STR $reglist, [R11, #-4]!
|
$label STMFD R11!, {$reglist}
]
CMP R11, R10
BLE StackOFloErr
MEND
MACRO
$label ePull $reglist, $writeback, $cc
LCLS temps
LCLL onereg
temps SETS "$reglist"
onereg SETL {TRUE}
WHILE onereg :LAND: :LEN: temps > 0
[ temps :LEFT: 1 = "," :LOR: temps :LEFT: 1 = "-"
onereg SETL {FALSE}
]
temps SETS temps :RIGHT: (:LEN: temps - 1)
WEND
[ onereg
[ "$writeback" = ""
LDR$cc $reglist, [R11], #4
|
LDR$cc $reglist, [R11]
]
|
[ "$writeback" = ""
LDM$cc.FD R11!, {$reglist}
|
LDM$cc.FD R11, {$reglist}
]
]
MEND
;*************************************************************************
......
......@@ -336,12 +336,13 @@ MoveCAMatR0toR3 Entry "r0,r1,r6,r7"
ADR lr, PhysicalAddressNotFoundError
B %BT95
StoreDebugRegs
StoreDebugRegs ; Note: Corrupts R0,R1
Push "lr"
MOV lr, #CamMapCorruptDebugBlock
STMIA lr, {r0-lr}
LDR r0, [sp, #1*4] ; reload stacked r0 (error pointer)
STR r0, [lr, #15*4] ; store in stacked PC position
LDR lr, =ZeroPage+CamMapCorruptDebugBlock
STMIA lr, {r0-r12}
STR sp, [lr, #13*4]!
LDMIA sp, {r0,r1} ; reload stacked LR & return R0 (error pointer)
STMIB lr, {r0,r1} ; LR -> LR, error -> PC
Pull "pc"
NoL2ForPageBeingRemovedError
......
......@@ -1074,54 +1074,56 @@ HAL_InvalidateCache_ARMvF
; The only register we can safely change is ip, but we can switch into FIQ mode with interrupts disabled and use the banked registers there
MRS ip, CPSR
MSR CPSR_c, #F32_bit+I32_bit+FIQ32_mode
MOV r8, #0
MCR p15, 0, r8, c7, c5, 0 ; invalidate instruction cache
MCR p15, 0, r8, c8, c7, 0 ; invalidate TLBs
MCR p15, 0, r8, c7, c5, 6 ; invalidate branch target predictor
myDSB ,r8,,y ; Wait for completion
myISB ,r8,,y
MOV r9, #0
MCR p15, 0, r9, c7, c5, 0 ; invalidate instruction cache
MCR p15, 0, r9, c8, c7, 0 ; invalidate TLBs
MCR p15, 0, r9, c7, c5, 6 ; invalidate branch target predictor
myDSB ,r9,,y ; Wait for completion
myISB ,r9,,y
; Check whether we're ARMv7 (and thus multi-level cache) or ARMv6 (and thus single-level cache)
MRC p15, 0, r9, c0, c0, 1
TST r9, #&80000000 ; EQ=ARMv6, NE=ARMv7
MCREQ ARM_config_cp,0,r8,ARMv4_cache_reg,C7 ; ARMv3-ARMv6 I+D cache flush
BEQ %FT10 ; Skip to the end
MRC p15, 1, r8, c0, c0, 1 ; Cache level ID register
BIC r8, r8, #&FF000000 ; Discard unification/coherency bits
MOV r9, #0 ; Current cache level
20
TST r8, #7 ; Get flags
BEQ %FT10 ; Cache clean complete
MCR p15, 2, r9, c0, c0, 0 ; Program cache size selection register
myISB ,r8,,y
MRC p15, 1, r10, c0, c0, 0 ; Get size info
AND r11, r10, #&7 ; log2(Line size)-2
BIC r10, r10, #&F0000007 ; Clear flags & line size
MOV r12, r10, LSL #19 ; Number of ways-1 in upper 10 bits
MOV r10, r10, LSR #13 ; Number of sets-1 in lower 15 bits
; Way number needs to be packed right up at the high end of the data word; shift it up
CLZ r14, r12
MOV r12, r12, LSL r14
; Set number needs to start at log2(Line size)+2
MOV r10, r10, LSL #4 ; Start at bit 4
MOV r10, r10, LSL r11 ; Start at log2(Line size)+2
; Now calculate the offset numbers we will use to increment sets & ways
BIC r12, r12, r12, LSL #1 ; Way increment
BIC r11, r10, r10, LSL #1 ; Set increment
; Now we can finally clean this cache!
ORR r14, r9, r10 ; Current way (0), set (max), and level
30
MRC p15, 0, r8, c0, c0, 1
TST r8, #&80000000 ; EQ=ARMv6, NE=ARMv7
MCREQ ARM_config_cp,0,r9,ARMv4_cache_reg,C7 ; ARMv3-ARMv6 I+D cache flush
BEQ %FT50 ; Skip to the end
; This is basically the same algorithm as the MaintainDataCache_WB_CR7_Lx macro, but tweaked to use less registers and to read from CP15 directly
TST r8, #&07000000
BEQ %FT50
MOV r11, #0 ; Current cache level
10 ; Loop1
ADD r10, r11, r11, LSR #1 ; Work out 3 x cachelevel
MOV r9, r8, LSR r10 ; bottom 3 bits are the Cache type for this level
AND r9, r9, #7 ; get those 3 bits alone
CMP r9, #2
BLT %FT40 ; no cache or only instruction cache at this level
MCR p15, 2, r11, c0, c0, 0 ; write CSSELR from r11
myISB ,r9
MRC p15, 1, r9, c0, c0, 0 ; read current CSSIDR to r9
AND r10, r9, #&7 ; extract the line length field
ADD r10, r10, #4 ; add 4 for the line length offset (log2 16 bytes)
LDR r8, =&3FF
AND r8, r8, r9, LSR #3 ; r8 is the max number on the way size (right aligned)
CLZ r13, r8 ; r13 is the bit position of the way size increment
LDR r12, =&7FFF
AND r12, r12, r9, LSR #13 ; r12 is the max number of the index size (right aligned)
20 ; Loop2
MOV r9, r12 ; r9 working copy of the max index size (right aligned)
30 ; Loop3
ORR r14, r11, r8, LSL r13 ; factor in the way number and cache number into r14
ORR r14, r14, r9, LSL r10 ; factor in the index number
MCR p15, 0, r14, c7, c6, 2 ; Invalidate
ADDS r14, r14, r12 ; Increment way
BCC %BT30 ; Overflow will occur once ways are enumerated
TST r14, r10 ; Are set bits all zero?
SUBNE r14, r14, r11 ; No, so decrement set and loop around again
BNE %BT30
; This cache is now clean. Move on to the next level.
ADD r9, r9, #2
MOVS r8, r8, LSR #3
BNE %BT20
10
SUBS r9, r9, #1 ; decrement the index
BGE %BT30
SUBS r8, r8, #1 ; decrement the way number
BGE %BT20
MRC p15, 0, r8, c0, c0, 1
40 ; Skip
ADD r11, r11, #2
AND r14, r8, #&07000000
CMP r14, r11, LSL #23
BGT %BT10
50 ; Finished
; Wait for clean to complete
MOV r8, #0
myDSB ,r8,,y
......@@ -1870,7 +1872,8 @@ ClearPhysRAM ROUT
20 TEQ r0, r1 ; *this* is the speed critical bit - executed
TEQNE r0, r5 ; 32768 times per outer loop
STMNEIA r0!, {r2,r8-r14}
STMNEIA r0!, {r2,r8-r10}
STMNEIA r0!, {r2,r8-r10}
BNE %BT20
TEQ r0, r1
......
......@@ -304,7 +304,8 @@ inspect_IRQ_stack
iis_end ; store the registers in the info block
LDR R12, =ZeroPage+HeapSavedReg_R0
STMIA R12, {R0-R4, stack}
STMIA R12, {R0-R4}
STR stack, [R12, #5*4]
first_heap_address_to_trap ; because register saveblock now set.
LDR R12, [R12, #HeapReturnedReg_PSR-HeapSavedReg_R0]
......
......@@ -308,7 +308,7 @@ SBRKPT ROUT
]
STR r14, [r10, #15*4] ; PC of the SWI put in.
BNE %FT01 ; NE if not in user mode
STMIA r10!, {r0}
STR r0, [r10], #4
MOV r0, r10
LDMFD sp, {r10-r12}
......@@ -331,19 +331,22 @@ SBRKPT ROUT
BEQ %FT02 ; [yes]
; Non-user, non-supervisor - must be IRQ, ABT, UND or SYS (no SWIs from FIQ)
STMIA r10!, {r0}
STR r0, [r10], #4
MOV r0, r10
BIC r14, r12, #T32_bit ; don't go into Thumb mode
LDMFD sp, {r10-r12} ; Not banked
MSR CPSR_c, R14 ; get at registers r13 and r14
STMIA r0, {r1-r14}
STMIA r0, {r1-r12}
STR sp, [r0, #12*4]
STR r14, [r0, #13*4]
WritePSRc SVC_mode, r12
B %BT10
; Supervisor mode case
02 MOV r14, r12 ; supervisor mode. R14 in buffer dead
LDMFD sp!, {r10-r12}
STMIA r14, {r0-r13}
STMIA r14, {r0-r12}
STR r13, [r14, #13*4]
LDR r12, =&DEADDEAD
STR r12, [r14, #14*4] ; mark R14 as dead
B %BT10
......@@ -681,10 +684,13 @@ DumpyTheRegisters ROUT
ORR R2, R1, #I32_bit :OR: F32_bit
BIC R2, R2, #T32_bit
MSR CPSR_c, R2 ; change into original mode
STMIA R0, {R8-R14} ; save the banked registers
STMIA R0, {R8-R12} ; save the banked registers
AND R2, R1, #&0F
STR SP, [R0, #5*4]
EORS R2, R2, #FIQ_mode ; Was we in FIQ ? Zero if so
STR R14, [R0, #6*4]
[ HAL
BNE UNDEF2
MSR CPSR_c, #I32_bit+F32_bit+SVC32_mode ; into SVC mode so we have a stack
......@@ -923,7 +929,8 @@ Branch0_FromTrampoline
LDR R1, =ZeroPage
LDR R1, [R1, #ExceptionDump]
STMIA R1, {R0-R13}
STMIA R1, {R0-R12}
STR R13, [R1, #13*4]
LDR R0, [R14, #0]
STR R0, [R1, #1*4]
LDR R0, [R14, #4]
......
......@@ -382,7 +382,8 @@ ReadVduVarForSam
MOV R0, sp
MOV R1, sp
SWI XOS_ReadVduVariables
Pull "R0, R14, PC"
LDR R0, [sp], #8
LDR pc, [sp], #4
;*****************************************************************************
; R0 -> envstring, R1 -> 5 byte time
......
......@@ -1256,7 +1256,8 @@ IRQ ROUT
BL CallVector
[ HAL
Pull "r10, lr, pc" ; new-style CDV - pull return address
Pull "r10, lr"
Pull "pc" ; new-style CDV - pull return address
|
Pull "r10, pc" ; return: someone will always claim it.
]
......
......@@ -687,15 +687,13 @@ kbdwait
SUBS r6, r6, #1 ; else wait a maximum of 5 seconds.
BNE kbdwait
kbddone
DebugTX "Keyboard scan complete"
MSR CPSR_c, #I32_bit+SVC32_mode
DebugTX "FIQ enabled"
CallHAL HAL_KbdScanFinish
LDR r1, =ZeroPage+InitIRQWs
MOV r0, #0
STRB r0, [r1, #KbdScanActive]
MSR CPSR_c, #SVC32_mode
DebugTX "IRQ enabled"
DebugTX "Keyboard scan complete"
|
[ KeyWait <> 0
; Check for keyboard there every 1/5 sec. but give up after 2 secs.
......
......@@ -1235,7 +1235,7 @@ ReturnNULR0 ROUT
KeyREMOVECheckRS423 ROUT
Push R14
BL KeyREMOVE
Pull "R14, PC", CS ; pull stacked R14 if CS
ADDCS R13, R13, #4 ; pull stacked R14 if CS
Pull PC
; *****************************************************************************
......
......@@ -52,10 +52,12 @@ OsbyteKeyStatus * &CA ; only OS_Byte variable which isn't pure any more!
ASSERT "$cond"="" :LOR: "$cond"="VS"
[ "$cond"=""
Pull "R0,R3,R14,PC", VC
LDRVC R0,[R13]
]
ADDVS R13, R13, #4 ; junk stacked R0
Pull "R3,R14,PC", VS
ADD$cond R13,R13,#4
LDR$cond R3,[R13],#8 ; pull r3, junk r14
LDR$cond PC,[R13],#4
MEND
; Main OSbyte entry point
......@@ -80,13 +82,17 @@ OsByte
BLNE TranslateError
]
SWINE XOS_GenerateError ; set V if not claimed
Pull "R1-R4, R14, PC"
Pull "R1-R4"
ADD SP,SP,#4
Pull "PC"
BadCommandError MakeErrorBlock BadCommand
GoMyOsbyte
CLRPSR V_bit, R3
Pull "R0,R3, R14,PC" ; pull the world AND the PC to return
Pull "R0,R3" ; pull the world AND the PC to return
ADD SP,SP,#4
Pull "PC"
; *****************************************************************************
......
......@@ -24,10 +24,11 @@ maxword * &16 ; highest known osword
ASSERT "$cond"="" :LOR: "$cond"="VS"
[ "$cond"=""
Pull "R0-R4,R11,WsPtr,link,PC", VC
LDRVC R0,[R13]
]
ADDVS R13, R13, #4 ; junk stacked R0
Pull "R1-R4,R11,WsPtr,link,PC", VS
LDM$cond.IB R13,{R1-R4,R11,WsPtr}
ADD$cond R13,R13,#8*4 ; R0-R4,R11,WsPtr,R14
LDR$cond PC,[R13],#4
MEND
......@@ -50,7 +51,9 @@ OsWord
GoMyOsword
CLRPSR V_bit, R4
Pull "R0-R4, R11, R12, R14, PC"
Pull "R0-R4, R11, R12"
ADD R13, R13, #4
Pull PC
; *****************************************************************************
......@@ -119,7 +122,9 @@ OsWord00 ROUT
MOV R2, R1 ; put line length into R2
Pull "R0,R1,R3" ; don't overwrite R2
Pull "R3, R4, R11, R12, R14, PC"
Pull "R3, R4, R11, R12"
ADD R13, R13, #4
Pull PC
; *****************************************************************************
......
......@@ -72,7 +72,7 @@ PMFWrch ROUT
]
15
BVS %FT45 ; error from VDU
LDMFD R13, {R0} ; reload R0 with character
LDR R0,[R13] ; reload R0 with character
BYTEWS WsPtr ; reload workspace pointer
LDRB R1, WrchDest ; and wrch destinations
BCS PrintVdu ; VDU says "Print it"
......@@ -120,7 +120,7 @@ PrintVdu
BL MOSDoPrintWS ; else print it (R12 -> ByteWS)
BVS %BT45 ; error in printing
LDMFD R13, {R0} ; reload R0 with character
LDR R0, [R13] ; reload R0 with character
LDRB R1, WrchDest ; and reload wrchdest
B %BT40
......@@ -135,7 +135,7 @@ RS423Vdu
BVS %FT70 ; if can't open serial output stream, report error
; and don't put anything in buffer
STRB r0, SerialOutHandle
LDMFD sp, {r0} ; get char back
LDR r0, [sp] ; get char back
60
PHPSEI
Push "r14" ; save IRQ indication
......
......@@ -153,8 +153,9 @@ Util_ChocService
STRB r0, [lr, #OsbyteVars + :INDEX: SerialOutHandle]
20
SWI XOS_Find ; close file, ignore errors (if we get an error it's closed anyway)
LDR r0, [sp], #8 ; restore r0, junk r1
MOV r1, #Service_Serviced ; indicate we closed it
Pull "r0,lr,pc" ; restore r0, junk r1, and exit
LDR pc, [sp], #4 ; exit
Util_Die ROUT
......@@ -813,8 +814,8 @@ KeyHelpCommon ; also used by *Configure
MOVVC r1, r0
MOVVC r0, r2
SWIVC XOS_PrettyPrint
Pull "r1,lr,PC", VS ; if error, pull R1, junk stacked R0 and exit
Pull "r1,r3" ; restore r1 and get buffer pointer
Pull "pc", VS ; if error, exit
MOV r0, #0
ADRL R2, SysCommsModule
BL OneModuleK
......@@ -879,11 +880,11 @@ OneModuleK ROUT
CMP r0, #0
BEQ OneModuleK_PrintTitle ; Don't trust MessageTrans to preserve Z
SWI XMessageTrans_Dictionary
STMDB sp!, {r1}
Push "r1"
MOVVC r1, r0
MOVVC r0, r4
SWIVC XOS_PrettyPrint
LDMIA sp!, {r1}
Pull "r1"
B %FT77
OneModuleK_PrintTitle
LDR r0, [stack]
......
......@@ -86,7 +86,7 @@ BangCamUpdate ROUT
ADD r6, r6, r4, LSR #12 ; put back the ones which were too many
ADD r0, r0, r6, LSL #12 ; move on address by the number of pages left
LDMFD r13, {r6} ; reload old logical address
LDR r6, [r13] ; reload old logical address
; now we have r6 = old logical address, r2 = physical page number, r0 = physical address
......@@ -544,7 +544,9 @@ DAbPreVeneer ROUT
ORR r3, r3, r1 ; and put in user's
MSR CPSR_c, r3 ; switch to user's mode
STMIA r2, {r8-r14} ; save the banked registers
STMIA r2, {r8-r12} ; save the banked registers
STR r13, [r2,#5*4]
STR r14, [r2,#6*4]
MRS r5, SPSR ; get the SPSR for the aborter's mode
STR r5, [r2, #8*4] ; and store away in the spare slot on the end
......@@ -956,7 +958,9 @@ DAbPreVeneer ROUT
ORR r6, r6, #I32_bit ; use aborter's flags and mode but set I
BIC r6, r6, #T32_bit ; and don't set Thumb
MSR CPSR_c, r6 ; switch to aborter's mode
LDMIA r2, {r8-r14} ; reload banked registers
LDMIA r2, {r8-r12} ; reload banked registers
LDR r13, [r2, #5*4]
LDR r14, [r2, #6*4]
MSR CPSR_c, r1 ; switch back to ABT32
80
......