1. 04 Jul, 2015 2 commits
    • Jeffrey Lee's avatar
      Enable high processor vectors/zero page relocation. OS_DynamicArea 20 fixes. · f5644f74
      Jeffrey Lee authored
      Detail:
        Makefile, hdr/Options - By default enable high processor vectors/zero page relocation for compatible machines, but also allow the components file to override the setting if required
        s/ChangeDyn - Fix OS_DynamicArea 20 to check the correct range for doubly mapped areas, and to correctly localise its error message
      Admin:
        Tested on Iyonix
      
      
      Version 5.35, 4.79.2.268. Tagged as 'Kernel-5_35-4_79_2_268'
      f5644f74
    • Robert Sprowson's avatar
      Add extra OS_DynamicArea subreason · c8f15bd6
      Robert Sprowson authored
      Subreason 20 takes a logical address and tells you which area it lies in, including system areas (ie. those returned by OS_Memory 16.
      This allows areas to change type in future without the caller needing to care where the kernel put it.
      
      Version 5.35, 4.79.2.267. Tagged as 'Kernel-5_35-4_79_2_267'
      c8f15bd6
  2. 20 Jan, 2015 1 commit
    • Jeffrey Lee's avatar
      Perform extra TLB maintenance on ARMv6+. Other cache/TLB maintenance tweaks. · aca7f939
      Jeffrey Lee authored
      Detail:
        s/ARMops - Implement Cache_RangeThreshold for PL310 (helps AMBControl to decide what type of TLB maintenance is best). Fix MMU_ChangingEntry_PL310 doing more work than is necessary; was attempting to flush all ways for a given address tag, when really it should have only been flushing all the lines within a page and letting the cache worry about the tags/indices they correspond to.
        s/ChangeDyn, s/VMSAv6, s/AMBControl/memmap - Do extra TLB maintenance following writes to the page tables, as mandated by the ARMv6+ memory order model. Fixes frequent crashes on Cortex-A9 when running with lazy task swapping disabled (and presumably fixes other crashes too)
        s/MemInfo - Fix OS_Memory cache/uncache so that it does cache/TLB maintenance on a per-page basis instead of a global basis. Vastly improves performance when you have a large cache, but may need tweaking again in future to do a global op if large numbers of pages are being modified.
      Admin:
        Tested on Pandaboard
      
      
      Version 5.35, 4.79.2.255. Tagged as 'Kernel-5_35-4_79_2_255'
      aca7f939
  3. 20 Apr, 2014 1 commit
    • Jeffrey Lee's avatar
      Add OS_Memory 24 implementation. Change OS_ValidateAddress to use it. Fix... · 03d3b37a
      Jeffrey Lee authored
      Add OS_Memory 24 implementation. Change OS_ValidateAddress to use it. Fix kernel leaving the physical access MB in a messy state. Try and protect against infinite abort loops caused by bad environment handlers.
      
      Detail:
        s/MemInfo - Added an implementation of ROL's OS_Memory 24 call. Unlike the old OS_ValidateAddress call, this call should successfully report the presence of all memory areas known to the kernel. It should also correctly indicate which parts of a sparse DA are mapped in, unlike the old OS_ValidateAddress implementation.
        s/ChangeDyn - Update dynamic area handling to construct a lookup table for mapping logical addresses to dynamic areas; this is used by OS_Memory 24 to quickly locate which DA(s) hit a given region
        s/AMBControl/main - Make sure lazy task swapping is marked as disabled when AMB_LazyMapIn is {FALSE} - required so that OS_Memory 24 will give application space the correct flags
        s/ArthurSWIs - Switch OS_ValidateAddress over to using OS_Memory 24, as per ROL. For compatibility, Service_ValidateAddress is still issued for any areas which the kernel doesn't recognise (currently, OS_Memory 24 doesn't issue any service calls itself)
        s/Convrsions - ADR -> ADRL to keep things happy
        s/HAL - Fix L2PT page allocation and RAM clear to release the physical access region once they're done with it
        s/Kernel - Make the error dispatcher validate the error handler code ptr & error buffer using OS_Memory 24 before attempting to use them. If they look bad, reset to default. Should prevent getting stuck in an infinite abort loop in some situations (e.g. as was the case with ticket 279). The system might not fully recover, but it's better than a hard crash.
        s/Middle - Rework data/prefetch/etc. abort handlers so that DumpyTheRegisters can validate the exception dump area via OS_Memory 24 before anything gets written to it. Should also help to prevent some infinite abort loops. Strip 26bit/pre-HAL code to make things a bit more readable.
        hdr/KernelWS - Update comment
      Admin:
        Tested on BB-xM, Raspberry Pi
      
      
      Version 5.35, 4.79.2.222. Tagged as 'Kernel-5_35-4_79_2_222'
      03d3b37a
  4. 17 Dec, 2013 1 commit
    • Jeffrey Lee's avatar
      Strip out some old build switches · 9d96c0ab
      Jeffrey Lee authored
      Detail:
        hdr/Options, s/ArthurSWIs, s/ChangeDyn, s/PMF/KbdDrA1, s/PMF/key, s/vdu/vdugrafa, s/vdu/vdugrafd, s/vdu/vdugrafhal, s/vdu/vdugrafv, s/vdu/vdumodes, s/vdu/vduwrch:
        - Strip out DoingVdu build switch (did nothing)
        - Strip out Japanese16BitSound switch (did nothing)
        - Strip out MakeModeSelectorsForModeNUmbers switch (altered the mode list structures, but there wasn't any code to do anything with the new data)
        - Strip out remaining uses of UseGraphicsV switch (now hardwired to {TRUE})
        - Strip out ShadowROM switch (altered FixedAreasTable to show the shadow mapping, but code to create the mapping is missing)
        - Strip out PollMouse switch (old Archimedes-era debug/development option)
      Admin:
        Tested on BB-xM
        Builds to same binary as previous version
      
      
      Version 5.35, 4.79.2.204. Tagged as 'Kernel-5_35-4_79_2_204'
      9d96c0ab
  5. 28 Mar, 2013 1 commit
    • Jeffrey Lee's avatar
      Teach the kernel about different memory attributes · c40b2dba
      Jeffrey Lee authored
      Detail:
        Briefly, this set of changes:
        * Adjusts PhysRamTable so that it retains the flags passed in by the HAL from OS_AddRAM (by storing them in the lower 12 bits of the size field)
        * Sorts the non-VRAM entries of PhysRamTable by speed and DMA capability, to ensure optimal memory allocation during OS startup.
        * Adjust the initial memory allocation logic to allow the cursor/sound chunk and HAL noncacheable workspace to come from DMA capable memory
        * Extends OS_Memory 12 to accept a 'must be DMA capable' flag in bit 8 of R0. This is the same as available in ROL's OS.
        * Extends OS_DynamicArea 0 to allow the creation of dynamic areas that automatically allocate from DMA capable memory. In ROL's OS this was done by setting bit 12 of R4, but we're using bits 12-14 for specifying the cache policy, so instead bit 15 is used.
        * Fixes OS_ReadSysInfo 6 to return the correct DevicesEnd value now that the IRQ/device limit is computed at runtime
        File changes:
        * hdr/OSEntries - Add definitions of the various flags passed to OS_AddRAM by the HAL. Add a new flag, NoDMA, for memory which can't be used for DMA.
        * hdr/KernelWS - Tidy PhysRamTable definition a bit by removing all the DRAM bank definitions except the first - this makes it easier to search for code which is interacting with the table. Remove VRAMFlags, it's redundant now that the flags are kept in the table. Add DMA allocation info to InitWs.
        * s/AMBControl/memmap - Updated to mask out the flags from PhysRamTable when reading RAM block sizes.
        * s/ARM600 - Strip out a lot of IOMD specific pre-HAL code.
        * s/ChangeDyn - Updated to cope with the flags stored in PhysRamTable. Implement support for DMA-capable dynamic areas. Rewrite InitDynamicAreas to insert pages into the free pool in the right order so that the fastest memory will be taken from it first.
        * s/GetAll, s/Middle - Fix OS_ReadSysInfo 6 to return the correct HAL-specific DevicesEnd value
        * s/HAL - Significant rework of initial RAM allocation code to allow the kernel workspace to come from the fastest DMA incapable RAM, while also allowing allocation of DMA capable memory for HAL NCNB workspace & kernel cursor/sound chunks. ClearPhysRAM rewritten as part of this.
        * s/MemInfo - Updated to cope with the flags stored in PhysRamTable. Add support for the new OS_Memory 12 flag. Update OS_Memory 7 to not assume PhysRamTable entries are sorted in address order, and rip out the old pre-HAL IOMD implementation.
        * s/NewReset - Remove GetPagesFromFreePool option, assume TRUE (as this has been the case for the past 10+ years). Revise a few comments and strip dead code. Update to cope with PhysRamTable flags.
        * s/VMSAv6 - Remove a couple of unused definitions
        * s/vdu/vdudriver - Update to cope with PhysRamTable flags
      Admin:
        Tested in Kinetic RiscPC ROM softload, Iyonix softload, & OMAP3
      
      
      Version 5.35, 4.79.2.186. Tagged as 'Kernel-5_35-4_79_2_186'
      c40b2dba
  6. 28 Oct, 2012 1 commit
    • Robert Sprowson's avatar
      Review of Internation switch · d58ce177
      Robert Sprowson authored
      Variously the call to TranslateError was either followed (outside the switch) by an unnecessary SETV, or missing SETV for the non international case.
      Added DMA controller HAL device for IOMD.
      
      Version 5.35, 4.79.2.174. Tagged as 'Kernel-5_35-4_79_2_174'
      d58ce177
  7. 15 Apr, 2012 1 commit
    • Jeffrey Lee's avatar
      OS_ChangeDynamicArea performance optimisations · 5e11e665
      Jeffrey Lee authored
      Detail:
        s/ChangeDyn:
          - Apply various optimisations to OS_ChangeDynamicArea to reduce the execution time when performing large grows/shrinks.
          - Optimisations can be toggled on/off with FastCDA_* flags for debugging.
          - On a 1GHz 512MB BB-xM, the initial *FreePool call now takes 0.15s instead of 13.46s. On a 512MB Iyonix the time has dropped from 1.18s to 0.23s.
          - Growing screen memory (on BB-xM) has also seen significant gains - between 2x and 4x speedup, depending on what state the source pages are in.
          - Added/updated documentation for a few functions and made more use of ROUTs for safety
        s/ARM600, s/VMSAv6:
          - Update BangCamUpdate, etc. to add support for the PageFlags_Unsafe flag that OS_ChangeDynamicArea uses to bypass cache/TLB maintenance in some situations
          - Avoid BangCamUpdate calling BangL2PT to map out the page if the page isn't mapped in (avoids unnecessary cache/TLB flush)
        s/ArthurSWIs:
          - Add extra ASSERT for safety
        s/AMBcontrol/memory
          - Fix incorrect assumption that the usable size of a heap block is always 8 less than the value stored in the header. Even with the old 8 byte aligned allocations the usable size will always be 4 bytes less than the value in the header. This code would have resulted in some slight memory wasteage, as AMBcontrol will have always tried growing the block four bytes bigger than needed.
      Admin:
        Tested on Iyonix & BB-xM
      
      
      Version 5.35, 4.79.2.146. Tagged as 'Kernel-5_35-4_79_2_146'
      5e11e665
  8. 24 Sep, 2011 1 commit
    • Jeffrey Lee's avatar
      Fix objasm 4 warnings · 6d052230
      Jeffrey Lee authored
      Detail:
        s/Arthur3, s/ChangeDyn, s/HAL, s/HeapMan, s/Middle, s/MoreSWIs, s/NewIRQs, s/Utility, s/VMSAv6, s/PMF/key, s/PMF/osbyte, s/PMF/osword, s/vdu/vdudecl, s/vdu/vdudriver, s/vdu/vduplot, s/vdu/vduwrch - Tweaked lots of LDM/STM instructions in order to get rid of the depracation/performance warnings
      Admin:
        Tested on rev A2 BB-xM
      
      
      Version 5.35, 4.79.2.98.2.53. Tagged as 'Kernel-5_35-4_79_2_98_2_53'
      6d052230
  9. 08 Aug, 2011 1 commit
    • Jeffrey Lee's avatar
      Add zero page relocation support · 2247d8e9
      Jeffrey Lee authored
      Detail:
        A whole mass of changes to add high processor vectors + zero page relocation support to the Cortex branch of the kernel
        At the moment the code can only cope with two ZeroPage locations, &0 and &FFFF0000. But with a bit more tweaking those restrictions can probably be lifted, allowing ZeroPage to be hidden at almost any address (assuming it's fixed at compile time). If I've done my job right, these restrictions should all be enforced by asserts.
        There's a new option, HiProcVecs, in hdr/Options to control whether high processor vectors are used. When enabling it and building a ROM, remember:
        * FPEmulator needs to be built with the FPEAnchor=High option specified in the components file (not FPEAnchorType=High as my FPEmulator commit comments suggested)
        * ShareFS needs unplugging/removing since it can't cope with it yet
        * Iyonix users will need to use the latest ROOL boot sequence, to ensure the softloaded modules are compatible (OMAP, etc. don't really softload much so they're OK with older sequences)
        * However VProtect also needs patching to fix a nasty bug there - http://www.riscosopen.org/tracker/tickets/294
        The only other notable thing I can think of is that the ProcessTransfer code in s/ARM600 & s/VMSAv6 is disabled if high processor vectors are in use (it's fairly safe to say that code is obsolete in HAL builds anyway?)
        Fun challenge for my successor: Try setting ZeroPage to &FFFF00FF (or similar) so its value can be loaded with MVN instead of LDR. Then use positive/negative address offsets to access the contents.
        File changes:
        - hdr/ARMops - Modified ARMop macro to take the ZeroPage pointer as a parameter instead of 'zero'
        - hdr/Copro15ops - Corrected $quick handling in myISB macro
        - hdr/Options - Added ideal setting for us to use for HiProcVecs
        - s/AMBControl/allocate, s/AMBControl/growp, s/AMBControl/mapslot, s/AMBControl/memmap, s/AMBControl/service, s/AMBControl/shrinkp, s/Arthur2, s/Arthur3, s/ArthurSWIs, s/ChangeDyn, s/ExtraSWIs, s/HAL, s/HeapMan, s/Kernel, s/MemInfo, s/Middle, s/ModHand, s/MoreSWIs, s/MsgCode, s/NewIRQs, s/NewReset, s/Oscli, s/PMF/buffer, s/PMF/IIC, s/PMF/i2cutils, s/PMF/key, s/PMF/mouse, s/PMF/osbyte, s/PMF/oseven, s/PMF/osinit, s/PMF/osword, s/PMF/oswrch, s/SWINaming, s/Super1, s/SysComms, s/TickEvents, s/Utility, s/vdu/vdu23, s/vdu/vdudriver, s/vdu/vdugrafl, s/vdu/vdugrafv, s/vdu/vdupalxx, s/vdu/vdupointer, s/vdu/vduswis, s/vdu/vduwrch - Lots of updates to deal with zero page relocation
        - s/ARM600 - UseProcessTransfer option. Zero page relocation support. Deleted pre-HAL ClearPhysRAM code to tidy the file up a bit.
        - s/ARMops - Zero page relocation support. Set CPUFlag_HiProcVecs when high vectors are in use.
        - s/KbdResPC - Disable compilation of dead code
        - s/VMSAv6 - UseProcessTransfer option. Zero page relocation support.
      Admin:
        Tested with OMAP & Iyonix ROM softloads, both with high & low zero page.
        High zero page hasn't had extensive testing, but boot sequence + ROM apps seem to work.
      
      
      Version 5.35, 4.79.2.98.2.48. Tagged as 'Kernel-5_35-4_79_2_98_2_48'
      2247d8e9
  10. 19 Feb, 2011 1 commit
    • Jeffrey Lee's avatar
      Update OS_IICOp to support multiple IIC buses · 327d3980
      Jeffrey Lee authored
      Detail:
        OS_IICOp (and in turn, RISCOS_IICOpV) now treat the top byte of R1 as containing the IIC bus number, allowing multiple buses to be used.
        hdr/KernelWS - Changed workspace a bit so that the kernel can support up to IICBus_Count buses (currently 3), each with its own IICBus_* block.
        s/HAL - Update Reset_IRQ_Handler to cope with interrupts from all IIC buses instead of just the first. Fix/update RISCOS_IICOpV description.
        s/NewIRQs - Update InitialiseIRQ1Vtable to set up interrupt handlers for all IRQ-supporting IIC buses
        s/NewReset - Get rid of the IICAbort call that was just before IICInit. IICInit now calls IICAbort itself.
        s/PMF/IIC - Bulk of the changes. Code now uses the IICBus_ structures instead of the IICStatus and IICType variables. Re-entrancy code has been updated to take into account the possiblity of multiple buses; when OS_IICOp calls are nested, the IIC transfers will be added to bus-specific queues instead of all going in the same queue. However only one queue will be processed at a time.
        s/ChangeDyn - Workspace shuffling means a couple of MOV's needed to be swapped with LDR's when getting immediate constants
      Admin:
        Tested with OMAP & IOMD ROM builds.
        Both high & low-level bus types seem to work OK, along with re-entrancy, both on the same bus and on a different bus.
      
      
      Version 5.35, 4.79.2.98.2.33. Tagged as 'Kernel-5_35-4_79_2_98_2_33'
      327d3980
  11. 03 Jul, 2010 1 commit
    • Jeffrey Lee's avatar
      Fix more issues caused by aborting MVA cache/TLB ops on ARMv7 · 9e6b9350
      Jeffrey Lee authored
      Detail:
        s/ARMops - Fixed an instance of 'invalidate branch predictor entry' that should have been 'invalidate all branch predictors'
        s/ChangeDyn - Avoid cleaning the Nowhere page when reallocating memory, to avoid incurring the performance hit of the abort handler, and to avoid AMBControl screwing things up by mapping in pages that we're trying to modify
        s/VMSAv6 - Move MVA cache/TLB abort handler to before ChocolateAMB code, to ensure AMBControl doesn't try mapping in pages for harmless cache/TLB op aborts. Also tweaked code to be a little bit faster.
      Admin:
        Tested on rev C2 beagleboard. No more lockups when moving screen memory around, for now at least.
      
      
      Version 5.35, 4.79.2.98.2.30. Tagged as 'Kernel-5_35-4_79_2_98_2_30'
      9e6b9350
  12. 22 Oct, 2009 2 commits
    • Jeffrey Lee's avatar
      Fix error handling for sparse dynamic area resize operations (for main HAL branch) · d0ddc243
      Jeffrey Lee authored
      Detail:
        s/ChangeDyn - Swap CMP with TEQ to avoid accidental clobbering of V flag before its state is checked on return from a SWI. Errors encounterd during sparse dynamic area resize operations (OS_DynamicArea 9 & 10) should now be reported properly.
      Admin:
        Not tested, but the same fix has been proven to work on the Cortex branch.
      
      
      Version 5.35, 4.79.2.104. Tagged as 'Kernel-5_35-4_79_2_104'
      d0ddc243
    • Jeffrey Lee's avatar
      Fix error handling for sparse dynamic area resize operations, increase Cortex... · 04f4e5cd
      Jeffrey Lee authored
      Fix error handling for sparse dynamic area resize operations, increase Cortex kernel version number to 5.15
      
      Detail:
        s/ChangeDyn - Swap CMP with TEQ to avoid accidental clobbering of V flag before its state is checked on return from a SWI. Errors encountered during sparse dynamic area resize operations (OS_DynamicArea 9 & 10) should now be reported properly.
        Version - Update kernel version/date to 5.15, to match current HAL version. This change is to allow modules to properly detect whether the kernel has the sparse dynamic area fix - it does not (yet) mean that the Cortex kernel contains all the features of the current development HAL kernel!
      Admin:
        Tested on rev C2 beagleboard
      
      
      Version 5.35, 4.79.2.98.2.14. Tagged as 'Kernel-5_35-4_79_2_98_2_14'
      04f4e5cd
  13. 06 Mar, 2009 1 commit
    • Jeffrey Lee's avatar
      Add VMSAv6 MMU support, fixes to allow booting on beagleboard · 3d1317e7
      Jeffrey Lee authored
      Detail:
        s/ARM600 - fix to SyncCodeAreasRange to correctly read cache line length for WB_CR7_Lx caches
        s/ARMops - Cortex cache handling fixes. Enable L2 cache for Cortex.
        s/ChangeDyn - VMSAv6 support in AllocateBackingLevel2
        s/HAL - Improve RISCOS_InitARM to set/clear correct CP15 flags for ARMv6/v7. VMSAv6 support in code to generate initial page tables.
        s/NewReset - Extra DebugTX calls during OS startup. Disable pre-HAL Processor_Type for HAL builds.
        s/VMSAv6 - Main VMSAv6 MMU code - stripped down version of s/ARM600 with support for basic VMSAv6 features.
        hdr/Options - Use VMSAv6 MMU code, not ARM600. Disable ARM6support since current VMSAv6 code will conflict with it.
      Admin:
        Tested basic OS functionality under qemu-omap3 and revision B6 beagleboard.
      
      
      Version 5.35, 4.79.2.98.2.3. Tagged as 'Kernel-5_35-4_79_2_98_2_3'
      3d1317e7
  14. 30 Nov, 2002 1 commit
    • Ben Avison's avatar
      Commit of kernel as featured in release 5.00. · 9664c93b
      Ben Avison authored
      Detail:
        Lots of changes since last version, at least the following:
        * Updated OS timestamp, removed alpha status
        * Negative INKEY OS version changed to &AA
        * GraphicsV is now alocated vector number &2A
        * ROM moved up to &FC000000
        * Max application slot increased to 512 Mbytes (for now)
        * Max size of RMA increased to 256 Mbytes
        * RMA is now first-created dynamic area (so it gets lowest address after
          top of application slot)
        * OS_Memory 10 reimplemeted
        * New OS_ReadSysInfo 6 values 18-22 added
        * OS_ReadSysInfo 8 gains flag bit to indicate soft power-off
        * Misc internal top-bit-set-address fixes
        * *ChangeDynamicArea can take sizes in megabytes or gigabytes
        * Magic word "&off" in R0 passed to OS_Reset powers down if possible
        * Added acceleration: block copy; CLS; text window scroll up; rectangle
          fill
        * Disabled LED flashing in page mode (liable to crash)
        * Masked sprite plot and VDU 5 text avoids reading the screen if possible
        * Framestore made USR mode accessible
        * Fix for VDU 5,127 bug - now relies on font definitions being in extreme
          quarters of memory, rather than bottom half
        * Allocated 64-bit OS_Convert... SWIs
        * IIC errors use allocated error numbers
        * Looks for Dallas RTC before Philips RTC because we're using a Philips
          NVRAM device with the same ID
        * Fix to bug that meant the oscillator in the Dallas RTC wasn't enabled
        * Default mouse type (USB) changed to allocated number
        * Ram disc max size increased to 128 Mbytes (Ursula merge) and made
          cacheable for StrongARMs (not XScale)
        * Branch through zero handler now works in USR mode, by use of a
          trampoline in the system stack to allow PC-relative register storage
        * Address exception handler changed to not use 0 as workspace
        * OS_Memory 13 extended to allow specification of cacheability and access
          privileges
        * Added OS_Memory 16 to return important memory addresses
        * RISCOS_MapInIO() takes cacheable flag in bit 3, access permissions in
          bits 10 and 11, doubly-mapped flag in bit 20, and access permissions
          specified flag in bit 21
        * Bug fix in last version for application abort handlers didn't quite
          work; register shuffle required
        * "Module is not 32-bit compatible" error now reports the module name
        * Default configured language changed from 10 to 11 (now Desktop again)
      
      Version 5.35, 4.79.2.51. Tagged as 'Kernel-5_35-4_79_2_51'
      9664c93b
  15. 07 Oct, 2002 1 commit
  16. 18 Jun, 2001 1 commit
    • Mike Stephens's avatar
      Reimplement enhancements to kernel Dynamic Area support from · 3f877936
      Mike Stephens authored
      Ursula. Quite a hairy code merge really, so let's hope it is
      worth it to someone. What you get (back after 2 or 3 years):
      - much more efficient for largish numbers of DAs (relevance
        to current build = approx 0)
      - fancy reason codes to support fast update of
        Switcher bar display (relevance = 0)
      - support for clamped maximum area sizes, to avoid address
        space exhaustion with big memory (relevance = 0)
      - better implementation of shrinkable DAs, performance
        wise (if lots of DAs, relevance = approx 0)
      - support for 'Sparse' DAs. Holey dynamic areas, Batman!
        (relevance, go on someone use the darned things)
      Moderately development tested on HAL/32bit ARM9 desktop.
      Note the Switcher should be compiled to use the new
      reason codes 6&7, for fabled desktop builds.
      
      Also, during this work, so I could see the wood for the
      trees, redid some source code clean up, removing pre-Medusa
      stuff (like I did about 3 years ago on Ursula, sigh). That's
      why loads of source files have changed. The new DA stuff
      is confined pretty much to hdr.KernelWS and s.ChangeDyn.
      
      Ta.
      
      Version 5.35, 4.79.2.38. Tagged as 'Kernel-5_35-4_79_2_38'
      3f877936
  17. 15 Jun, 2001 1 commit
    • Mike Stephens's avatar
      Merge in long command line support from Ursula kernel. · 8727ebaa
      Mike Stephens authored
      Look for LongCommandLine flag, command line size currently
      set at 1k.
      For HAL/32bit builds, the kernel buffer space is at high
      (top bit set) address, which may break some code using signed
      comparisons. So *beware* that there may be some latent
      bugs in old kernel code using these buffers, not yet found.
      One such bug, in s.Arthur2 found and fixed.
      Tested moderately on ARM9 desktop build.
      Lovely to reimplement things I did two and half years ago.
      
      Version 5.35, 4.79.2.37. Tagged as 'Kernel-5_35-4_79_2_37'
      8727ebaa
  18. 06 Jun, 2001 1 commit
    • Mike Stephens's avatar
      Further work on Lazy task swapping: · ae287104
      Mike Stephens authored
        hooks to give correct mapping info for OS_Memory 0
        same for OS_ReadMemMapEntries
        same for OS_FindMemMapEntries
        Lazy fixup routine no longer assumes an abort in current
        app space must be a truant page. However, work in this
        area not complete (no support yet for abort handler code
        in app space itself, eg. for C trampoline)
      Good to know this will be a big performance boost when
      our products use one monolithic application (sarcasm).
      Ta
      
      Version 5.35, 4.79.2.32. Tagged as 'Kernel-5_35-4_79_2_32'
      ae287104
  19. 22 May, 2001 1 commit
    • Mike Stephens's avatar
      Reimplement Lazy task swapping, an amusing idea from Ursula, would have done... · bdc4f843
      Mike Stephens authored
      Reimplement Lazy task swapping, an amusing idea from Ursula, would have done it sooner but couldn't be bothered (humour).
      
      Currently activates for all ARMs flagged as base-restored
      abort model. No handling of eg. StrongARM pre-revT bug, but
      then the kernel no longer runs on StrongARM (progress).
      Still some details to fix: all aborts in current app space
      assumed to be missing pages, but this must be fixed to
      handle abort code in app space, things like debuggers
      marking code read only.
      
      Plus, small fixes:
        OS_Memory 8 returns vaguely useful info for RAM,VRAM
        in HAL build (temporary partial implementation)
        Broken handling of old BBC commands with (fx,tv etc)
        with no spaces fixed (fudgeulike code from Ursula,
        now 32-bit).
      
      Version 5.35, 4.79.2.31. Tagged as 'Kernel-5_35-4_79_2_31'
      bdc4f843
  20. 01 May, 2001 1 commit
  21. 13 Feb, 2001 1 commit
  22. 25 Jan, 2001 1 commit
  23. 10 Nov, 2000 1 commit
  24. 20 Oct, 2000 2 commits
  25. 10 Oct, 2000 1 commit
  26. 09 Oct, 2000 1 commit
  27. 06 Oct, 2000 1 commit
  28. 05 Oct, 2000 1 commit
  29. 02 Oct, 2000 1 commit
  30. 15 Sep, 2000 1 commit
    • Kevin Bracey's avatar
      * Converted to building with ObjAsm (but still a single object file using ORG). · 49836a59
      Kevin Bracey authored
      * Added ARM_IMB and ARM_IMBRange SWIs as recommended by ARMv5.
      * Some early prototype HAL bits popped in - a lot of source restructuring still
        to come.
      * New debug target creates an AIF image with debug information, and translates
        this into an ASCII object file for the 16702B logic analyser.
      
      Version 5.35, 4.79.2.1. Tagged as 'Kernel-5_35-4_79_2_1'
      49836a59
  31. 09 May, 2000 1 commit
    • Stewart Brodie's avatar
      Fixed "SWI &6D656D not known" system collapse. · b41af248
      Stewart Brodie authored
        Fixed multiple internationalisation of error message.
      Detail:
        Somebody had decided to write a comment that R0-R2 needed to be
          unstacked before exiting the dynamic area remove routine, but
          then forgot to do so.  The crash is the same each time, as the
          address of MessageTrans error buffer it was trying to return
          is the value mistakenly loaded in R15.
        Kernel doesn't try to translate error messages multiple times.
          Not only does this give rise to errors about not being able
          to translate error messages, but causes MessageTrans to have to
          search repeatedly for non-existant tokens, slowing things down
          enormously.
      Admin:
        Tested in Ursula build.
        Not a complete fix - FileCore now leaks map & buffer dynamic areas
          whenever the RAM disc size is altered, but that needs to be fixed
          in FileCore (it needs to accept that OS_ChangeDynamicArea is not
          re-entrant and delete the DAs on a callback)
      
      Version 5.26. Tagged as 'Kernel-5_26'
      b41af248
  32. 04 Apr, 2000 1 commit
    • Kevin Bracey's avatar
      32-bit Kernel. · b4016e9c
      Kevin Bracey authored
      Details:
        The Kernel will now compile to produce a pure 32-bit system if No26bitCode is
        set to TRUE.
        If No26bitCode is FALSE, then the Kernel will be a standard 26-bit Kernel,
        although some internal changes have taken place to minimise compile
        switches between the two cases. See Docs.32bit for more technical info.
      
        The hardest part was the flood-fill...
      
      Other changes:
        Pointer shape changes now take place on the next VSync, rather than actually
        WAITING for the VSync. Turning the Hourglass on shouldn't slow your machine
        down by 5% now :)
      
        Lots of really crusty pre-IOMD code removed.
      
      Admin:
        Tested in 32 and 26-bit forms in a limited desktop build. Basically, this
        will need to see a lot of use to iron out difficulties. I'd like anyone who
        has a non-frozen project to at least attempt using this Kernel.
      
      Version 5.23. Tagged as 'Kernel-5_23'
      b4016e9c
  33. 19 Aug, 1999 1 commit
  34. 17 Aug, 1999 1 commit
  35. 30 Apr, 1999 1 commit
  36. 13 May, 1997 1 commit
  37. 07 May, 1997 1 commit