1. 30 Nov, 2002 1 commit
    • Ben Avison's avatar
      Commit of kernel as featured in release 5.00. · 9664c93b
      Ben Avison authored
        Lots of changes since last version, at least the following:
        * Updated OS timestamp, removed alpha status
        * Negative INKEY OS version changed to &AA
        * GraphicsV is now alocated vector number &2A
        * ROM moved up to &FC000000
        * Max application slot increased to 512 Mbytes (for now)
        * Max size of RMA increased to 256 Mbytes
        * RMA is now first-created dynamic area (so it gets lowest address after
          top of application slot)
        * OS_Memory 10 reimplemeted
        * New OS_ReadSysInfo 6 values 18-22 added
        * OS_ReadSysInfo 8 gains flag bit to indicate soft power-off
        * Misc internal top-bit-set-address fixes
        * *ChangeDynamicArea can take sizes in megabytes or gigabytes
        * Magic word "&off" in R0 passed to OS_Reset powers down if possible
        * Added acceleration: block copy; CLS; text window scroll up; rectangle
        * Disabled LED flashing in page mode (liable to crash)
        * Masked sprite plot and VDU 5 text avoids reading the screen if possible
        * Framestore made USR mode accessible
        * Fix for VDU 5,127 bug - now relies on font definitions being in extreme
          quarters of memory, rather than bottom half
        * Allocated 64-bit OS_Convert... SWIs
        * IIC errors use allocated error numbers
        * Looks for Dallas RTC before Philips RTC because we're using a Philips
          NVRAM device with the same ID
        * Fix to bug that meant the oscillator in the Dallas RTC wasn't enabled
        * Default mouse type (USB) changed to allocated number
        * Ram disc max size increased to 128 Mbytes (Ursula merge) and made
          cacheable for StrongARMs (not XScale)
        * Branch through zero handler now works in USR mode, by use of a
          trampoline in the system stack to allow PC-relative register storage
        * Address exception handler changed to not use 0 as workspace
        * OS_Memory 13 extended to allow specification of cacheability and access
        * Added OS_Memory 16 to return important memory addresses
        * RISCOS_MapInIO() takes cacheable flag in bit 3, access permissions in
          bits 10 and 11, doubly-mapped flag in bit 20, and access permissions
          specified flag in bit 21
        * Bug fix in last version for application abort handlers didn't quite
          work; register shuffle required
        * "Module is not 32-bit compatible" error now reports the module name
        * Default configured language changed from 10 to 11 (now Desktop again)
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_51'
  2. 28 Oct, 2002 1 commit
    • Ben Avison's avatar
      In the No26bitCode case (ie when abort handlers are entered in ABT32 mode), if... · 982426fe
      Ben Avison authored
      In the No26bitCode case (ie when abort handlers are entered in ABT32 mode), if lazy task swapping was enabled and a data abort occurred that was not a page translation fault, then the code in AMB_LazyFixUp to map in the whole application slot was being circumvented, leading to problems for abort handlers in application space because r14_abt was corrupted by any abort due to accessing the abort handler itself. The test of the FSR (to compensate for the FAR being unusable for external aborts) which prompted the circumvention has therefore been moved inside AMB_LazyFixup.
      Also now preserves the FSR and FAR across AMB_LazyFixUp, so they are now
      visible from application abort handlers if desired.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_50'
  3. 16 Oct, 2002 1 commit
    • Ben Avison's avatar
      Mostly device stuff. · 14a44ef3
      Ben Avison authored
        * Implemented OS_Hardware 2, 3 and 4 as described in Docs.HAL.NewAPI.
        * Added new OS->HAL and HAL->OS routines to register HAL devices with the
          OS during hard resets.
        * Updated Docs.HAL.NewAPI to correct inconsistencies, fill in missing
          definitions, and allow for interrupt sharing.
        * Now uses OS_LeaveOS to trigger callbacks after ROM module init.
        Untested. Requires new HAL.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_49'
  4. 07 Oct, 2002 1 commit
  5. 07 Feb, 2002 1 commit
    • Ben Avison's avatar
      IIC code is now re-entrant. Also a bugfix. · 4ecea6cc
      Ben Avison authored
        I pinched the IIC code from here to build MPEGDriver-0_32-1_33_2_2; now
        that I've added re-entrancy there (MPEGDriver-0_32-1_33_2_4), I'm folding
        the changes back in here, in case it's ever of use to someone else.
        Re-entrancy is achieved by restricting register use to r0-r3,r10,r11,CPSR
        so that re-entered code can complete any pending IIC operation by
        pulling those registers from the IRQ stack, before executing the new
        The bugfix is regarding a continued read transaction - previously, the
        final byte read of a read transaction was never acknowledged; it needs to
        be acknowledged if it is immediately followed by another read transaction
        without its own repeated Start condition.
        Tested as part of MPEGDriver, but not as part of a kernel build.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_47'
  6. 11 Jul, 2001 1 commit
    • David Cotton's avatar
      Change for Customer M build. · 16021e84
      David Cotton authored
          The Kernel now sets "ProtectStationID" on the basis of the Embedded_UI
      flag, rather than the STB flag, so you're able to set the bottom byte of your
      IP address in IPConfig.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_46'
  7. 04 Jul, 2001 2 commits
  8. 29 Jun, 2001 1 commit
  9. 27 Jun, 2001 1 commit
    • Mike Stephens's avatar
      StrongARM is back, and this time it's provisional! · f39e1298
      Mike Stephens authored
      IOMD HAL:
        enables fast clock for StrongARM on Medusa h/w
        ARMops for StrongARM implemented. Tested moderately on
        HAL/32-bit minimal desktop build for Risc PC. Could do
        with more testing later. eg. does reentrant cache
        cleaning support really work?
        Lazy task swapping is enabled for revT or later, wahey.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_42'
  10. 26 Jun, 2001 1 commit
    • Mike Stephens's avatar
      1) Bring IOMD HAL more up to date. Add support for new call HAL_CleanerSpace... · 63a6ffec
      Mike Stephens authored
      1) Bring IOMD HAL more up to date. Add support for new call HAL_CleanerSpace (preparation for StrongARM kernel support).
      2) In kernel, add HAL_CleanerSpace call (preparation for
      StrongARM and XScale core support). Fix bug found with
      ARMv3 support during test on Risc PC.
      3) Implement new API for kernel SWIs that have used top
      bits of addresses as flags. The new API has an extra
      flag that must be set, so kernel can distinguish and
      support both APIs. The reason for all this is that
      addresses are 32-bits now, people, keep up there. Briefly:
          bit 31 of r0 set for new API, r1 is full 32-bit address
          flags move from r1 bits 31-29 to r0 bits 30-28
          bit 31 of r1 set for new API, r0 is full 32-bit address
          flags move from bits 31,30 of r0 to bits 30,29 of r1
          bit 31 of r2 set for new API, r0 is full 32-bit address
          flag moves from bit 31 of r0 to bit 30 of r2
      Tested on Risc PC and briefly on Customer A 2
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_41'
  11. 22 Jun, 2001 1 commit
    • Mike Stephens's avatar
      fix bug in oscli gstrans handling (a problem provoked by long command lines... · 6be01a33
      Mike Stephens authored
      fix bug in oscli gstrans handling (a problem provoked by long command lines with top bit set buffer addresses and not fixed properly). Problem was mistaken rejection of gstrans'd parameters other than at beginning of buffer.
      Tested on simple desktop build for Risc PC
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_40'
  12. 21 Jun, 2001 1 commit
  13. 18 Jun, 2001 1 commit
    • Mike Stephens's avatar
      Reimplement enhancements to kernel Dynamic Area support from · 3f877936
      Mike Stephens authored
      Ursula. Quite a hairy code merge really, so let's hope it is
      worth it to someone. What you get (back after 2 or 3 years):
      - much more efficient for largish numbers of DAs (relevance
        to current build = approx 0)
      - fancy reason codes to support fast update of
        Switcher bar display (relevance = 0)
      - support for clamped maximum area sizes, to avoid address
        space exhaustion with big memory (relevance = 0)
      - better implementation of shrinkable DAs, performance
        wise (if lots of DAs, relevance = approx 0)
      - support for 'Sparse' DAs. Holey dynamic areas, Batman!
        (relevance, go on someone use the darned things)
      Moderately development tested on HAL/32bit ARM9 desktop.
      Note the Switcher should be compiled to use the new
      reason codes 6&7, for fabled desktop builds.
      Also, during this work, so I could see the wood for the
      trees, redid some source code clean up, removing pre-Medusa
      stuff (like I did about 3 years ago on Ursula, sigh). That's
      why loads of source files have changed. The new DA stuff
      is confined pretty much to hdr.KernelWS and s.ChangeDyn.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_38'
  14. 15 Jun, 2001 1 commit
    • Mike Stephens's avatar
      Merge in long command line support from Ursula kernel. · 8727ebaa
      Mike Stephens authored
      Look for LongCommandLine flag, command line size currently
      set at 1k.
      For HAL/32bit builds, the kernel buffer space is at high
      (top bit set) address, which may break some code using signed
      comparisons. So *beware* that there may be some latent
      bugs in old kernel code using these buffers, not yet found.
      One such bug, in s.Arthur2 found and fixed.
      Tested moderately on ARM9 desktop build.
      Lovely to reimplement things I did two and half years ago.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_37'
  15. 13 Jun, 2001 3 commits
    • Mike Stephens's avatar
      Changes to Lazy task swapping to support abort handler in abort mode (now that we can count to 32). · a0f4966c
      Mike Stephens authored
      LazyFixup now ensures all app pages are mapped in before handing
      on a real (no-lazy) abort. This allows an abort handler in app
      space itself, without scrambling the details of the original
      abort (via a lazy abort in abort mode).
      Many a happy minute spent coding and testing for recursive
      aborts and fixups, but lets just pretend it doesn't happen
      shall we.
      Tested with simple popbang code on ARM9 desktop build.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_36'
    • Simon Forrest's avatar
      * Added FIQ disabling code to HAL entry table. · f35516b7
      Simon Forrest authored
        * (As above.)  The HAL entry table was missing the HAL_FIQDisableCode
          entry, causing assertion checks to fail.
        * Problem found during Customer L build.
        * Built but untested.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_35'
    • Kevin Bracey's avatar
      Moved IOAllocPtr and IOAllocLimit to SkippedTables - the ARM9 got away with it... · 5d747bd7
      Kevin Bracey authored
      Moved IOAllocPtr and IOAllocLimit to SkippedTables - the ARM9 got away with it because of the writeback cache, but poor souls like Simon condemned to an eternity of the ARM7 were a bit stuffed.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_34'
  16. 11 Jun, 2001 1 commit
  17. 06 Jun, 2001 1 commit
    • Mike Stephens's avatar
      Further work on Lazy task swapping: · ae287104
      Mike Stephens authored
        hooks to give correct mapping info for OS_Memory 0
        same for OS_ReadMemMapEntries
        same for OS_FindMemMapEntries
        Lazy fixup routine no longer assumes an abort in current
        app space must be a truant page. However, work in this
        area not complete (no support yet for abort handler code
        in app space itself, eg. for C trampoline)
      Good to know this will be a big performance boost when
      our products use one monolithic application (sarcasm).
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_32'
  18. 22 May, 2001 1 commit
    • Mike Stephens's avatar
      Reimplement Lazy task swapping, an amusing idea from Ursula, would have done... · bdc4f843
      Mike Stephens authored
      Reimplement Lazy task swapping, an amusing idea from Ursula, would have done it sooner but couldn't be bothered (humour).
      Currently activates for all ARMs flagged as base-restored
      abort model. No handling of eg. StrongARM pre-revT bug, but
      then the kernel no longer runs on StrongARM (progress).
      Still some details to fix: all aborts in current app space
      assumed to be missing pages, but this must be fixed to
      handle abort code in app space, things like debuggers
      marking code read only.
      Plus, small fixes:
        OS_Memory 8 returns vaguely useful info for RAM,VRAM
        in HAL build (temporary partial implementation)
        Broken handling of old BBC commands with (fx,tv etc)
        with no spaces fixed (fudgeulike code from Ursula,
        now 32-bit).
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_31'
  19. 17 May, 2001 1 commit
    • Kevin Bracey's avatar
      * Fixed the IIC code. · 390c26e8
      Kevin Bracey authored
      * Kernel puts sensible default FIQ handler in through the HAL.
      * Fix to temporary page uncaching code.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_30'
  20. 11 May, 2001 1 commit
    • Simon Forrest's avatar
      * Variant of the Kernel and L7200 HAL that supports multiple hardware targets. · ea50d7a5
      Simon Forrest authored
        * Must now specify the hardware target
          to ensure that the L7200 HAL is built with the appropriate tweaks to
          support each.  This is achieved by specifying:
                    -options "BOARD=<target>"
          within the components file for the HAL_L7200 component.
        * Tested on Customer L build to create a ROM suitable for the Customer M unit
          (that has only minor differences to the Customer L).
        * Affects all projects using the L7200 HAL, which must now specify the
          hardware target in the components file.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_29'
  21. 01 May, 2001 1 commit
  22. 20 Apr, 2001 1 commit
  23. 11 Apr, 2001 1 commit
  24. 29 Mar, 2001 2 commits
    • Dan Ellis's avatar
      Baud rate return is more correct. · d068e40f
      Dan Ellis authored
        Maths was wrong.  The returned baud rate is the crystal frequency divided
      by the divisor.
        Assembles, not tested.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_25'
    • Dan Ellis's avatar
      Fixed UART baud rate · f9911b4b
      Dan Ellis authored
        MOV a3, a1 doesn't move a3 into a1...
        Not tested.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_24'
  25. 27 Mar, 2001 1 commit
  26. 20 Mar, 2001 1 commit
  27. 19 Mar, 2001 1 commit
  28. 16 Mar, 2001 1 commit
  29. 08 Mar, 2001 1 commit
    • Kevin Bracey's avatar
      Added some missing IIC and USB files. · 9d13b691
      Kevin Bracey authored
      An attempt to do NVMemory by using part of the Flash that the OS is sitting
      in for Customer L. Programming algorithm works, but I'm not confident that the
      Kernel does the right thing yet.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_19'
  30. 07 Mar, 2001 1 commit
  31. 01 Mar, 2001 1 commit
  32. 13 Feb, 2001 1 commit
  33. 01 Feb, 2001 1 commit
    • Dan Ellis's avatar
      Addition of HAL UART for Customer L · 69043479
      Dan Ellis authored
        HAL entries have been entered for the Customer L UART (very much like the ARM
      PrimeCell, rather than the 16550).
        It builds.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_16'
  34. 25 Jan, 2001 1 commit
  35. 23 Jan, 2001 2 commits