From f1b16e9f6874166503e22f606a7f2cb023ce0046 Mon Sep 17 00:00:00 2001
From: Kevin Bracey <kbracey@gitlab.riscosopen.org>
Date: Thu, 20 Apr 2000 14:57:28 +0000
Subject: [PATCH] OS_CallASWI and OS_CallASWIR12 sped up by 4-6 cycles
(depending on which ARM).
Some POST changes which got lost recommitted.
Version 5.24. Not tagged
---
TestSrc/Begin | 9 ++++++---
VersionASM | 2 +-
VersionNum | 4 ++--
s/Kernel | 12 +++++-------
4 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/TestSrc/Begin b/TestSrc/Begin
index 9768f76a..992cf15b 100644
--- a/TestSrc/Begin
+++ b/TestSrc/Begin
@@ -92,6 +92,9 @@
; 19 Jun 97 BAR 2.25 Remove un-necessary mov r13,r14's
; When completed flashing LED's restore the
; faultcode flag from fiq_regs.
+; 04 Apr 00 KJB 2.30 Converted to run in 32-bit mode always.
+; ShowIOMDRegs set to FALSE (request from
+; Tom Clay)
;
;------------------------------------------------------------------------
;
@@ -104,8 +107,8 @@
TS_STATUS * "R" ; Medusa POST version 2.0x
;
-TS_RELEASE * 22
-TS_CHANGES * 4
+TS_RELEASE * 23
+TS_CHANGES * 0
GBLL POSTenabled
@@ -115,7 +118,7 @@ POSTenabled SETL {TRUE} ; don't permit POST for ordinary startup
AlwaysShortPOST SETL {TRUE} :LAND: STB ; always do a short POST
GBLL ShowIOMDRegs
-ShowIOMDRegs SETL (IO_Type = "IOMD") :LAND: {TRUE} :LAND: STB ; show IOMD regs
+ShowIOMDRegs SETL (IO_Type = "IOMD") :LAND: {FALSE} :LAND: STB ; show IOMD regs
GBLL DontShowProgressColours
DontShowProgressColours SETL {TRUE} :LAND: STB ; Do not show the progress colour screens.
diff --git a/VersionASM b/VersionASM
index 9e603274..de1e017f 100644
--- a/VersionASM
+++ b/VersionASM
@@ -9,6 +9,6 @@
Module_MajorVersion SETS "5.24"
Module_Version SETA 524
Module_MinorVersion SETS ""
-Module_Date SETS "17 Apr 2000"
+Module_Date SETS "20 Apr 2000"
Module_FullVersion SETS "5.24"
END
diff --git a/VersionNum b/VersionNum
index d7a6f553..f687d014 100644
--- a/VersionNum
+++ b/VersionNum
@@ -5,11 +5,11 @@
*/
#define Module_MajorVersion_CMHG 5.24
#define Module_MinorVersion_CMHG
-#define Module_Date_CMHG 17 Apr 2000
+#define Module_Date_CMHG 20 Apr 2000
#define Module_MajorVersion "5.24"
#define Module_Version 524
#define Module_MinorVersion ""
-#define Module_Date "17 Apr 2000"
+#define Module_Date "20 Apr 2000"
#define Module_FullVersion "5.24"
diff --git a/s/Kernel b/s/Kernel
index c5e2ed81..b2506227 100644
--- a/s/Kernel
+++ b/s/Kernel
@@ -463,17 +463,17 @@ SVC * {PC}-SWIRelocation
Push "r11,r14" ; push SWI number and return address
-SVC_CallASWI * {PC}-SWIRelocation ; CallASWI,CallASWIR12 re-entry point
-
- BICS r11, r11, #Auto_Error_SWI_bit
- BEQ SWIWriteC + SWIRelocation
-
AND r10, r12, #I32_bit+F32_bit
ORR r10, r10, #SVC2632 ; set IFTMMMMM = IF0x0011
msr ,CPSR_c, r10 ; restore caller's IRQ state
BIC r14, r12, #V_bit ; clear V (some SWIs need original PSR in r12)
+SVC_CallASWI * {PC}-SWIRelocation ; CallASWI,CallASWIR12 re-entry point
+
+ BICS r11, r11, #Auto_Error_SWI_bit
+ BEQ SWIWriteC + SWIRelocation
+
CMP r11, #OS_WriteI
LDRLO pc, [pc, r11, LSL #2]
@@ -895,13 +895,11 @@ process_callback_chain ROUT
; SWI OS_WriteC
; In r11 = 0 (look, up there ^) !
-; r12 = SPSR
SWIWriteC ROUT
msr ,CPSR_c, #SVC2632 ; enable interrupts
- BIC lr, r12, #V_bit ; clear caller's V cos we didn't before
STR lr, [sp, #-4]!
LDR r11, [r11, #VecPtrTab+WrchV*4] ; load top node pointer
--
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