From dc5f83904b1170ff44425d34e4ec5f93c4a22e18 Mon Sep 17 00:00:00 2001
From: Kevin Bracey <kbracey@gitlab.riscosopen.org>
Date: Thu, 23 Sep 1999 16:47:45 +0000
Subject: [PATCH] Added support for ATMEL 4K and 8K EEPROM parts, including
write protection of top quarter. Untested.
Added support for ARM7500FE IO clock divide by 2.
Version 4.89. Tagged as 'Kernel-4_89'
---
VersionASM | 8 +++---
VersionNum | 14 +++++-----
hdr/KernelWS | 1 +
s/ARM600 | 8 ++++++
s/PMF/i2cutils | 74 ++++++++++++++++++++++++++++++++++++++++++++++++--
5 files changed, 92 insertions(+), 13 deletions(-)
diff --git a/VersionASM b/VersionASM
index 97dc3582..507e62f6 100644
--- a/VersionASM
+++ b/VersionASM
@@ -6,9 +6,9 @@
GBLS Module_MinorVersion
GBLS Module_Date
GBLS Module_FullVersion
-Module_MajorVersion SETS "4.88"
-Module_Version SETA 488
+Module_MajorVersion SETS "4.89"
+Module_Version SETA 489
Module_MinorVersion SETS ""
-Module_Date SETS "20 Sep 1999"
-Module_FullVersion SETS "4.88"
+Module_Date SETS "23 Sep 1999"
+Module_FullVersion SETS "4.89"
END
diff --git a/VersionNum b/VersionNum
index b4aa174a..19b2aa75 100644
--- a/VersionNum
+++ b/VersionNum
@@ -1,15 +1,15 @@
-/* (4.88)
+/* (4.89)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
-#define Module_MajorVersion_CMHG 4.88
+#define Module_MajorVersion_CMHG 4.89
#define Module_MinorVersion_CMHG
-#define Module_Date_CMHG 20 Sep 1999
+#define Module_Date_CMHG 23 Sep 1999
-#define Module_MajorVersion "4.88"
-#define Module_Version 488
+#define Module_MajorVersion "4.89"
+#define Module_Version 489
#define Module_MinorVersion ""
-#define Module_Date "20 Sep 1999"
+#define Module_Date "23 Sep 1999"
-#define Module_FullVersion "4.88"
+#define Module_FullVersion "4.89"
diff --git a/hdr/KernelWS b/hdr/KernelWS
index c5ea4107..47615457 100644
--- a/hdr/KernelWS
+++ b/hdr/KernelWS
@@ -1083,6 +1083,7 @@ RTCFitted # 1 ; flag =1 iff RTC is fitted
NVRamBase # 1 ; Base of NVRam
NVRamSpeed # 1 ; Clock hold time in 0.5µs units
NVRamPageSize # 1 ; Page size for writing (log2)
+NVRamWriteSize # 1 ; Size of writable region (256byte units)
]
diff --git a/s/ARM600 b/s/ARM600
index 01594e62..aad1e5f4 100644
--- a/s/ARM600
+++ b/s/ARM600
@@ -965,9 +965,17 @@ init7500FEcpu
; IOCLK divide by 1
;
[ FECPUSpeedNormal
+ [ FEIOSpeedHalf
MOV r0, #IOMD_CLKCTL_CpuclkNormal + IOMD_CLKCTL_MemclkNormal + IOMD_CLKCTL_IOclkNormal
+ |
+ MOV r0, #IOMD_CLKCTL_CpuclkNormal + IOMD_CLKCTL_MemclkNormal + IOMD_CLKCTL_IOclkHalf
+ ]
|
+ [ FEIOSpeedHalf
MOV r0, #IOMD_CLKCTL_CpuclkHalf + IOMD_CLKCTL_MemclkNormal + IOMD_CLKCTL_IOclkNormal
+ |
+ MOV r0, #IOMD_CLKCTL_CpuclkHalf + IOMD_CLKCTL_MemclkNormal + IOMD_CLKCTL_IOclkHalf
+ ]
]
]
STRB r0, [r12, #IOMD_CLKCTL] ; initialise all the prescalers.
diff --git a/s/PMF/i2cutils b/s/PMF/i2cutils
index 77038d5d..2820f8a0 100644
--- a/s/PMF/i2cutils
+++ b/s/PMF/i2cutils
@@ -35,6 +35,7 @@
; 17-Sep-98 KJB Add support for 16K 24C128 EEPROM.
; 21-Sep-98 KJB Add OS_NVMemory SWI.
; 30-Jul-99 KJB Add support for 8K 24C64 EEPROM.
+; 23-Sep-99 KJB Remove support for 24C64, add support for 4K and 8K protectable ATMEL parts.
PhysChecksum * (((CheckSumCMOS + &30) :MOD: &F0) + &10)
@@ -47,7 +48,8 @@ RTCAddress * &a0 ; traditional RTC / 240 byte CMOS
E2ROMAddress * &a8 ; 24C08 device - 512 byte or 1K
E2ROMAddress2K * &e0 ; 24C174 device - 2K
E2ROMAddress2K_OTP * &60 ; 24C174 device - OTP section
-E2ROMAddress8K * &a2 ; 24C64 device - 8K
+E2ROMAddress4K * &a4 ; 24C32 device - 4K (top 1K protectable)
+E2ROMAddress8K * &a2 ; 24C64 device - 8K (top 2K protectable)
E2ROMAddress16K * &a8 ; 24C128 device - 16K
]
@@ -459,6 +461,11 @@ Write
Pull "R0-R4, PC", CC ; don't write to OTP section
]
+ MOV R14, #0 ; don't write to protected section
+ LDRB R14, [R14, #NVRamWriteSize]
+ CMP R0, R14 ; (note assumption that NVRamWriteSize is
+ Pull "R0-R4, PC", HS ; outside mangled region).
+
MOV R2, R0
MOV R3, R1
[ ChecksumCMOS
@@ -533,13 +540,16 @@ WriteBlock ROUT
[ E2ROMSupport
[ :LNOT: :DEF: TestHarness
MOV R14, #0
+ LDRB R4, [R14, #NVRamWriteSize]
LDRB R14, [R14, #NVRamSize]
|
LDRB R14, NVSize
+ MOV R4, R14
]
MOV R14, R14, LSL #8
|
MOV R14, #240
+ MOV R4, R14
]
CMP R0, R14
@@ -550,6 +560,12 @@ WriteBlock ROUT
CMP R3, R14
BHI %FT90
+ CMP R0, R4 ; ignore writes totally outside writable area
+ BHS %FT80
+
+ SUBS R14, R3, R4
+ SUBGT R2, R2, R14 ; truncate writes partially outside writable area
+
TEQ R2, #0
BEQ %FT80
@@ -1304,6 +1320,38 @@ MakeChecksum ROUT
LTORG
+; *****************************************************************************
+;
+; OS_SetTime - Set the real-time clock
+;
+; in: R0 = pointer to 5 byte UTC time
+;
+; out: R0 preserved
+;
+
+SetTimeSWI ROUT
+ Push "R0-R8"
+ SUB SP, SP, #36
+ MOV R1, R0
+ MOV R2, SP
+ SWI XTerritory_ConvertTimeToUTCOrdinals
+ ADDVS SP, SP, #36+4
+ Pull "R1-R8", VS
+ ExitSWIHandler VS
+ LDR R8, [SP], #4 ; centiseconds
+ LDR R7, [SP], #4 ; seconds
+ LDR R1, [SP], #4 ; minutes
+ Pull "R0,R2,R3,R5" ; hours, day, month, year
+ ADD SP, SP, #8 ; junk day of week and year
+ MOV R4, #100
+ DivRem R6, R5, R4, R14 ; R5 = year (lo), R6 = year (hi)
+
+ BL SetTime
+
+ STRVS R0,[SP]
+ Pull "R0-R8"
+ ExitSWIHandler
+
; *****************************************************************************
;
; SetTime - Write the CMOS clock time and update 5-byte RealTime
@@ -1492,7 +1540,7 @@ ReadTime ROUT
[ CacheCMOSRAM
-InitCMOSCache ENTRY "r0-r5"
+InitCMOSCache ENTRY "r0-r6"
[ E2ROMSupport
; Need to set the slowest speed so we can probe
@@ -1521,6 +1569,7 @@ InitCMOSCache ENTRY "r0-r5"
STRB R4, RTCFlag
]
MOV R5, #4 ; assume 16 byte page size to start with
+ MOV R6, #0 ; assume not protected
; Have we got a 2K E² ?
MOV r1, #E2ROMAddress2K
@@ -1559,12 +1608,30 @@ InitCMOSCache ENTRY "r0-r5"
]
BVC %FT5
+; Have we got a 4K device?
+
+ MOV r1, #E2ROMAddress4K
+ MOV r0, #E2ROMAddress4K
+ BL DummyAccess
+ MOVVC R4, #16
+ [ IOMD_C_EEPROMProtect <> 0
+ MOVVC R6, #12 ; Only bottom 3K writable
+ ]
+ MOVVC R5, #5 ; 32 byte page size
+ [ ClockNVMemoryFast
+ MOVVC R3, #3 ; Fast speed setting (1.5µs delays)
+ ]
+ BVC %FT5
+
; Have we got an 8K device?
MOV r1, #E2ROMAddress8K
MOV r0, #E2ROMAddress8K
BL DummyAccess
MOVVC R4, #32
+ [ IOMD_C_EEPROMProtect <> 0
+ MOVVC R6, #24 ; Only bottom 6K writable
+ ]
MOVVC R5, #5 ; 32 byte page size
[ ClockNVMemoryFast
MOVVC R3, #3 ; Fast speed setting (1.5µs delays)
@@ -1579,6 +1646,9 @@ InitCMOSCache ENTRY "r0-r5"
STRB R1, [R2, #NVRamBase]
STRB R4, [R2, #NVRamSize]
STRB R5, [R2, #NVRamPageSize]
+ TEQ R6, #0
+ MOVEQ R6, R4
+ STRB R6, [R2, #NVRamWriteSize]
[ ClockNVMemoryFast
STRB R3, [R2, #NVRamSpeed]
]
--
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