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Commit d10d2336 authored by Jeffrey Lee's avatar Jeffrey Lee

Clear the exclusive monitor when returning to pre-empted code

Detail:
  s/Kernel - Add macro for CLREX, which uses a dummy STREX on basic ARMv6 machines. Clear the exclusive monitor after issuing transient callbacks, to cope with callbacks being triggered on exit from IRQ
  s/ArthurSWIs, s/HAL, s/NewIRQs - Clear the exclusive monitor on exit from IRQ handlers & default FIQ handler
  s/VMSAv6 - Clear the exclusive monitor on entry to the data abort pre-veneer
Admin:
  Tested on Raspberry Pi
  Non-transient callback handlers, custom abort handlers, FIQ handlers, and anything else which returns directly to interrupted user code is responsible for issuing its own CLREX if the code has done something that could have left the local monitor in the exclusive state (e.g. calling a SWI counts towards this, as there's no guarantee the monitor will be open on exit from the SWI)


Version 5.35, 4.79.2.327. Tagged as 'Kernel-5_35-4_79_2_327'
parent 8a653457
......@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.326"
Module_Date SETS "01 Jun 2016"
Module_ApplicationDate SETS "01-Jun-16"
Module_MinorVersion SETS "4.79.2.327"
Module_Date SETS "15 Jun 2016"
Module_ApplicationDate SETS "15-Jun-16"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.326)"
Module_HelpVersion SETS "5.35 (01 Jun 2016) 4.79.2.326"
Module_FullVersion SETS "5.35 (4.79.2.327)"
Module_HelpVersion SETS "5.35 (15 Jun 2016) 4.79.2.327"
END
......@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.326
#define Module_Date_CMHG 01 Jun 2016
#define Module_MinorVersion_CMHG 4.79.2.327
#define Module_Date_CMHG 15 Jun 2016
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.326"
#define Module_Date "01 Jun 2016"
#define Module_MinorVersion "4.79.2.327"
#define Module_Date "15 Jun 2016"
#define Module_ApplicationDate "01-Jun-16"
#define Module_ApplicationDate "15-Jun-16"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.326)"
#define Module_HelpVersion "5.35 (01 Jun 2016) 4.79.2.326"
#define Module_FullVersion "5.35 (4.79.2.327)"
#define Module_HelpVersion "5.35 (15 Jun 2016) 4.79.2.327"
#define Module_LibraryVersionInfo "5:35"
......@@ -1172,6 +1172,7 @@ FIQKiller
STMFD R13!, {R0-R3,R14}
MOV R14, PC
LDMIA R10, {R9,PC}
MyCLREX R0, R1
LDMFD R13!, {R0-R3,PC}^
FIQKiller_ws
]
......
......@@ -2917,6 +2917,7 @@ Reset_IRQ_Handler
CMP a1, #-1
CallHAL HAL_IRQDisable,NE ; Stop the rogue device from killing us completely
Reset_IRQ_Exit
MyCLREX a1, a2
Pull "a1-a2,lr"
MSR CPSR_c, a2
MSR SPSR_cxsf, a1
......
......@@ -91,6 +91,26 @@ $label VDWS $reg
$label LDR $reg, =ZeroPage+VduDriverWorkSpace
MEND
; *******************************************************************
; *** MyCLREX - Manually clear exclusive monitor ***
; *** Consult the ARM ARM for details of when this is required! ***
; *******************************************************************
MACRO
MyCLREX $temp1, $temp2
[ NoARMv6
ASSERT :LNOT: SupportARMv6
; No action required
ELIF NoARMK
; ARMv6, need dummy STREX
; Use the word below SP
SUB $temp1, r13, #4
STREX $temp2, $temp1, [$temp1]
|
; ARMv6K+, have CLREX
CLREX
]
MEND
; one that builds a module command table entry:
; set Module_BaseAddr to module base before use.
......@@ -1058,6 +1078,9 @@ Do_CallBack_postpone_already_clear
BLNE process_callback_chain
MOV lr,r12
ASSERT FixCallBacks ; (clobbering r11)
MyCLREX r11, r12 ; CLREX required for the case where transient callbacks have been triggered on exit from IRQ handling
[ FixCallBacks
LDRB r11, [r10, #CallBack_Flag] ; non-transient callback may have been set during transient callbacks
]
......
......@@ -76,16 +76,18 @@ Initial_IRQ_Code ROUT
LDRB r11, [r11, #CallBack_Flag]
TEQ r11, #0
Pull "r1-r3, r11, r12, lr", EQ
MSREQ SPSR_cxsf, lr
Pull "r0, pc", EQ, ^
BNE %FT10
05
MyCLREX r0, r1
Pull "r1-r3, r11, r12, lr"
MSR SPSR_cxsf, lr
Pull "r0, pc",, ^
10
TST r11, #CBack_Postpone
LDREQ lr, [sp_irq, #4*5] ; get SPSR off stack
TSTEQ lr, #I32_bit :OR: &0F ; check we came from USR26 or USR32 mode, with IRQs enabled
Pull "r1-r3, r11, r12, lr", NE
MSRNE SPSR_cxsf, lr
Pull "r0, pc", NE, ^
BNE %BT05
; Do a CallBack: asked for, not postponed, and we're returning into USR26/32 mode.
......
......@@ -592,6 +592,8 @@ DAbPreVeneer ROUT
STMIA r13_abort, {r0-r7} ; save unbanked registers anyway
STR lr_abort, [r13_abort, #15*4] ; save old PC, ie instruction address
MyCLREX r0, r1 ; Exclusive monitor is in unpredictable state "after taking a data abort", clear it here
; Fixup code for MVA-based cache/TLB ops, which can abort on ARMv7 if the specified MVA doesn't have a mapping.
; Must come before AMBControl, else things can go very wrong during OS_ChangeDynamicArea
; MVA cache ops have the form coproc=p15, CRn=c7, opc1=0, opc2=1
......
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