Commit ce95d42e authored by Jeffrey Lee's avatar Jeffrey Lee Committed by ROOL
Browse files

Remove 1MB bodge from LongDesc LoadAndDecodeL1Entry

LoadAndDecodeL1Entry will now always return the size/alignment of the
entry. This allows ConstructCAMfromPageTables to walk over a 2MB long
descriptor page table pointer in one go, instead of splitting it into
two 1MB chunks (as if short descriptor page tables were in use) and
calling LoadAndDecodeL1Entry twice. This has allowed the 1MB result
alignment bodge to be removed from the LongDesc version of
LoadAndDecodeL1Entry.
parent 15a7d5ee
......@@ -476,15 +476,16 @@ LoadAndDecodeL2Entry ROUT
; In:
; r0 = MB-aligned logical addr
; Out:
; r0,r1 = phys addr of section or L2PT entry
; r0,r1 = phys addr of start of section or L2PT entry
; r2 = page flags if 1MB page
; or -1 if fault
; or -2 if page table ptr
; r3 = section size (bytes) if section-mapped
; r3 = entry size/alignment (bytes)
LoadAndDecodeL1Entry
ALTENTRY
LDR r1, =L1PT
LDR r0, [r1, r0, LSR #20-2]
MOV r3, #1048576
AND r2, r0, #3
ASSERT L1_Fault < L1_Page
ASSERT L1_Page < L1_Section
......@@ -510,7 +511,6 @@ LoadAndDecodeL1Entry
MOV r0, r0, LSR #20
MOV r0, r0, LSL #20
MOV r1, #0
MOV r3, #1048576
; Jump to common code to do AP decode + PCBTrans search
B %BT20
......
......@@ -1765,11 +1765,12 @@ ConstructCAMfromPageTables
30 MOV a1, v2
BL LoadAndDecodeL1Entry ; a1,a2 = phys addr, a3 = page flags/type, a4 = page size (bytes)
CMP a3, #-2 ; Only care about page table pointers
BEQ %FT40
ADDS v2, v2, #&00100000
BEQ %FT39
ADDS v2, v2, a4
BCC %BT30
Pull "v1-v8, pc"
39 ADD v7, v2, a4
40 MOV a1, v2
BL LoadAndDecodeL2Entry ; a1,a2 = phys addr, a3 = flags (-1 if fault), a4 = page size (bytes)
CMP a3, #-1 ; move to next page if fault
......@@ -1784,11 +1785,10 @@ ConstructCAMfromPageTables
ASSERT CAM_PageFlags=4
STMCCIA a1, {v2, v6} ; store logical address, PPL
80 ADD v2, v2, #&00001000
TST v2, #&000FF000
BNE %BT40
TEQ v2, #0 ; yuck (could use C from ADDS but TST corrupts C
BNE %BT30 ; because of big constant)
80 ADDS v2, v2, #&00001000 ; always advance in 4K units here
TEQ v2, v7
BNE %BT40 ; more to do from this L1 entry
BCC %BT30 ; logical address not wrapped yet
Pull "v1-v8, pc"
......
......@@ -2347,24 +2347,27 @@ CheckMemoryAccess ROUT
LDR r9, [r10, #IOAllocTop]
CMP r1, r9
BHS %FT40
MOV r3, r1, LSR #20
MOV r6, r1, LSR #20
LDR r4, [r10, #IOAllocPtr]
MOV r3, r3, LSL #20 ; Get MB-aligned addr of first entry to check
CMP r3, r4
MOVLO r3, r4 ; Skip all the unallocated regions
MOV r6, r6, LSL #20 ; Get MB-aligned addr of first entry to check
CMP r6, r4
MOVLO r6, r4 ; Skip all the unallocated regions
31
Push "r0-r3"
MOV r0, r3
Push "r0-r2"
MOV r0, r6
BL LoadAndDecodeL1Entry ; TODO bit wasteful. We only care about access privileges, but this call gives us cache info too.
LDR r5, [r10, #MMU_PPLAccess]
AND lr, r2, #DynAreaFlags_APBits
LDR r5, [r5, lr, LSL #2]
Pull "r0-r3"
ADD r4, r3, #1<<20
Pull "r0-r2"
SUB lr, r3, #1
ADD r4, r6, r3
BIC r3, r6, lr ; Aligned start addr
BIC r4, r4, lr ; Aligned end addr
ORR r5, r5, #CMA_Partially_Phys
BL CMA_AddRange2
CMP r4, r9
MOV r3, r4
MOV r6, r4
BNE %BT31
40
; Everything else!
......@@ -2473,7 +2476,6 @@ CheckMemoryAccess ROUT
Pull "r0-r2"
BHS %FT80
ADD r4, r3, #PhysicalAccess
! 0, "LongDescTODO 1MB bodge in LoadAndDecodeL1Entry will make this wrong"
LDR r5, [r10, #MMU_PPLAccess]
LDR r3, =PhysicalAccess
LDR r5, [r5, lr, LSL #2]
......
......@@ -417,27 +417,22 @@ LoadAndDecodeL2Entry ROUT
; In:
; r0 = MB-aligned logical addr
; Out:
; r0,r1 = phys addr of section or L2PT entry
; r0,r1 = phys addr of start of section or L2PT entry
; r2 = page flags if 1MB page
; or -1 if fault
; or -2 if page table ptr
; r3 = section size (bytes) if section-mapped
; r3 = entry size/alignment (bytes)
LoadAndDecodeL1Entry
; Note that currently this really is only aligned to 1MB, not 2MB (and
; returned page size should be 1MB). TODO: Try and tidy this up (always
; returning the mapping size might help?)
! 0, "LongDescTODO Remove LoadAndDecodeL1Entry 1MB bodge"
LDR r1, =LL2PT
AND r2, r0, #1:SHL:20
ADD r0, r1, r0, LSR #18
BIC r0, r0, #7 ; Input is only 1MB aligned
LDRD r0, [r0]
ANDS r3, r0, #LL_TypeMask
MOVEQ r2, #-1
MOVEQ r3, #1:SHL:21
MOVEQ pc, lr
CMP r3, #LL12_Block
ORREQ r0, r0, r2 ; Add in the megabyte offset
MOVEQ r3, #1:SHL:20 ; And pretend it's a megabyte page size
MOV r3, #1:SHL:21
BEQ %BT05 ; Branch to common decode code
; Table pointer
MOV r2, #-2
......
......@@ -413,11 +413,11 @@ LoadAndDecodeL2Entry ROUT
; In:
; r0 = MB-aligned logical addr
; Out:
; r0,r1 = phys addr of section or L2PT entry
; r0,r1 = phys addr of start of section or L2PT entry
; r2 = page flags if 1MB page
; or -1 if fault
; or -2 if page table ptr
; r3 = section size (bytes) if section-mapped
; r3 = entry size/alignment (bytes)
LoadAndDecodeL1Entry
ALTENTRY
LDR r1, =L1PT
......@@ -427,6 +427,7 @@ LoadAndDecodeL1Entry
ASSERT L1_Page < L1_Section
CMP r2, #L1_Page
BGT %FT50
MOV r3, #1048576
MOVLT r2, #-1
MOVEQ r2, #-2
MOVEQ r0, r0, LSR #10
......
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