Commit ba993cb5 authored by Jeffrey Lee's avatar Jeffrey Lee Committed by ROOL
Browse files

Support runtime selection of pagetable format

Runtime selection between long descriptor and short descriptor page
table format is now possible (with the decision based on whether the HAL
registers any high RAM or not). The main source changes are as follows:

* LongDesc and ShortDesc switches are in hdr.Options to control what
kernel variant is built
* PTOp and PTWhich macros introduced in hdr.ARMops to allow for
invocation of functions / code blocks which are specific to the page
table format. If the kernel is being built with only one page table
format enabled, PTOp is just a BL instruction, ensuring there's no
performance loss compared to the old code.
* _LongDesc and _ShortDesc suffixes added to various function names, to
allow both versions of the function to be included at once if runtime
selection is enabled
* Most of the kernel / MMU initialisation code in s.HAL is now encased
in a big WHILE loop, allowing it to be duplicated if runtime switching
is enabled (easier than adding dynamic branches all...
parent ce95d42e
......@@ -86,5 +86,38 @@ ARMunk * 255
]
MEND
; Call pagetable operation routine
GBLS pt
MACRO
PTOp$cc $op
[ "$pt" <> "" ; Scoped to just one type?
BL$cc $op._$pt
ELIF LongDesc :LAND: ShortDesc
[ "$cc"<>"" :LAND: "$cc"<>"AL"
LCLS rcc
rcc SETS :REVERSE_CC:"$cc"
B$rcc %FT90
]
MRC p15, 0, lr, c2, c0, 2 ; Read TTBCR (yuck)
TST lr, #&80000000 ; Long descriptors enabled?
ADR lr, %FT90
BNE $op._LongDesc
B $op._ShortDesc
90
ELIF LongDesc
BL$cc $op._LongDesc
|
BL$cc $op._ShortDesc
]
MEND
[ LongDesc :LAND: ShortDesc
; NE if LongDesc, EQ if ShortDesc
MACRO
PTWhich $temp
MRC p15, 0, $temp, c2, c0, 2
TST $temp, #&80000000
MEND
]
END
......@@ -298,13 +298,20 @@ UNDStackAddress ASpace UNDStackSize, &100000
DCacheCleanAddress ASpace &00040000, &10000 ; eg. for StrongARM, 256k of space
KbuffsBaseAddress ASpace KbuffsMaxSize ; kernel buffers for long command lines
HALWorkspaceNCNB ASpace &00008000 ; 32K of uncacheable HAL workspace (if requested)
KWSLongDescBase * :INDEX: @
[ LongDesc
LL3PT ASpace &00800000, &100000 ; 8MB of L3PT
LL2PT ASpace &00004000 ; 16KB of L2PT
LL1PT ASpace &00001000 ; 32 bytes of L1PT
|
L2PT ASpace &00400000, &400000
L1PT ASpace &00004000
]
[ ShortDesc
KWSLongDescLimit * :INDEX: @
# KWSLongDescBase-(:INDEX:@) ; Wind back so that long & short descriptor page tables share the same address space
L2PT ASpace &00400000, &400000 ; 4MB of L2PT
L1PT ASpace &00004000 ; 16KB of L1PT
[ (:INDEX: @) < KWSLongDescLimit
# KWSLongDescLimit-(:INDEX:@) ; Wind forwards
]
]
ASSERT &FAFF0000-@ < &80000000
# &FAFF0000-@ ; padding to ensure SoundWorkSpace export is correct (in CursorChunkAddress)
......
......@@ -182,9 +182,16 @@ PMPRAMFS_Size * 256 ; Number of logical pages (physi
[ :LNOT: :DEF: LongDesc
GBLL LongDesc
LongDesc SETL {FALSE} :LAND: MEMM_Type = "VMSAv6" ; Use long descriptor page table format?
LongDesc SETL {FALSE} :LAND: MEMM_Type = "VMSAv6" ; Support long descriptor page table format?
]
[ :LNOT: :DEF: ShortDesc
GBLL ShortDesc
ShortDesc SETL {TRUE} ; Support short descriptor page table format?
]
ASSERT LongDesc :LOR: ShortDesc ; Must support at least one!
GBLL CacheablePageTables
CacheablePageTables SETL {TRUE} ; Use cacheable page tables where possible
......
......@@ -71,11 +71,7 @@ AMBControl_Init
MOVNE R1,#AMBFlag_LazyMapIn_disable
STR R1,AMBFlags
; Calculate default page flags
MOV R0, #0
MOV R1, #0
GetPTE R0, 4K, R0, R1
STR R0,AMBPageFlags
PTOp AMB_SetPageFlags
|
MOV R1,#AMBFlag_LazyMapIn_disable
STR R1,AMBFlags
......
......@@ -88,7 +88,11 @@ ms_domapout
MOV r1,#0
MOVS r5,r3
MOV r7,#0
BLNE AMB_SetMemMapEntries_MapOut_Lazy
[ AMB_LazyMapIn
PTOpNE AMB_SetMemMapEntries_MapOut_Lazy
|
BLNE AMB_SetMemMapEntries_MapOut
]
Pull "r1,r5,r7,r10"
ms_donemap
......
......@@ -79,7 +79,7 @@ AMB_SetMemMapEntries_MapIn ROUT
ADD r10,r10,r1,LSL #2
; Map in the pages (assuming area currently unmapped)
BL AMB_movepagesin_L2PT
PTOp AMB_movepagesin_L2PT
BL AMB_movepagesin_CAM
[ PMPParanoid
BL ValidatePMPs
......@@ -132,7 +132,7 @@ AMB_SetMemMapEntries_MapOut ROUT
ADD r10,r10,r1,LSL #2
; Map out the pages (assuming area currently fully mapped)
BL AMB_movecacheablepagesout_L2PT
PTOp AMB_movecacheablepagesout_L2PT
BL AMB_movepagesout_CAM
[ PMPParanoid
BL ValidatePMPs
......@@ -143,6 +143,16 @@ AMB_SetMemMapEntries_MapOut ROUT
EXIT
[ AMB_LazyMapIn
ptcounter SETA 0
WHILE ptcounter < 2
[ ptcounter = 0 :LAND: ShortDesc
pt SETS "ShortDesc"
ELIF ptcounter = 1 :LAND: LongDesc
pt SETS "LongDesc"
|
pt SETS ""
]
[ "$pt" <> ""
; ----------------------------------------------------------------------------------
;
; AMB_SetMemMapEntries_MapOut_Lazy:
......@@ -156,7 +166,7 @@ AMB_SetMemMapEntries_MapOut ROUT
; Lazy task swapping variant of SetMemMapEntries_MapOut
; Performs a sparse map out if lazy task swapping is enabled
;
AMB_SetMemMapEntries_MapOut_Lazy ROUT
AMB_SetMemMapEntries_MapOut_Lazy_$pt ROUT
LDR r7, AMBFlags
TST r7, #AMBFlag_LazyMapIn_disable :OR: AMBFlag_LazyMapIn_suspend
MOV r7, #0
......@@ -206,12 +216,13 @@ AMB_SetMemMapEntries_MapOut_Lazy ROUT
LDR r0,[r10,#DANode_Flags]
LDR r11,[r2,#MMU_PCBTrans]
GetTempUncache r12, r0, r11, lr ;r12 = temp uncache L2PT flags
MOV r4,r1 ;r4 = current index
[ LongDesc
[ pt = "LongDesc"
GetTempUncache_LongDesc r12, r0, r11, lr ;r12 = temp uncache L2PT flags
LDR r11,=LL3PT+(ApplicationStart:SHR:(Log2PageSize-3));r11 -> L3PT, offset by appspace start
|
GetTempUncache_ShortDesc r12, r0, r11, lr ;r12 = temp uncache L2PT flags
LDR r11,=L2PT+(ApplicationStart:SHR:(Log2PageSize-2));r11 -> L2PT, offset by appspace start
]
CMP r9,#1
......@@ -232,7 +243,7 @@ AMB_SetMemMapEntries_MapOut_Lazy ROUT
TST r8,r9
BEQ %FT34
; Mapped in page found, make uncacheable
[ LongDesc
[ pt = "LongDesc"
ADD lr,r11,r4,LSL #3
LDRD r0,[lr] ;Get current L3PT entry
CMP r6,#0
......@@ -312,7 +323,7 @@ AMB_SetMemMapEntries_MapOut_Lazy ROUT
TST r8,r9
BEQ %FT54
; Mapped in page found, unmap it
[ LongDesc
[ pt = "LongDesc"
MOV r0,#0
MOV r1,#0
ADD lr,r11,r4,LSL #3
......@@ -373,8 +384,12 @@ AMB_SetMemMapEntries_MapOut_Lazy ROUT
]
MOV r7,#0
EXIT
|
AMB_SetMemMapEntries_MapOut_Lazy * AMB_SetMemMapEntries_MapOut
]
ptcounter SETA ptcounter + 1
WEND
pt SETS ""
]
[ AMB_LazyMapIn
......@@ -471,24 +486,28 @@ AMB_LazyFixUp ROUT
ADD r4,r4,r6
MOV r4,r4,ROR #20 ;High address packed into low bits for LongDesc
MOV r1,#DynAreaFlags_PMP
GetPTE r4,4K,r4,r1
;
;here, r0 = page index into appslot, r1 = PPL, r3 = page number of page involved
[ LongDesc
; r4,r5 = new L3PT entry value to map in page
|
; r4 = new L2PT entry value to map in page
]
;
ADD r0,r0,#ApplicationStart:SHR:Log2PageSize ;address now in terms of pages from 0
[ LongDesc
[ LongDesc :LAND: ShortDesc
PTWhich r5
BNE %FT50
]
[ ShortDesc
GetPTE r4,4K,r4,r1,ShortDesc
LDR r5,=L2PT
STR r4,[r5,r0,LSL #2] ;update L2PT
[ LongDesc
B %FT60
50
]
]
[ LongDesc
GetPTE r4,4K,r4,r1,LongDesc
LDR r12,=LL3PT
ADD r12,r12,r0,LSL #3
STRD r4,[r12] ;update L3PT
|
LDR r5,=L2PT
STR r4,[r5,r0,LSL #2] ;update L2PT
]
60
]
;
LDR r5,=ZeroPage
LDR r5,[r5,#CamEntriesPointer]
......
......@@ -40,7 +40,11 @@ shrinkpages ROUT
Push "R5,R12"
SUB R5,R5,R1
MOV R7,#0
BL AMB_SetMemMapEntries_MapOut_Lazy
[ AMB_LazyMapIn
PTOp AMB_SetMemMapEntries_MapOut_Lazy
|
BL AMB_SetMemMapEntries_MapOut
]
Pull "R5,R12"
10
......
......@@ -17,7 +17,7 @@
; Convert given page flags to the equivalent temp uncacheable L2PT flags
; n.b. temp not used here but included for VMSAv6 compatibility
MACRO
GetTempUncache $out, $pageflags, $pcbtrans, $temp
GetTempUncache_ShortDesc $out, $pageflags, $pcbtrans, $temp
ASSERT $out <> $pageflags ; For consistency with VMSAv6 version
ASSERT $out <> $pcbtrans
[ "$temp" <> ""
......@@ -61,7 +61,7 @@ TempUncache_L2PTMask * L2_X+L2_C+L2_B
; r2, r3, r5, r7-r12 preserved
;
BangCamUpdate ROUT
BangCamUpdate_ShortDesc ROUT
TST r11, #DynAreaFlags_DoublyMapped ; if moving page to doubly mapped area
SUBNE r3, r3, r9 ; then CAM soft copy holds ptr to 1st copy
......@@ -122,7 +122,7 @@ BangCamUpdate ROUT
LDR r4, =DuffEntry ; check for requests to map a page to nowhere
TEQ r4, r3 ; don't actually map anything to nowhere
MOVEQ pc, lr
GetPTE r0, 4K, r0, r11
GetPTE r0, 4K, r0, r11, ShortDesc
LDR r1, =L2PT ; point to level 2 page tables
......@@ -155,7 +155,7 @@ BangL2PT ; internal entry point used only
LDR r4, =ZeroPage
BNE %FT20
LDR lr, [r4, #MMU_PCBTrans]
GetTempUncache r0, r11, lr
GetTempUncache_ShortDesc r0, r11, lr
LDR lr, [r1, r3, LSR #10] ;get current L2PT entry
BIC lr, lr, #TempUncache_L2PTMask ;remove current attributes
ORR lr, lr, r0
......@@ -205,19 +205,19 @@ PPLAccessARM6 ; EL1EL0
DCD -1
]
PPLTrans
PPLTrans_ShortDesc
& (AP_Full * L2_APMult) + L2_SmallPage ; R any W any
& (AP_Read * L2_APMult) + L2_SmallPage ; R any W sup
& (AP_None * L2_APMult) + L2_SmallPage ; R sup W sup
& (AP_ROM * L2_APMult) + L2_SmallPage ; R any W none
PPLTransX
PPLTransX_ShortDesc
& (AP_Full * L2X_APMult) + L2_ExtPage ; R any W any
& (AP_Read * L2X_APMult) + L2_ExtPage ; R any W sup
& (AP_None * L2X_APMult) + L2_ExtPage ; R sup W sup
& (AP_ROM * L2X_APMult) + L2_ExtPage ; R any W none
PPLAccess ; EL1EL0
PPLAccess_ShortDesc ; EL1EL0
; RWXRWX
GenPPLAccess 2_111111
GenPPLAccess 2_111101
......@@ -325,7 +325,7 @@ MMUC_modcon_readonly
; r3 -> PCBTrans
; Out:
; r0 = PTE for 4K page ("small page" or "extended page" depending on PPLTrans)
Get4KPTE ROUT
Get4KPTE_ShortDesc ROUT
Entry "r4"
AND lr, r1, #DynAreaFlags_APBits
LDR lr, [r2, lr, LSL #2]
......@@ -348,7 +348,7 @@ Get4KPTE ROUT
; As per Get4KPTE
; Out:
; r0 = PTE for 64K page ("large page")
Get64KPTE ROUT
Get64KPTE_ShortDesc ROUT
Entry "r4"
AND lr, r1, #DynAreaFlags_APBits
LDR lr, [r2, lr, LSL #2]
......@@ -380,7 +380,7 @@ Get64KPTE ROUT
; As per Get4KPTE
; Out:
; r0 = PTE for 1M page ("section")
Get1MPTE
Get1MPTE_ShortDesc
ALTENTRY
AND lr, r1, #DynAreaFlags_APBits
[ ARM6support
......@@ -413,7 +413,7 @@ Get1MPTE
; r2 = page flags
; or -1 if fault
; r3 = page size (bytes)
LoadAndDecodeL2Entry ROUT
LoadAndDecodeL2Entry_ShortDesc ROUT
LDR r1, =L2PT
LDR r0, [r1, r0, LSR #10]
ANDS r3, r0, #3
......@@ -481,7 +481,7 @@ LoadAndDecodeL2Entry ROUT
; or -1 if fault
; or -2 if page table ptr
; r3 = entry size/alignment (bytes)
LoadAndDecodeL1Entry
LoadAndDecodeL1Entry_ShortDesc
ALTENTRY
LDR r1, =L1PT
LDR r0, [r1, r0, LSR #20-2]
......@@ -521,7 +521,7 @@ LoadAndDecodeL1Entry
; TTBR and any other related registers updated
; If MMU is currently on, it's assumed the mapping of ROM+stack will not be
; affected by this change
SetTTBR ROUT
SetTTBR_ShortDesc ROUT
ARM_MMU_transbase r0
MOV pc, lr
......
......@@ -59,64 +59,6 @@ Init_ARMarch
MOV a1, a1, LSR #16
MOV pc, lr
; Called pre-MMU to set up some (temporary) PCBTrans and PPLTrans pointers,
; and the initial PageTable_PageFlags value
; Also used post-MMU for VMSAv6 case
; In:
; a1 -> ZeroPage
; Out:
; a1-a4, ip corrupt
Init_PCBTrans ROUT
LDR a2, =AreaFlags_PageTablesAccess :OR: DynAreaFlags_NotCacheable :OR: DynAreaFlags_NotBufferable
STR a2, [a1, #PageTable_PageFlags]
[ MEMM_Type = "VMSAv6"
[ LongDesc
ADRL a2, XCBTableVMSAv6Long
STR a2, [a1, #MMU_PCBTrans]
ADRL a4, PPLTrans
STR a4, [a1, #MMU_PPLTrans]
|
ADRL a2, XCBTableVMSAv6
STR a2, [a1, #MMU_PCBTrans]
; Use shareable pages if we're a multicore chip
; N.B. it's important that we get this correct - single-core chips may
; treat shareable memory as non-cacheable (e.g. ARM11)
ADRL a4, PPLTransNonShareable
; Look at the cache type register to work out whether this is ARMv6 or ARMv7+
MRC p15, 0, a2, c0, c0, 1 ; Cache type register
TST a2, #1<<31 ; EQ = ARMv6, NE = ARMv7+
MRC p15, 0, a2, c0, c0, 5 ; MPIDR
BNE %FT50
MRC p15, 0, a3, c0, c0, 0 ; ARMv6: MPIDR is optional, so compare value against MIDR to see if it's implemented. There's no multiprocessing extensions flag so assume the check against MIDR will be good enough.
TEQ a2, a3
ADDNE a4, a4, #PPLTransShareable-PPLTransNonShareable
B %FT90
50
AND a2, a2, #&c0000000 ; ARMv7+: MPIDR is mandatory, but multicore not guaranteed. Check if multiprocessing extensions implemented (bit 31 set), and not uniprocessor (bit 30 clear).
TEQ a2, #&80000000
ADDEQ a4, a4, #PPLTransShareable-PPLTransNonShareable
90
STR a4, [a1, #MMU_PPLTrans]
]
|
; Detecting the right PCBTrans table to use is complex
; However we know that, pre-MMU, we only use the default cache policy,
; and we don't use CNB memory
; So just go for a safe PCBTrans, like SA110, and the non-extended
; PPLTrans
ADRL a2, XCBTableSA110
STR a2, [a1, #MMU_PCBTrans]
ADRL a2, PPLTrans
[ ARM6support
ARM_6 a3
ADDEQ a2, a2, #PPLTransARM6-PPLTrans
]
STR a2, [a1, #MMU_PPLTrans]
]
MOV pc, lr
ARM_Analyse
MOV a2, lr
BL Init_ARMarch
......@@ -905,21 +847,20 @@ Analyse_WB_CR7_Lx
90
[ MEMM_Type = "VMSAv6"
; Reuse Init_PCBTrans
; Reuse Init_PCBTrans to set up PageTable_PageFlags, MMU_PPLAccess,
; MMU_PCBTrans, MMU_PPLTrans
MOV a1, v6
BL Init_PCBTrans
ADRL a1, PPLAccess
STR a1, [v6, #MMU_PPLAccess]
PTOp Init_PCBTrans
|
TST v5, #CPUFlag_ExtendedPages
ADRNEL a1, PPLTransX
ADREQL a1, PPLTrans
ADRNEL a1, PPLTransX_ShortDesc
ADREQL a1, PPLTrans_ShortDesc
[ ARM6support
ARM_6 lr
ADREQL a1, PPLTransARM6
]
STR a1, [v6, #MMU_PPLTrans]
ADRL a1, PPLAccess
ADRL a1, PPLAccess_ShortDesc
[ ARM6support
ADREQL a1, PPLAccessARM6
]
......@@ -4413,7 +4354,7 @@ XCBTableXScaleNoExt ; C+B CNB NCB N
[ MEMM_Type = "VMSAv6"
[ :LNOT: LongDesc
[ ShortDesc
; VMSAv6/v7 L2 memory attributes (short descriptor format, TEX remap disabled)
L2_SO_S * 0 ; Strongly-ordered, shareable
......@@ -4485,7 +4426,9 @@ XCBTableVMSAv6 ; C+B CNB NCB
DCW L2_Nrm_NC, L2_SO_S, L2_Nrm_NC, L2_SO_S ; X, X, X, X
DCW L2_Nrm_NC, L2_SO_S, L2_Nrm_NC, L2_SO_S ; X, X, X, X
|
]
[ LongDesc
; Attributes for long-descriptor page table format
; This gives the AttrIndx field of the low attributes
......
......@@ -323,7 +323,7 @@ CDS_PostService
; r11 = PPL + CB bits
Call_CAM_Mapping
Push "r0, r1, r4, r6, lr"
BL BangCamUpdate
PTOp BangCamUpdate
Pull "r0, r1, r4, r6, pc"
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......@@ -511,7 +511,7 @@ FindMemMapEntries_Code ROUT
; use the page tables to perform a logical -> physical (-> page no.) conversion
BL logical_to_physical ; r5 corrupt, r8,r9 = phys
PTOp logical_to_physical ; r5 corrupt, r8,r9 = phys
BLCC physical_to_ppn ; r5,r10-r11 corrupt, r3 = page
; If we found a page, double-check that the logical address is a match
; (means we can never find the second mapping of doubly-mapped regions
......@@ -566,7 +566,7 @@ SetMemMapEntries_Code ROUT
AND r0, r0, r6
BIC r11, r11, r6
ORR r11, r11, r0
BL BangCamUpdate
PTOp BangCamUpdate
B %BT01
02
Pull "r0-r6, r9, lr"
......@@ -913,7 +913,7 @@ DAC_roundup
BL AllocateAreaAddress ; in: r4 = flags, r5 = size of area needed; out: r3, or V=1, r0->error
BVS %BT25
40
BL AllocateBackingLevel2 ; in: r3 = address, r4 = flags, r5 = size; out: VS if error
PTOp AllocateBackingLevel2 ; in: r3 = address, r4 = flags, r5 = size; out: VS if error
BVS %BT25
41
......@@ -1923,71 +1923,11 @@ DynArea_SparseChange ; common entry point for claim and relea
BNE %BT10
ADD r3,r2,r3 ;stop address
;
[ LongDesc
LDR r5,=LL3PT
ADD r5,r5,r2,LSR #9 ;r5 -> L3PT for base (assumes 4k page)
MOV r8,r2 ;start address
;
;look for next fragment of region that needs to have mapping change
20
CMP r8,r3
BHS %FT50 ;done
LDRD r6,[r5],#8 ;pick-up next L3PT entry
CMP r4,#0 ;if operation is a release...
CMPEQ r6,#0 ;...and L3PT entry is 0 (not mapped)...
ADDEQ r8,r8,#&1000 ;...then skip page (is ok)
BEQ %BT20
CMP r4,#0 ;if operation is a claim (not 0)...
CMPNE r6,#0 ;...and L3PT entry is non-0 (mapped)...
ADDNE r8,r8,#&1000 ;...then skip page (is ok)
BNE %BT20
MOV r1,#&1000 ;else we need to do a change (1 page so far)
30
ADD r9,r8,r1
CMP r9,r3
BHS %FT40
LDRD r6,[r5],#8 ;pick-up next L3PT entry
CMP r4,#1 ;if operation is a release (not 1)...
CMPNE r6,#0 ;...and L3PT entry is non-0 (mapped)...
ADDNE r1,r1,#&1000 ;...then count page as needing change
BNE %BT30
CMP r4,#1 ;if operation is a claim...
CMPEQ r6,#0 ;...and L3PT entry is 0 (not mapped)...
ADDEQ r1,r1,#&1000 ;...then count page as needing change
BEQ %BT30
|
LDR r5,=L2PT
ADD r5,r5,r2,LSR #10 ;r5 -> L2PT for base (assumes 4k page)
MOV r8,r2 ;start address
;
;look for next fragment of region that needs to have mapping change
20
PTOp ScanSparse
CMP r8,r3
BHS %FT50 ;done
LDR r6,[r5],#4 ;pick-up next L2PT entry
CMP r4,#0 ;if operation is a release...
CMPEQ r6,#0 ;...and L2PT entry is 0 (not mapped)...
ADDEQ r8,r8,#&1000 ;...then skip page (is ok)
BEQ %BT20
CMP r4,#0 ;if operation is a claim (not 0)...
CMPNE r6,#0 ;...and L2PT entry is non-0 (mapped)...
ADDNE r8,r8,#&1000 ;...then skip page (is ok)
BNE %BT20
MOV r1,#&1000 ;else we need to do a change (1 page so far)
30
ADD r9,r8,r1
CMP r9,r3
BHS %FT40
LDR r6,[r5],#4 ;pick-up next L2PT entry
CMP r4,#1 ;if operation is a release (not 1)...
CMPNE r6,#0 ;...and L2PT entry is non-0 (mapped)...
ADDNE r1,r1,#&1000 ;...then count page as needing change
BNE %BT30
CMP r4,#1 ;if operation is a claim...
CMPEQ r6,#0 ;...and L2PT entry is 0 (not mapped)...
ADDEQ r1,r1,#&1000 ;...then count page as needing change
BEQ %BT30
]
;set up pseudo DA and do Batcall to change mapping of fragment we have found
40
MOV r2,SP ;temp DANode
......@@ -3083,7 +3023,7 @@ DynArea_PMP_LogOp ROUT
DebugTX "-> Map out"
]
ADD r4, r12, r4, LSL #12
BL logical_to_physical
PTOp logical_to_physical
MOVCS r5, #-1
BCS %FT10
Push "r3,r10-r11"
......@@ -3182,7 +3122,7 @@ DynArea_PMP_LogOp ROUT
SUBLO r1, r1, #4096
BICLO r6, r6, #PageFlags_Unsafe
; If there's nothing at the target address, increase our logical size
BL logical_to_physical
PTOp logical_to_physical
ADDCS r1, r1, #4096
BICCC r6, r6, #PageFlags_Unsafe
BCC %FT57
......@@ -3219,7 +3159,7 @@ DynArea_PMP_LogOp ROUT
LDRNE r7, [sp, #:INDEX:PMPLogOp_GlobalTLBFlushNeeded + 6*4 + 5*4]
TEQNE r7, #0
ORRNE r11, r11, #PageFlags_Unsafe
BL BangCamUpdate
PTOp BangCamUpdate
Pull "r2,r4,r6,r7,r10"
; If the above was unsafe, then it means the below can be unsafe too
AND r11, r11, #PageFlags_Unsafe
......@@ -3233,7 +3173,7 @@ DynArea_PMP_LogOp ROUT
[ PMPDebug
DebugReg r11, "Actual flags "
]
BL BangCamUpdate
PTOp BangCamUpdate
Pull "r2-r4,r6,r9,r11"
65
MOV r0, #0 ; Reinit LogOp_MapOut counters
......@@ -3346,73 +3286,46 @@ LogOp_MapOut ROUT
BEQ %FT10
; Work out if a global cache flush makes sense
MOV r8, r1
MOV r6, r0, LSL #12
MOV r2, r1
MOV r11, r0, LSL #12
ARMop Cache_RangeThreshold,,,r12
CMP r6, r0
SUBLS r6, r6, #1
CMP r11, r0
SUBLS r11, r11, #1
MOV r7, r3
LDR r12, [r12, #CamEntriesPointer]