From b85d7d81d8d76e95440b6db1c39399eaa6a8945b Mon Sep 17 00:00:00 2001
From: Stewart Brodie <sbrodie@gitlab.riscosopen.org>
Date: Wed, 2 Feb 2000 11:59:08 +0000
Subject: [PATCH] Added OS_ReadSysInfo 6, 7 and 8 from Ursula branch.
Ensured that M_Phoebe builds set UtilityModule version to 4.00
Detail:
The softload utility relies on the existence of the extra reason codes
to OS_ReadSysInfo introduced in Ursula. The main kernel now supports
these too (they are simply interfaces to read kernel capabilities and
configuration - eg. addresses and sizes of UND and SVC mode stacks)
Avoid OS_ReadSysInfo 9 - ROL have used it for reading the ROM personality
information (and it's not in our kernel)
Added some of the new macros into Copro15ops required by the ABT dump
area code (returned by OS_ReadSysInfo 7) and added the code into ARM600
to store abort information there.
Admin:
Required by softload utility for Ursula builds.
Tested on Risc PC.
Version 5.15. Tagged as 'Kernel-5_15'
---
Version | 17 ++++--
VersionASM | 8 +--
VersionNum | 14 ++---
s/ARM600 | 19 +++++++
s/Copro15ops | 16 ++++++
s/Middle | 143 ++++++++++++++++++++++++++++++++++++++++++++++++++-
6 files changed, 201 insertions(+), 16 deletions(-)
diff --git a/Version b/Version
index 13483313..c40caac2 100644
--- a/Version
+++ b/Version
@@ -1,19 +1,28 @@
; > Versions.Vicky
- GET VersionASM
+ GET VersionASM
GBLA Version
GBLS VString
GBLS Date
+ GBLA OSVersionID ;for OS_Byte 129
[ STB
-Version SETA Module_Version
-VString SETS Module_MajorVersion
-Date SETS Module_Date ; version for STB/NC OS
+Version SETA 452
+VString SETS "4.52"
+Date SETS "07 Nov 1996" ; version for STB/NC OS
+OSVersionID SETA &A6
+ |
+ [ M_Phoebe
+Version SETA 400
+VString SETS "4.00"
+Date SETS "02 Feb 2000" ; version for RISC OS on desktop computers
+OSVersionID SETA &A8 ; was &A7 for 3.70,3.71
|
Version SETA 371
VString SETS "3.71"
Date SETS "19 Feb 1997" ; version for RISC OS on desktop computers
]
+ ]
END
diff --git a/VersionASM b/VersionASM
index dc9fc3cb..efeb7717 100644
--- a/VersionASM
+++ b/VersionASM
@@ -6,9 +6,9 @@
GBLS Module_MinorVersion
GBLS Module_Date
GBLS Module_FullVersion
-Module_MajorVersion SETS "5.14"
-Module_Version SETA 514
+Module_MajorVersion SETS "5.15"
+Module_Version SETA 515
Module_MinorVersion SETS ""
-Module_Date SETS "27 Jan 2000"
-Module_FullVersion SETS "5.14"
+Module_Date SETS "02 Feb 2000"
+Module_FullVersion SETS "5.15"
END
diff --git a/VersionNum b/VersionNum
index 4055daae..3939f5a7 100644
--- a/VersionNum
+++ b/VersionNum
@@ -1,15 +1,15 @@
-/* (5.14)
+/* (5.15)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
-#define Module_MajorVersion_CMHG 5.14
+#define Module_MajorVersion_CMHG 5.15
#define Module_MinorVersion_CMHG
-#define Module_Date_CMHG 27 Jan 2000
+#define Module_Date_CMHG 02 Feb 2000
-#define Module_MajorVersion "5.14"
-#define Module_Version 514
+#define Module_MajorVersion "5.15"
+#define Module_Version 515
#define Module_MinorVersion ""
-#define Module_Date "27 Jan 2000"
+#define Module_Date "02 Feb 2000"
-#define Module_FullVersion "5.14"
+#define Module_FullVersion "5.15"
diff --git a/s/ARM600 b/s/ARM600
index 1d7069ed..ebaee4ee 100644
--- a/s/ARM600
+++ b/s/ARM600
@@ -3009,6 +3009,11 @@ PAbPreVeneer ROUT
; for the time being just merge lr and psr
mrs AL, r1, SPSR_all ; r1 = saved PSR
+
+ LDR r2, =Abort32_dumparea
+ STMIA r2, {r1,lr_abort} ;dump 32-bit PSR, fault address (PC)
+ STR lr_abort,[r2,#2*4] ;dump 32-bit PC
+
AND r2, r1, #&F0000003 ; get saved NZCV and 26 bit modes
ORR lr_abort, lr_abort, r2
AND r2, r1, #I32_bit + F32_bit ; extract I and F from new place
@@ -3050,6 +3055,10 @@ DAbPreVeneer ROUT
mrs AL, r1, CPSR_all ; r1 = CPSR
ADD r2, r13_abort, #8*4 ; r2 -> saved register bank for r8 onwards
+ LDR r4, =Abort32_dumparea+3*4 ;use temp area (avoid overwriting main area for expected aborts)
+ ARM_read_FAR r3
+ STMIA r4, {r0,r3,lr_abort} ; dump 32-bit PSR, fault address, 32-bit PC
+
MOV r4, lr_abort ; move address of aborting instruction into an unbanked register
BIC r1, r1, #&1F ; knock out current mode bits
ANDS r3, r0, #&1F ; extract old mode bits (and test for USR26_mode (=0))
@@ -3469,6 +3478,16 @@ DAbPreVeneer ROUT
90
+; copy temp area to real area (we believe this is an unexpected data abort now)
+
+ LDR r0, =Abort32_dumparea
+ LDR r1, [r0,#3*4]
+ STR r1, [r0]
+ LDR r1, [r0,#4*4]
+ STR r1, [r0,#4]
+ LDR r1, [r0,#5*4]
+ STR r1, [r0,#2*4]
+
; for the time being just merge lr and psr
LDR r0, [sp, #8*4] ; r0 = original SPSR (can't have been modified)
diff --git a/s/Copro15ops b/s/Copro15ops
index e76fce00..0b259c85 100644
--- a/s/Copro15ops
+++ b/s/Copro15ops
@@ -20,6 +20,8 @@
; 24-01-96 MJS Created
; 07-10-96 MJS Updated for proper ARM 810 support (not needed for RO 3.70)
+; 10-03-97 MJS A few additions for chocolate flavour screen handling (possible
+; Domain and FSR register use) in Phoebe OS
ARM_config_cp CP 15 ;coprocessor number for configuration control
@@ -27,6 +29,8 @@ ARM_ID_reg CN 0 ;processor ID
ARM_control_reg CN 1 ;control
ARM_tbase_reg CN 2 ;translation base (MMU)
ARM_domain_reg CN 3 ;domain access control (MMU)
+ARM_FSR_reg CN 5 ;Fault status reg (MMU, read only on ARM 6/7)
+ARM_FAR_reg CN 6 ;Fault address reg (MMU, read only on ARM 6/7)
ARM67_TLBflush_reg CN 5 ;TLB flush, ARMs 6 or 7
ARM67_TLBpurge_reg CN 6 ;TLB purge entry, ARMs 6 or 7
@@ -89,6 +93,18 @@ C15 CN 15
MCR$cond ARM_config_cp,0,$reg,ARM_control_reg,C0,0
MEND
+;read MMU fault status
+ MACRO
+ ARM_read_FSR $reg,$cond
+ MRC$cond ARM_config_cp,0,$reg,ARM_FSR_reg,C0,0
+ MEND
+
+;read MMU fault address
+ MACRO
+ ARM_read_FAR $reg,$cond
+ MRC$cond ARM_config_cp,0,$reg,ARM_FAR_reg,C0,0
+ MEND
+
;read ID register to register $id
;bits 15:12 of returned ID will be 0,7,8,10 for ARM 6,7,8,A
MACRO
diff --git a/s/Middle b/s/Middle
index c8d618c8..78d60602 100644
--- a/s/Middle
+++ b/s/Middle
@@ -1057,8 +1057,14 @@ ReadSysInfo_Code ROUT
CMP r0, #5
BCC %FT40 ; R0 = 4
BEQ %FT50 ; R0 = 5
+ CMP r0, #7
+ BCC %FT60 ; R0 = 6
+ BEQ %FT70 ; R0 = 7
+ CMP r0, #9
+ BCC %FT80 ; R0 = 8
+ ; R0 = 9 not allocated yet (BEQ %FT90)
- ; R0 > 5, so illegal value
+ ; R0 > 8, so illegal value
ADR r0, ErrorBlock_BadReadSysInfo
[ International
@@ -1410,6 +1416,141 @@ NVRAM_TAG_MACAddressChecksum
LDR r0, [r0, #RawMachineID+0]
ExitSWIHandler
+; OS_ReadSysInfo 6 - read kernel values (Acorn use only; eg. SoftLoad, ROMPatch)
+;
+; On entry: r0 = 6 (reason code)
+; r1 -> input block, 1 word per entry, giving number of value required, terminated by -1
+; OR: r1 = 0 if just 1 value is required, and this is to beturned in r2
+; r2 -> output block, 1 word per entry, will be filled in on output
+; OR: r2 = number of single value required, if r1 = 0
+;
+; On exit:
+; if r1 entry != 0:
+; r0,r1,r2 preserved
+; output block filled in, filled in value(s) set to 0 if unrecognised/no longer meaningful value(s)
+; if r1 entry = 0:
+; r0,r1 preserved
+; r2 = single value required, or set to 0 if if unrecognised/no longer meaningful value
+;
+; valid value numbers available - see table below
+;
+
+60
+ Push "r0-r3"
+ ADR r3,osri6_table
+ CMP r1,#0
+ BEQ %FT64
+62
+ LDR r0,[r1],#4
+ CMP r0,#-1
+ BEQ %FT66
+ CMP r0,#osri6_maxvalue
+ MOVHI r0,#0
+ LDRLS r0,[r3,r0,LSL #2]
+ STR r0,[r2],#4
+ B %BT62
+64
+ CMP r2,#osri6_maxvalue
+ MOVHI r2,#0
+ LDRLS r2,[r3,r2,LSL #2]
+ STR r2,[sp,#2*4]
+66
+ Pull "r0-r3"
+ ExitSWIHandler
+
+osri6_table
+ DCD CamEntriesPointer ;0
+ DCD MaxCamEntry ;1
+ DCD PageFlags_Unavailable ;2
+ DCD PhysRamTable ;3
+ DCD ARMA_Cleaner_flipflop ;4
+ DCD TickNodeChain ;5
+ DCD ROMModuleChain ;6
+ DCD DAList ;7
+ DCD AppSpaceDANode ;8
+ DCD Module_List ;9
+ DCD ModuleSHT_Entries ;10
+ DCD ModuleSWI_HashTab ;11
+ DCD IOSystemType ;12
+ DCD L1PT ;13
+ DCD L2PT ;14
+ DCD UNDSTK ;15
+ DCD SVCSTK ;16
+ DCD SysHeapStart ;17
+osri6_maxvalue * 17
+
+
+; OS_ReadSysInfo 7 - read 32-bit Abort information for last unexpected abort
+; (prefetch or data)
+;
+; On entry: r0 = 6 (reason code)
+;
+; On exit: r1 = 32-bit PC for last abort
+; r2 = 32-bit PSR for last abort
+; r3 = fault address for last abort (same as PC for prefetch abort)
+;
+70
+ Push "r0"
+ LDR r0, =Abort32_dumparea
+ LDR r1, [r0,#2*4]
+ LDR r2, [r0]
+ LDR r3, [r0,#4]
+ Pull "r0"
+ ExitSWIHandler
+
+; OS_ReadSysInfo 8 - Returns summary information on host platform.
+;
+; On entry:
+; r0 = 8 (reason code 8)
+;
+; On exit:
+; r0 = platform class
+; currently defined classes are:
+; 0 = unspecified platform (r1,r2 will be 0)
+; 1 = Medusa (currently returned for Risc PC only)
+; 2 = Morris (currently returned for A7000 only)
+; 3 = Morris+ (currently returned for A7000+ only)
+; 4 = Phoebe (currently returned for Risc PC 2 only)
+; all other values currently reserved
+; r1 = 32 additional platform specifier flags (if defined)
+; bits 0..31 = value of flags 0..31 if defined, 0 if undefined
+; r2 = defined status of the 32 flags in r1
+; bits 0..31 = status of flags 0..31
+; 0 = flag is undefined in this OS version
+; 1 = flag is defined in this OS version
+;
+; The current flag definitions for r1 (1=supported, 0=unsupported) are :
+;
+; 0 = Podule expansion card(s)
+; 1 = PCI expansion card(s)
+; 2 = additional processor(s)
+; 3 = auto power off
+; 4..31 reserved (currently undefined)
+;
+80
+ Push "r3-r5"
+ ADR r3, %86
+ MOV r4, #IOMD_Base
+ LDRB r4, [r4, #IOMD_ID0]
+82
+ LDR r5, [r3], #4
+ TEQ r5, #&80000000 ;terminator
+ TEQNE r5, r4
+ LDMEQIA r3, {r0-r2}
+ BEQ %FT84
+ ADD r3, r3, #3*4
+ B %BT82
+84
+ Pull "r3-r5"
+ ExitSWIHandler
+86
+ DCD IOMD_Original :AND: &FF, 1, &00000001, &0000000F
+ DCD IOMD_7500 :AND: &FF, 2, &00000001, &0000000F
+ DCD IOMD_7500FE :AND: &FF, 3, &00000001, &0000000F
+ DCD IOMD_IOMD2 :AND: &FF, 4, &0000000F, &0000000F
+ DCD &80000000, 0, 0, 0 ;terminator
+
+
LTORG
END
--
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