Commit b3b95b4b authored by Robert Sprowson's avatar Robert Sprowson

Move former ControlList_Interlaced item into SyncPol flags

ControlList_Interlaced is taken to have meant "output interlaced sync on H/V" and "configure DMA to show alternate lines in the framestore on alternate fields", therefore SyncPol flags mean:
b43
 00 = 'normal' progressive scan
 01 = interlaced sync, but both fields show the same image
 10 = (invalid)
 11 = interlaced sync, fields use alternate lines from the image

Version 6.21. Tagged as 'Kernel-6_21'
parent fc49beaf
......@@ -9,12 +9,12 @@
GBLS Module_ApplicationDate
GBLS Module_HelpVersion
GBLS Module_ComponentName
Module_MajorVersion SETS "6.20"
Module_Version SETA 620
Module_MajorVersion SETS "6.21"
Module_Version SETA 621
Module_MinorVersion SETS ""
Module_Date SETS "24 Jun 2019"
Module_ApplicationDate SETS "24-Jun-19"
Module_Date SETS "02 Jul 2019"
Module_ApplicationDate SETS "02-Jul-19"
Module_ComponentName SETS "Kernel"
Module_FullVersion SETS "6.20"
Module_HelpVersion SETS "6.20 (24 Jun 2019)"
Module_FullVersion SETS "6.21"
Module_HelpVersion SETS "6.21 (02 Jul 2019)"
END
/* (6.20)
/* (6.21)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
#define Module_MajorVersion_CMHG 6.20
#define Module_MajorVersion_CMHG 6.21
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 24 Jun 2019
#define Module_Date_CMHG 02 Jul 2019
#define Module_MajorVersion "6.20"
#define Module_Version 620
#define Module_MajorVersion "6.21"
#define Module_Version 621
#define Module_MinorVersion ""
#define Module_Date "24 Jun 2019"
#define Module_Date "02 Jul 2019"
#define Module_ApplicationDate "24-Jun-19"
#define Module_ApplicationDate "02-Jul-19"
#define Module_ComponentName "Kernel"
#define Module_FullVersion "6.20"
#define Module_HelpVersion "6.20 (24 Jun 2019)"
#define Module_LibraryVersionInfo "6:20"
#define Module_FullVersion "6.21"
#define Module_HelpVersion "6.21 (02 Jul 2019)"
#define Module_LibraryVersionInfo "6:21"
......@@ -55,7 +55,7 @@ ControlList_ExternalRegister # 1
ControlList_HClockSelect # 1
ControlList_RClockFrequency # 1
ControlList_DPMSState # 1
ControlList_Interlaced # 1 ; 1 = interlace sync, and adjust DMA so each field shows alternate rows from the framebuffer
# 1 ; Obsolete, see SyncPol b4
ControlList_OutputFormat # 1
ControlList_ExtraBytes # 1
ControlList_NColour # 1
......@@ -69,7 +69,9 @@ ControlList_Terminator * -1
SyncPol_InvertHSync * 1 ; 0 = positive, 1 = negative
SyncPol_InvertVSync * 2 ; 0 = positive, 1 = negative
SyncPol_InterlaceSpecified * 4 ; if set, interlace bit has been specified, else filled in by kernel
SyncPol_Interlace * 8 ; 0 = progressive sync, 1 = interlace sync (either specified by service call claimant or filled in from *TV by kernel). Note: Does not adjust DMA, so (with a static image) both fields are identical.
SyncPol_Interlace * 8 ; 0 = progressive sync, 1 = interlace sync (either specified
; by service call claimant or filled in from *TV by kernel).
SyncPol_InterlaceFields * 16 ; 0 = both fields are identical, 1 = adjust DMA so each field shows alternate rows
OPT OldOpt
......
......@@ -137,11 +137,11 @@ HandleServiceModeExtension ROUT
LDR r1, [lr, #VIDCList3_HorizDisplaySize]
CMP r1, r2
BNE %FT20
; Assume first control list item will be ControlList_Interlaced, and that it will only be present for interlaced modes
LDR r1, [lr, #VIDCList3_ControlList]
CMP r1, #ControlList_Interlaced
; Adjust vertical size when two distinct fields
LDR r1, [lr, #VIDCList3_SyncPol]
TST r1, #SyncPol_InterlaceFields
LDR r1, [lr, #VIDCList3_VertiDisplaySize]
MOVEQ r1, r1, LSL #1
MOVNE r1, r1, LSL #1
CMP r1, r4
BNE %FT20
; XRes, YRes check out. Now check framerate
......@@ -881,11 +881,11 @@ HandleServiceEnumerateScreenModes ROUT
BEQ %BT10
ADD r9, r9, r1 ; -> VIDC list
; Get X, Y, Hz
; Assume first control list item will be ControlList_Interlaced, and that it will only be present for interlaced modes
; Adjust vertical size when two distinct fields
LDR r10, [r9, #VIDCList3_ControlList]
CMP r10, #ControlList_Interlaced
TST r10, #SyncPol_InterlaceFields
LDR r10, [r9, #VIDCList3_VertiDisplaySize]
MOVEQ r10, r10, LSL #1
MOVNE r10, r10, LSL #1
LDR r11, [r9, #VIDCList3_HorizDisplaySize]
ORR r10, r10, r11, LSL #12
LDR r11, [r9, #-4]
......
......@@ -1214,19 +1214,21 @@ PushModeInfoCommonNoService
; Recalculate LineLength, ScreenSize based on the contents of the VIDC
; list
ADD R9, SP, #9*4 ; adjust for pushed registers
LDR R10, [R9, #wkwordsize + VIDCList3_SyncPol]
AND R10, R10, #SyncPol_Interlace :OR: SyncPol_InterlaceFields
TEQ R10, #SyncPol_Interlace :OR: SyncPol_InterlaceFields
MOVEQ R10, #1 ; true interlace with 2 interleaved fields
MOVNE R10, #0
LDR R2, [R9, #wkwordsize + VIDCList3_PixelDepth]
LDR R4, [R9, #wkwordsize + VIDCList3_HorizDisplaySize]
MOV R4, R4, LSL R2
ADD R4, R4, #7
MOV R4, R4, LSR #3
ADD R14, R9, #wkwordsize + VIDCList3_ControlList
MOV R10, #0
61
LDMIA R14!, {R7, R8}
CMP R7, #ControlList_ExtraBytes
ADDEQ R4, R4, R8
CMP R7, #ControlList_Interlaced
MOVEQ R10, R8
CMP R7, #ControlList_Terminator
BNE %BT61
STR R4, [R9, #wkLineLength]
......
......@@ -78,10 +78,10 @@ $label
& $vfpch ; front porch
;
& $pixrate ; pixel rate (kHz)
& sp ; sync polarity
[ "$int"<>""
& ControlList_Interlaced
& 1
& sp :OR: SyncPol_Interlace :OR: SyncPol_InterlaceFields
|
& sp ; sync polarity
]
& -1 ; terminator (no video control parameters)
......
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