diff --git a/OldTestSrc/A600tlb b/OldTestSrc/A600tlb
deleted file mode 100644
index 6481c8b3ae56a34333abc2a617bc3efe58a6a586..0000000000000000000000000000000000000000
--- a/OldTestSrc/A600tlb
+++ /dev/null
@@ -1,61 +0,0 @@
-;
-; A600tlb
-;
-; POST procedure for checking the TLB in A600 MMU.
-;
-; for each of level 1, level 2 small-page, level 2 large-page
-; construct page table
-; flush cache
-; start timer
-; for 32 addresses (with different mappings)
-; check address mapping
-; save timer
-; for same 32 addresses
-; check address mapping
-; compare test times (did 2nd test require table walk ?)
-
-
-
-
-
-Use a list of addresses that cover a good mixture of virtual addresses
-Build a page table that maps these to physical RAM addresses in various ways
-Access the addresses in such an order that the cache rotates, scrapping
-one entry each time through the list, and loading another. So each cache
-entry gets used 31 times, then is lost.
-Choice of physical mapping should ensure that the cache entries contain
-lots of different values of page and section base addresses.
-Choice of virtual test address should ensure that cache tag varies as
-widely as posible, too. PRBS ?
-Very widely varying values of cache tag require that a large number
-of mappings exist .. if these are 2-level mappings, that requires
-a lot of RAM. Page tables should be multiply-mapped.
-RISC OS puts lots of stuff below the 4M mark. Limits App space to 16M
-for backwards compatibility. Probably worth testing outside these
-limits to ensure Gold doesn't fall over, but failure rates would be
-very low.
-
-
-
-
-;
-; POST procedure for checking access faults (was PPL test)
-;
-; for each of level 1, level 2 small-page, level 2 large-page
-; construct page table
-; for user, supervisor mode
-; check address alignment fault
-; check section translation fault
-; check
-; check page translation fault
-; for 3 domain types
-; for 16 domains
-; check access permissions
-;
-
-
-
-;
-; POST procedure for checking IDC
-;
-;
diff --git a/OldTestSrc/Arm3 b/OldTestSrc/Arm3
deleted file mode 100644
index a385f75f4cbbd089f79c6ac394810fa1b4dd0109..0000000000000000000000000000000000000000
--- a/OldTestSrc/Arm3
+++ /dev/null
@@ -1,71 +0,0 @@
-; > TestSrc.ARM3
-
- TTL RISC OS 2+ POST ARM version determination
-;
-; Reads ARM3 version register, returns 0 if ARM 2 fitted.
-;
-;------------------------------------------------------------------------
-; History
-;
-; Date Name Comment
-; ---- ---- -------
-; 20-Apr-89 ArtG Initial version
-;
-;
-;------------------------------------------------------------------------
-
-A3Cid CN 0
-A3Cfls CN 1
-A3Cmod CN 2
-A3Ccac CN 3
-A3Cupd CN 4
-A3Cdis CN 5
-
-A3CON CP 15
-
-
-
-ts_ARM_type
- MOV r13,lr
-;
-; First, set up an undefined instruction vector to catch an ARM 2
-; (or a faulty ARM 3 ??) when the copro instruction is run.
-; Only applies on systems where ROM isn't mapped at zero.
-
- [ CPU_Type = "ARM2" :LOR: CPU_Type = "ARM3"
- MOV r0,#0 ; set a page at logical 0
- MOV r1,r0
- BL ts_set_cam
- ADR r0,ts_ARM_undefined
- LDMIA r0,{r2,r3}
- MOV r1,#4
- STMIA r1,{r2,r3} ; set the undefined instruction trap
- ]
-;
-; Read ARM3C0 version I.D.
-;
- MOV r0, #(-1) ; should always be altered
- MRC A3CON,0,r0,A3Cid,A3Cid ; Read control register 0
- MOV r12, r0
- [ CPU_Type = "ARM2" :LOR: CPU_Type = "ARM3"
- MOV r1,#0
- BL ts_set_cam_idle ; remove the vector page again
- ]
- MOVS r0, r12 ; return the ID (0 for ARM 2)
- MOV pc,r13
-
-;
-; Trap to be taken when ARM 2 is fitted
-;
-
-ts_ARM_undefined
- MOV r0,#0
- MOVS pc,r14_svc
-10
- ASSERT ((%10 - ts_ARM_undefined) / 4 = 2)
-
-
-
-
- END
-
diff --git a/OldTestSrc/Begin b/OldTestSrc/Begin
deleted file mode 100644
index b4b65b2d128da4c53e8184152d27393c5259a372..0000000000000000000000000000000000000000
--- a/OldTestSrc/Begin
+++ /dev/null
@@ -1,1428 +0,0 @@
-; > TestSrc.Begin
-
- TTL RISC OS 2+ Power-On Self-Test
-;
-; Startup code for RISC OS ROM Self-Test.
-;
-; Performs ROM test patterns, determines test strategy and enters
-; external or internal test code.
-;
-; A minimal set of opcodes should be used (ideally, only B, LDR and ADDS)
-; so that a processor test may be validly included in the internal test
-; sequence.
-;
-;------------------------------------------------------------------------
-; History
-;
-; Date Name Rel Comment
-; ---- ---- --- -------
-; 23-Feb-93 ArtG 2.00 Experimental ARM 600 / Jordan mods
-; 20-Oct-93 ARTG 2.02 Changed to new conditional assembly scheme
-;
-;------------------------------------------------------------------------
-
-; TS_STATUS should be one of :
-;
-; 'R' RISC OS POST
-; 'S' Standalone version (with a2 memory test instead of RISCOS)
-; 'T' Test build - development only
-;
-
-TS_STATUS * "R" ; Medusa POST version 2.0x
-;
-TS_RELEASE * 20
-TS_CHANGES * 4
-
-
- GBLL POSTenabled
-POSTenabled SETL {TRUE} ; don't permit POST for ordinary startup
-
-ts_Rom_bits * 21 ; Widest ROM address
-ts_Rom_length * 1 :SHL: ts_Rom_bits ; Longest ROM
-ts_highaddr_bit * 1 :SHL: 25 ; ARM address width
-ts_Alias_bits * (1 :SHL: 23) ; I/F output bits
-ts_recover_time * (1 :SHL: 8) ; inter-twiddle delay
-ts_pause_time * 200 ; Display pause time
-ts_S5_base * &3350000 ; IO register base address
-ts_IOEB_ID * (ts_S5_base + &50) ; IOE_B ASIC identification
-ts_IOEB_ident * &5 ; the value found there
-ts_PCaddress * &3010000 ; PC IO world base address
-ts_ReadyByte_00 * &90 ; signal 'Here I am' to ExtIO
-ts_BBRAM * &A0 ; IIC address of clock/ram chip
-ts_RamChunk * &2000 ; gap between data line tests
-ts_MaxRamTest * 4*1024*1024 ; Max. DRAM tested on normal reset
-ts_VIDCPhys * &3400000 ; Real location of VIDC
-
-;
-; Border colours used for self-test indicators
-;
- [ VIDC_Type = "VIDC1a"
-C_ARMOK * &40000000+&70C ; testing ROM
-C_RAMTEST * &40000000+&C70 ; testing RAM
-C_FAULT * &40000000+&00F ; failed tests
-C_PASSED * &40000000+&7C0 ; all passed
-C_WARMSTART * &40000000+&777 ; not tested
- ]
-
- [ VIDC_Type = "VIDC20"
-C_ARMOK * &40000000+&7000C0 ; testing ROM
-C_RAMTEST * &40000000+&C07000 ; testing RAM
-C_FAULT * &40000000+&0000F0 ; failed tests
-C_PASSED * &40000000+&70C000 ; all passed
-C_WARMSTART * &40000000+&707070 ; not tested
- ]
-
-;
-; Responses to external commands
-;
-
-ErrorCmd * &00FF
-
-
-;
-; Control bitmasks used to indicate results of test to RISCOS
-;
-
-R_SOFT * 0 ; not a power-on reset
-R_HARD * 1 ; Self-test run due to POR
-R_EXTERN * 2 ; external tests performed
-R_TESTED * 4 ; Self-test run due to test link
-R_MEMORY * 8 ; Memory has been tested
-R_ARM3 * &10 ; ARM 3 fitted
-R_MEMSKIP * &20 ; long memory test disabled
-R_IOEB * &40 ; PC-style IO controller
-R_VRAM * &80 ; VRAM present
-
-R_STATUS * &1ff ; bits that aren't a fault
-
-R_CHKFAILBIT * &100 ; CMOS contents failed checksum
-R_ROMFAILBIT * &200 ; ROM failed checksum
-R_CAMFAILBIT * &400 ; CAM failed
-R_PROFAILBIT * &800 ; MEMC protection failed
-R_IOCFAILBIT * &1000 ; IOC register test failed
-R_INTFAILBIT * &2000 ; Cannot clear interrupts
-R_VIDFAILBIT * &4000 ; VIDC flyback failure
-R_SNDFAILBIT * &8000 ; Sound DMA failure
-R_CMSFAILBIT * &10000 ; CMOS unreadable
-R_LINFAILBIT * &20000 ; Page zero RAM failure
-R_MEMFAILBIT * &40000 ; Main RAM test failure
-R_CACFAILBIT * &80000 ; ARM 3 Cache test failure
-;
- [ MorrisSupport
-Kludge * 96
- |
-Kludge * 0
- ]
- SUBT Exception vectors
-;
-; These vectors are available for use while the Rom is mapped into
-; low memory addresses. The Reset vector will be copied to low RAM
-; as part of a software reset sequence : therefore it must perform
-; a fixed operation to ensure compatibility with future versions
-; of RISC-OS.
-;
-
-Reset
-ts_start
- $DoMorrisROMHeader
-
- [ :LNOT: MorrisSupport
- [ ResetIndirected
- LDR pc,.+ResetIndirection ; load pc from vector at &118
- |
- B ts_RomPatt + PhysROM ; Jump to normal ROM space
- ]
- ]
-01
- & ts_Rom_length ; gets patched by ROM builder
-02
- & (ts_ROM_cvectors - ROM) ; pointer to code vector table
-03
- & (ts_ROM_dvectors - ROM) ; pointer to data vector table
-04
- & (ts_ROM_bvectors - ROM) ; pointer to branch table
- B Reset ; not currently used
- B Reset
- B Reset
-
-
-ts_ROMSIZE * %BT01 - ts_start
-ts_CVECTORS * %BT02 - ts_start
-ts_DVECTORS * %BT03 - ts_start
-ts_BVECTORS * %BT04 - ts_start
-
-;
-; Selftest version ID
-;
-
-00
- ASSERT %B00 <= (ts_start + &2c + Kludge)
- % ((ts_start + &2c + Kludge) - %B00)
-
-ts_ID & ((TS_STATUS :SHL: 24) + (TS_RELEASE :SHL: 16) + TS_CHANGES)
-
-ts_ID_text
-ts_himsg
- = "SELFTEST" ; **DISPLAY_TEXT**
- = &89 ; Cursor position
- = TS_STATUS
- = ("0" + (TS_RELEASE / 10))
- = "."
- = ("0" + (TS_RELEASE :MOD: 10))
- = ("0" + (TS_CHANGES :MOD: 10))
- = 0
-
-
-;
-; These vector tables permit access by the external (or downloaded) test
-; software to data and code in the POST modules.
-; Find the start of these tables through the 2nd and 3rd vectors at
-; the start of the ROM.
-;
-
-ts_ROM_dvectors
-01
- & ts_ID ; Selftest identification number
-02
- & (ts_ID_text - ROM) ; Selftest identification text
-
-
-;
-; vectors ORd with these flags to assure proper mode when
-; executed by host thro' vector table.
-;
-
-ts_runflags * (I_bit :OR: F_bit :OR: SVC_mode)
-
-ts_ROM_cvectors
- & ts_RomPatt :OR: ts_runflags
- & ts_User_startup :OR: ts_runflags
- & ts_Self_test_startup :OR: ts_runflags
- & ts_Dealer_startup :OR: ts_runflags
- & ts_Forced_startup :OR: ts_runflags
- & ts_GetCommand :OR: ts_runflags
- & ts_Softstart :OR: ts_runflags
- & ts_Hardstart :OR: ts_runflags
-
-
-;
-; ROM branch vectors - intended primarily so downloaded programs
-; may use standard subroutines. This table should be in a fixed place.
-;
-
-00
- ASSERT %B00 <= (ts_start + 128 + Kludge)
- % ((ts_start + 128 + Kludge) - %B00)
-
-ts_ROM_bvectors
- B ts_RomPatt
- B ts_GetCommand
- B ts_SendByte
- B ts_SendWord
- B ts_GetByte
- B ts_GetWord
- B ts_SendText
- B ts_MoreText
- B ts_SendLCDCmd
-
-
-;
-; Pad out until the location of the ResetIndirection vector
-;
-
- ASSERT .-ROM <= ResetIndirection
- % ResetIndirection-(.-ROM)
- & ts_RomPatt-ROM+PhysROM
-
-;
-; ROM test code
-;
-; Note : the register order in ADDS ...pc.. is often critical.
-; If we want to adjust pc, use ADDS pc,rn,pc so that the PSR is
-; rewritten with it's original value.
-; If we want to do some pc-relative arithmetic, use ADDS rn,pc,rn
-; so that the bits from PSR are NOT used in the address calculation.
-;
-
- SUBT Macros
-
- MACRO
- MODE $mode_bits
- TEQP psr,#($mode_bits :OR: I_bit :OR: F_bit)
- NOP
- MEND
-
- MACRO
- MOV_fiq $dest,$src
- MODE FIQ_mode
- MOV $dest,$src
- MODE SVC_mode
- MEND
-
- MACRO
- FAULT $code
- MODE FIQ_mode
- ORR r12_fiq,r12_fiq,$code
- MODE SVC_mode
- MEND
-
- MACRO
- M32_fiq $dest,$src,$tmp1,$tmp2
- SetMode FIQ32_mode,$tmp1,$tmp2
- MOV $dest,$src
- msr AL,CPSR_all,$tmp2
- MEND
-
- MACRO
- FAULT32 $code,$tmp
- SetMode FIQ32_mode,$tmp
- ORR r12_fiq,r12_fiq,$code
- SetMode SVC32_mode,$tmp
- MEND
-
-;
-; Define an area of storage with the required set of data bus patterns
-; These are used both for testing the complete width of the data bus
-; during ROM pattern testing, and will provide a tidy set of patterns
-; if the reset is held, while the ARM increments addresses.
-;
-
- SUBT ROM Address and Data Patterns
-
-DataPatterns
-
- GBLA dmask
-dmask SETA &80000000
-
- DCD &FFFFFFFF ; first two : all set
- DCD &0 ; all clear
-
- GBLA OldOpt ; don't list all the walking
-OldOpt SETA {OPT} ; patterns
- OPT OptNoList
-
- WHILE dmask > 0 ; then for each bit
- DCD &$dmask ; set it
- DCD :NOT: &$dmask ; and clear it
-dmask SETA dmask :SHR: 1
- WEND
- OPT OldOpt
-DEnd
-
-
- OPT OptList
-;
-;
-; Read the ROM at a series of addresses
-; such that : a) all the address lines are exercised individually
-; b) all the data lines are exercised individually
-;
-; Data and address lines are exercised as walking-0 and walking-1.
-; The test is performed as a series of LDR operations to avoid using
-; a larger instruction set.
-;
-
-ts_RomPatt ROUT
-
- ; Patterns which will exercise most of the data bus.
- ; All are arbitrary instructions with NV execution
-
- DCD &F0000000 ; walking 1
-
-OldOpt SETA {OPT} ; patterns
- OPT OptNoList
-
-dmask SETA &08000000
- WHILE dmask > 0
- DCD dmask :OR: &F0000000
-dmask SETA dmask :SHR: 1
- WEND
-
- DCD &FFFFFFFF ; walking 0
-
-dmask SETA &08000000
- WHILE dmask > 0
- DCD (:NOT: dmask) :OR: &F0000000
-dmask SETA dmask :SHR: 1
- WEND
-
- OPT OldOpt
-
- ; Now some proper code :
- ; Initialise address pointer and make MemC safe
-
- LDR r0,%01
- ADD pc,r0,pc
-01
- & 0 ; useful constant
-
- [ IO_Type = "IOC-A1" ;;!! unsafe if we execute ROM at zero
- LDR r1,%02
- ADD pc,r0,pc
-02 ;;!! This remaps MEMC's ROM
- & &E000C :OR: MEMCADR ;;!! addressing if it hasn't
- STR r1,[r1] ;;!! already happened.
- ]
-
- LDR r5,%03 ; Load r5 with a constant which
- ADD pc,r0,pc ; may be added to ROM plus a
-03 ; walking-zero bitmask to create
- & ts_Rom_length - 3 ; a valid word address in ROM.
- LDR r2,%04 ; Offset from ROM start to here
- ADD pc,r0,pc
-04
- & ROM - pcfromstart
-
- ADD r2,pc,r2 ; pointer to start of ROM
- ADD r3,r2,r0 ; pointer to start of ROM
-pcfromstart
- ADD r4,r2,r0 ; pointer to start of ROM
-
- ; assembly-time loop - only 32 iterations required
-
-OldOpt SETA {OPT}
-
- GBLA doffset
-doffset SETA DataPatterns
- WHILE doffset < DEnd
-
- LDR r0,doffset ; walking 1 data pattern
- LDR r1,doffset+4 ; walking 0 data pattern
- LDR r6,[r2] ; walking 1 address pattern
- LDR r6,[r3] ; walking 0 address pattern
-
- [ (doffset - DataPatterns) > ((32 - ts_Rom_bits) * 8)
- [ (doffset - DataPatterns) < (31 * 8)
- ADD r2,r4,r0 ; r2 = ROM + walking 1 pattern
- ADD r3,r4,r1 ; r3 = ROM + walking 0 pattern
- ADD r3,r3,r5 ; adjust to a valid address
- ]
- ]
-
- OPT OptNoList
-
-doffset SETA doffset + 8
- WEND
-
- ASSERT (. - doffset < 4095) ; in range without barrel shift ?
-
- OPT OldOpt
-
-;
-; External interface drivers -
-; provides entry points to send byte- and word- and string-sized objects
-; and to receive byte- and word-sized objects
-;
-; Continue into GetCommand, which determines adapter type (or no adapter)
-; and jumps to an ExtCmd handler, ts_User_startup, ts_Forced_startup or
-; ts_Dealer_startup as appropriate.
-;
- B ts_GetCommand
-
- GET TestSrc.ExtIO
-
-;
-; External command handlers - respond to commands given through the
-; external test interface.
-;
-
- GET TestSrc.ExtCmd
-
-
- SUBT Selftest
-;
-; There is no attached test interface. Is this a power-on reset ?
-; Addressing IOC will make MEMC1a remap the ROM to high memory if
-; it hasn't already done it, so be careful to ensure that the
-; ARM is addressing normally-addressed ROM when this code runs.
-;
-
-ts_User_startup ROUT
- LDR r0,%01
- ADD pc,r0,pc
-01
- & 0
-;
-; IOMD will only access the ROM until a write to IOMD has been made -
-; make this write also switch on refresh so the DRAM has a chance to
-; get running before the memory test starts.
-;
- [ MEMC_Type = "IOMD"
- LDR r1,%02
- ADD pc,r0,pc
-02
- & (IOMD_Base+IOMD_VREFCR)
- LDR r2,%03
- ADD pc,r0,pc
-03
- & IOMD_VREFCR_REF_16
- STR r2, [r1,#0]
- ]
-
- [ POSTenabled
- LDR r1,%12 ; load address of IOC IRQ register
- ADD pc,r0,pc
-12
- & IOC+IOCIRQSTAA
-
- LDR r1, [r1,#0] ; Get IRQSTAA register (hence POR bit)
- LDR r2, %13
- ADD pc,r0,pc ; Constant to shift por to bit 31
-13
- & por_bit :SHL: 1
-14 ADD r1,r1,r1
- ADDS r2,r2,r2
- BCC %14 ; loop until por_bit is at bit 31
- ADDS r1,r1,r1 ; then shift it into carry
- BCC ts_Self_test_end ; POR bit clear - do soft reset.
-
-; it's a power-on reset, so assume we can't be in 32-bit mode
-
- MOV_fiq r12_fiq, #R_HARD
- B ts_Self_test_startup
- |
- B CONT ; if user POST disabled
- ]
-;
-; Perform self - tests
-;
-; Any distinction between test operation for Power-up, Display-only
-; and Forced tests needs to be made between these three entry points.
-;
-
-
-; This is where tests start if a dumb test link is fitted
-; (a diode from A21 to *ROMCS, disabling the ROMs when A21 is high)
-
-ts_Forced_startup ROUT
-
- MOV_fiq r12_fiq, #R_TESTED
- B ts_Self_test_startup
-
-; This is where the tests start if an external display adapter is fitted
-
-ts_Dealer_startup ROUT
-
- MOV_fiq r12_fiq, #R_EXTERN
-
- LDR r4,%FT02 ; make a pointer to signon string
-01 ADD r4,pc,r4
- ADD pc,r0,pc
-02
- & (ts_himsg - %BT01 - 8)
-
- ADD r14,pc,r0 ; make a return address for this 'call'
- ASSERT (.+4 = ts_Self_test_startup) ; PC must point there already !
- B ts_SendText
-
-ts_Self_test_startup ROUT
-
-; This is where the power-on test starts (every user gets this)
-
-
-;
-; Processor test would go here .... if there was one.
-;
-
-;
-; From this point on we assume we can safely use all the processor
-;
-; Initialise VIDC : Sync mode 0, border covers screen
-;
-
-ts_InitVIDC
- [ IO_Type = "IOMD" ; If POSTbox fitted, ROM may still be mapped everywhere
- MOV r2,#IOMD_Base
- MOV r0, #IOMD_VREFCR_REF_16 ; switch on DRAM refresh
- STR r0, [r2, #IOMD_VREFCR]
-
- ; choose monitor settings from ID bit 0
- MOV r1,#ts_VIDCPhys
- ADRL r2,TestVIDCTAB
- LDR r0,=IOMD_MonitorType
- LDR r0,[r0]
- ANDS r0,r0,#IOMD_MonitorIDMask
- ADDEQ r2,r2,#(TestVVIDCTAB-TestVIDCTAB)
-
- | ; not IOMD
- MOV r1,#ts_VIDCPhys
- ADRL r2,TestVIDCTAB
- ]
-
-10 LDR r0, [r2],#4
- CMP r0, #-1
- STRNE r0, [r1]
- BNE %BT10
-
- LDR r0,=C_ARMOK ; set initial screen colour
- STR r0, [r1]
-
- B ts_RomTest
-
-
- LTORG
- ROUT
-
-;
-; Calculate ROM checksum : display status and calculated checksum.
-;
-
-1
- = "ROM :",0
-2
- = "ROM bad",&88,&ff,&ff,&ff,&ff,&ff,&ff,&ff,&ff,0
-3
- = "ROM size",&8A,&ff,&ff,&ff,&ff,&ff,&ff,0
- ALIGN
-
-ts_RomTest
- ADR r4,%BT1
- BL ts_SendText
-
- BL ts_ROM_checksum
- BEQ %20
- ADR r4,%BT2 ; Failed message
- FAULT #R_ROMFAILBIT ; set ROM bit in r12_fiq
- MOV r8,r0 ; calculated checksum
- BL ts_SendText
-
- BL ts_ROM_alias ; Checksum failed :-
- ADR r4,%BT3 ; hunt for first alias
- MOV r8,r0, LSL #8
- BL ts_SendText ; and report it.
-20
-
- [ IO_Type = "IOC-A1" ; Don't use RISC OS MemSize
- ; until much later - it sets up
- ; the ARM600 MMU as well.
- B ts_MEMCset
-
-;
-; Do MEMC setup and memory size determination (the first time).
-;
- LTORG
- ROUT
-
-1
- = "M Size :",0
-2
- = "M Size",&89,&ff,&ff,&ff,&ff,".",&ff,&ff,0
- ALIGN
-
-ts_MEMCset
- MOV r12,#0
- ADR r4,%BT1
- BL ts_SendText
- LDR r1,=(&E000C :OR: MEMCADR) ; MemSize expects 32k page
- STR r1,[r1]
- BL MemSize
-
-;
-; MemSize returns with r0 = page size (now in bytes, *NOT* in MEMC control patterns),
-; r1 = memory size (in bytes)
-; r2 = MEMC control value
-;
-; Translate these into a number that looks like :
-;
-; mmmm.pp
-;
-; where mmmm is memory size in hex Kbytes, pp is page size in hex Kbytes.
-;
- MODE FIQ_mode ; Save memory size and
- MOV r11_fiq,r2 ; MEMC setup value for
- MOV r10_fiq,r1 ; later use
- MODE SVC_mode
-
- MOV r8, r0, LSR #2 ; MemSize now returns actual page size in r0
- ADD r8,r8,r1,LSL #6
- ADR r4,%BT2
- BL ts_SendText
-
- ]
-
-;
-; Test data, address and byte strobe lines.
-; On MEMC systems, this calls MemSize and tests the memory that finds.
-; On IOMD systems, memory sizing is performed along with the data line
-; tests, and that result is used for address line testing.
-;
-
- B ts_LineTest
-
- GBLS tsGetMem1
-tsGetMem1 SETS "GET TestSrc.Mem1" :CC: MEMC_Type
- $tsGetMem1
-
-;
-; Test IOC.
-; This shuld require vector space to work (for testing interrupts),
-; but the current version just reports the status register contents.
-;
-; Display is ccaabbff
-;
-; where cc is the control register
-; aa is IRQ status register A
-; bb is IRQ status register B
-; ff is FIQ status register
-;
-
- B ts_IOCTest
-
- LTORG
- ROUT
-
- [ IO_Type = "IOMD"
-1
- = "IOMD :",0
-2
- = "IOMD-F",&88,&ff,&ff,&ff,&ff,&ff,&ff,&ff,&ff,0
-3
- = "IOMD-V"
-4
- = &88,&ff,&ff,&ff,&ff," V.",&ff,0
- |
-1
- = "IOC :",0
-2
- = "IOC-F",&88,&ff,&ff,&ff,&ff,&ff,&ff,&ff,&ff,0
-3
- = "IOC"
-4
- = &88,&ff,&ff,&ff,&ff,&ff,&ff,&ff,&ff,0
- ]
- ALIGN
-
-ts_IOCTest
- ADR r4,%BT1
- BL ts_SendText
- BL ts_IOCreg ; check register integrity
- BEQ %FT8
- ADR r4,%BT2
- BL ts_SendText ; report if failure
-
- FAULT #R_IOCFAILBIT
-8
- ADR r4,%BT1
- BL ts_SendText
- BL ts_IOCstat
- BEQ %FT10 ; fail message only printed if
- ADR r4,%BT3 ; ID code unrecognised
- BL ts_SendText
- FAULT #R_IOCFAILBIT ; .. and set error bit if IOMD code is wrong
- B %FT11
-10
- ADR r4,%BT4 ; print the status value
- BL ts_MoreText
-11
-
- [ IO_Type = "IOMD"
- B ts_CMOStest
- |
- B ts_IOEBtest
- ]
-
- LTORG
- ROUT
-
-;
-; Check for presence of IOEB ASIC
-;
-
- [ IO_Type = "IOEB"
-
-1
- = "IOEB :",0
-2
- = "IOEB",&88,"exists",0
-
-
- ALIGN
-
-ts_IOEBtest
- ADR r4,%BT1
- BL ts_SendText
-
- LDR r0,=ts_IOEB_ID ; read an ID register in the IOEB ASIC
- LDRB r0, [r0]
- AND r0, r0, #&f
- CMPS r0, #ts_IOEB_ident ; if it looks right ( == 5) ..
- BNE %10
-
- FAULT #R_IOEB ; set that bit in the result word
- ADR r4, %BT2
- BL ts_SendText
-10 B ts_CMOStest
- ] ; IOEB IO world
-;
-; Read CMOS
-; Check the checksum, read the memory test flag.
-;
-
-1
- = "SRAM :",0
-2
- = "SRAM-F",0
-3
- = "SRAM-C",&8e,&ff,&ff,0
- ALIGN
-
-ts_CMOStest
- ADR r4,%BT1
- BL ts_SendText
-
- [ ChecksumCMOS
-
- LDR r0,=(ts_BBRAM + &4000)
- MOV r1,#&C0 ; Get first RAM area
- MOV r2,#CMOSxseed
- BL ts_CMOSread
- BNE %20
- MOV r2, r0
- LDR r0,=(ts_BBRAM + &1000) ; Accumulate the second RAM area
- MOV r1,#&2F
- BL ts_CMOSread
- BNE %20
- RSB r2, r0, #0 ; Subtract from the checksum byte
- LDR r0,=(ts_BBRAM + &3F00)
- MOV r1,#1
- BL ts_CMOSread
- BNE %20
- MOV r8, r0, LSL #24
- ANDS r0, r0, #&FF ; A zero result ?
- MOV r1, #R_CHKFAILBIT
- ADR r4,%BT3 ; Report checksum failure
- BNE %21 ; failed .. report error
- ] ; end ChecksumCMOS
-
- LDR r0,=(ts_BBRAM + &FC00) ; Read Misc1CMOS byte
- MOV r1,#1
- MOV r2,#0
- BL ts_CMOSread
- BNE %20
- ANDS r0,r0,#&80 ; Test the memory-test-disable bit
- BEQ %25
- FAULT #R_MEMSKIP ; If set, skip the memory test
- B %25
-
-20
- MOV r1,#R_CMSFAILBIT ; Real fault - set the fault bit
- ADR r4,%BT2 ; Report fault accessing IIC
- ; (Bitmap & POST display)
-21
- FAULT r1
- BL ts_SendText ; Report one fault or another
-25
- B ts_IOinit
-
- LTORG
- ROUT
-;
-; Initialize various machine registers - e.g, turn off the floppy
-; drive, etc, etc.
-;
-
-1
- = "IOinit:",0
- ALIGN
-
-ts_IOinit
- ADR r4,%BT1
- BL ts_SendText
- ADRL r2,ts_IOinitab
-10
- LDR r0,[r2],#4 ; Get address
- LDR r1,[r2],#4 ; Get initialization data
- CMPS r0,#(-1)
- STRNE r1,[r0] ; write to IO port
- BNE %10
- B Speedset
-;
-; Use the RISC OS MEMC setup code to guess the proper processor / memory
-; configuration. The memory speed can then be set up correctly for
-; fastest possible working, and the memory array tested in the
-; configuration RISC OS expects.
-;
-; Display the results of the TimeCPU test as :
-;
-; ssss.m.r
-;
-; where ssss is the processor speed in hex kHz,
-; m is 0 for MEMC, 1 for MEMC1a
-; r is the MEMC rom speed switch setting.
-;
- ROUT
-
-1
- = "Speed :",0
-2
- = "Speed",&88,&ff,&ff,&ff,&ff,".",&ff,".",&ff,0
-
- ALIGN
-
-Speedset
- ADR r4,%BT1
- BL ts_SendText
-
- [ MEMC_Type = "IOMD"
- MOV r9,#0
- |
- MOV_fiq r0, r11_fiq ; get MEMC setup
- MOV r9,r0 ; compare IOC and CPU clocks
- ]
-
- BL TimeCPU
- MOV r0,r9
- MOV_fiq r11_fiq,r0
-
- MOV r8,r7,LSL #16
- TST r7, #1 :SHL: 16 ; test bit 16 of r7 :
- ADDNE r8,r8,#&1000 ; MEMC1 / MEMC1a detected
- AND r9,r9,#&C0 ; get High ROM access bits
- ADD r8,r8,r9, LSL #2
- ADR r4,%BT2
- BL ts_SendText
- B RAMtest
-
-
-;
-; Long RAM test, ideally exercising all memory.
-; In order to keep boot time short, the following scheme is used :
-;
-; Normal power-on boot - test VRAM and up to 4M of first DRAM entry
-; CMOS disable set - test nothing
-; Test hardware fitted - test entire memory
-;
-
- ROUT
-
-
-1
- = "RAM :",0
-2
- = "RAM bad",&88,&ff,&ff,&ff,&ff,&ff,&ff,&ff,&ff,0
-3
- = &89,"skipped",0
-4
- = "RAM :",&88,&ff,&ff,&ff,&ff,&ff,&ff,&ff,&ff,0
-
-
- ALIGN
-
-RAMtest
- ADR r4,%BT1
- BL ts_SendText
-;
-; if (R_MEMSKIP && R_HARD)
-; skip all the remaining tests
-; if (!R_LINFAILBIT)
-; perform the long memory test
-;
- MOV_fiq r0,r12_fiq ; skip this test if data line fault
- AND r1,r0,#(R_MEMSKIP :OR: R_HARD) ; or the user didn't want it
- TEQS r1,#(R_MEMSKIP :OR: R_HARD)
- ANDNE r1,r1,#R_LINFAILBIT
- TEQNE r1,#R_LINFAILBIT
- BNE %12
- ADR r4,%BT3 ; skipping memory test ....
- BL ts_MoreText
- B ts_Report
-12
- LDR r1,=C_RAMTEST ; doing at least part of the long memory test
- LDR r0,=ts_VIDCPhys ; write the border colour
- STR r1,[r0]
-
- BL MemSize ; Set MMU up, mapping (some) RAM at logical address 0
- ; Note that this returns with the MMU enabled,
- ; the ROM remapped to it's ORGed address,
- RSB r4,r4,#PhysROM ; and r4 the offset from physical to ORGed ROM addresses
- ADD r4,r4,#PhysSpace
- SetMode SVC32_mode,r0 ; Must do this, as PhysSpace is outside 26 bit addressing
- ADD pc,pc,r4 ; Jump into the ROM at its image in PhysSpace
- NOP ; this instruction skipped by pc adjustment
-
-;
-; Modify the PhysRamTable so only VRAM and the first ts_MaxRamTest of DRAM gets tested
-;
- M32_fiq r0,r12_fiq,r1,r2 ; get the test condition flags
-
- ANDS r0,r0,#(R_EXTERN :OR: R_TESTED)
- BNE %FT16 ; do full test if test adapter is present
- MOV r9,#PhysRamTable
- ADD r10,r9,#(PhysRamTableEnd-PhysRamTable)
-14
- LDR r1,[r9, #4]
- ADD r0,r0,r1 ; r0 = running sum of memory sizes
- SUBS r2,r0,#ts_MaxRamTest ; r2 = excess over ts_MaxRamTest
- SUBHI r1,r1,r2 ; r1 = current size truncated
- STRHI r1,[r9, #4]
- MOVHI r0,#ts_MaxRamTest ; truncate running sum to MaxRamTest
-
- ADD r9,r9,#(DRAMPhysAddrB-DRAMPhysAddrA)
- CMPS r9,r10
- BNE %BT14
-16
- FAULT32 #R_MEMORY,r0 ; memory tests were attempted
-
- MOV r9,#VideoPhysAddr
- LDR r8,[r9] ; report the test address
- ADRL r4,%BT4
- BL ts_SendText
- LDR r0,[r9] ; get VRAM start address and size
- LDR r1,[r9,#4]
- ADD r0,r0,#PhysSpace
- BL ts_RamTest
- BNE %FT20 ; failed - abort ram testing
-
-;
-; VRAM (or 1st MB of DRAM, if no VRAM fitted) looks OK - move the translation
-; table there so memory tests can proceed without smashing it.
-;
- MOV r9,#PhysRamTable
- LDR r0,[r9,#VideoPhysAddr-PhysRamTable] ; get address of video RAM
- LDR r1,[r9,#DRAMPhysAddrA-PhysRamTable] ; get address of 1st DRAM bank
- LDR r3, =DRAMOffset_L2PT
- ADD r1, r1, r3 ; make r1 -> L2PT
- ADD r0, r0, r3 ; make r0 -> temporary L2PT
- BL ts_remap_ttab ; copy ttab at r1 to r0 and change table base
-
-;
-; Now run the RAM test at each DRAMPhysAddr until the end of the table or a zero entry
-; is reached. Mark tested entries by setting the PhysSpace address, so a pointer to the
-; next entry need not be kept.
-;
-18
- MOV r9,#DRAMPhysAddrA
- ADD r10,r9,#(PhysRamTableEnd-DRAMPhysAddrA)
-19
- CMPS r9,r10 ; reached end of table ?
- LDRNE r0,[r9]
- TSTNE r0,r0 ; reached unused entries ?
- LDRNE r1,[r9,#4] ; or blanked-out entries ?
- TSTNE r1,r1
- BEQ %FT21 ; .. all passed OK
- TSTS r0,#PhysSpace
- ADDNE r9,r9,#(DRAMPhysAddrB-DRAMPhysAddrA)
- BNE %BT19 ; this entry done .. find the next
-
- MOV r8,r0 ; report address of this block
- ADRL r4,%BT4
- BL ts_SendText
-
- LDR r0,[r9] ; start testing it
- ADD r0,r0,#PhysSpace
- LDR r1,[r9, #4]
- STR r0,[r9] ; mark block so it isn't retested
- MOV r2,#PhysRamTable
- LDMIA r2,{r3-r14} ; save the PhysRamTable
- STMIA r0,{r3-r14}
- BL ts_RamTest
- LDMIA r13,{r1-r11,r14} ; restore the PhysRamTable
- MOV r13,#PhysRamTable
- STMIA r13,{r1-r11,r14}
- BEQ %BT18 ; if it passed, go look for another block
-
-20
- FAULT32 #R_MEMFAILBIT,r2 ; failed - report fault address
- ADRL r4,%BT2
- MOV r11,r1 ; Save failed data
- MOV r8,r0 ; first failing address
- BL ts_SendText
- MOV r4,r12 ; get fault message
- MOV r8,r11 ; and fault data
- BL ts_SendText
-21
-
- [ MEMM_Type = "MEMC1"
-
-;
-; Test the CAMs - for each fitted MEMC, go through all the CAM entries
-; remapping logical memory and testing against physical correspondence.
-; Then try out the protection bits in each CAM entry and various
-; processor modes.
-; These tests return pointers to their own fault report strings.
-;
- B ts_CAMtest
- ROUT
-1
- = "CAMs :",0
-2
- = "PPLs :",0
-3
- = &89,"skipped",0
- ALIGN
-
-ts_CAMtest
- LDR r4,=%BT1
- BL ts_SendText
-
- MOV_fiq r0,r12_fiq ; skip this test if memory fault
- MOV r1,#(R_LINFAILBIT :OR: R_MEMFAILBIT)
- ANDS r0,r0,r1
- BEQ %08
- LDR r4,=%BT3
- BL ts_MoreText
- B %20
-
-08
- BL ts_CAM
- BEQ %10
- BL ts_SendText
- FAULT #R_CAMFAILBIT
-10
- LDR r4,=%BT2
- BL ts_SendText
-
- MOV_fiq r0,r12_fiq ; skip this test if memory fault
- MOV r1,#(R_LINFAILBIT :OR: R_MEMFAILBIT)
- ANDS r0,r0,r1
- BEQ %18
- LDR r4,=%BT3
- BL ts_MoreText
- B %20
-18
- BL ts_memc_prot
- BEQ %20
- BL ts_SendText
- FAULT #R_PROFAILBIT
-20
-
- ]
-
-;
-; After testing memory and translation, turn MMU off again before running remainder
-; of tests. This simplifies finishing up (where system must be put back into 26-bit
-; mode before initialising RISCOS) if memory tests were deselected.
-; Take care to poke the real translation table - it's been relocated to video
-; RAM during the memory tests.
-;
-
-ts_restore_physical
- MOV r5, pc ; obtain current address
- SUB r5, r5,#PhysSpace ; adjust to point to unmapped version
- MOV r5, r5, LSR #20 ; divide by 1MB
- MOV r7, r5, LSL #20 ; r7 = physical address of base of section
- ORR r7, r7, #(AP_None * L1_APMult)
- ORR r7, r7, #L1_Section
- MOV r3, #VideoPhysAddr ; find the copied translation table
- LDR r3, [r3]
- ADD r3, r3, #PhysSpace
- ADD r3, r3, #DRAMOffset_L1PT
- STR r7, [r3, r5, LSL #2] ; store replacement entry in L1 (not U,C or B)
-
- SetCop r7, CR_IDCFlush ; flush cache + TLB just in case
- SetCop r7, CR_TLBFlush ; (data written is irrelevant)
-
-; The ROM should now be mapped at the present address less PhysSpace, which is where it
-; would be if the MMU were turned off.
-
- MOV r4,#PhysSpace
- SUB pc,pc,r4
- NOP ; this instruction is skipped
-
- MOV r7, #MMUC_D ; Now turn the MMU off
- SetCop r7, CR_Control
-
- B ts_VIDCtest
-
-
-;
-; The VIDC tests check vertical blanking frequency in a fixed video
-; mode and measure the time taken for sound DMA.
-;
-
- ROUT
-
-1
- = "VIDC :",0
-2
- = "Virq bad",&88,' ',&ff,'.',&ff,&ff,&ff,&ff,&ff,0
-3
- = "Sirq bad",&8B,&ff,&ff,&ff,&ff,&ff,0
-4
- = &8A,"Mid0 ",&ff,0
-
- ALIGN
-
-ts_VIDCtest
- ADR r4,%BT1
- BL ts_SendText
- [ IO_Type = "IOMD"
- LDR r0,=IOMD_MonitorType ; Indicate monitor ID bit's value
- LDR r0,[r0]
- AND r0,r0,#IOMD_MonitorIDMask
- MOV r8,r0,LSL #28
- ADR r4,%BT4
- BL ts_MoreText
- ]
-
- BL ts_VIDC_period
- BEQ %10
- ADR r4,%B2
- MOV r8, r0, LSL #8
- BL ts_SendText ; Display Virq fail msg
- FAULT #R_VIDFAILBIT
-10
- [ IO_Type = "IOMD"
- MOV r3,#IOMD_Base ; skip Sirq test on version 1 IOMD
- LDRB r0,[r3,#IOMD_VERSION]
- CMPS r0,#1
- BEQ %FT20
- ]
- BL ts_SIRQ_period
- BEQ %20
- ADR r4,%B3
- MOV r8, r0, LSL #12
- BL ts_SendText ; Display Sirq fail msg
- FAULT #R_SNDFAILBIT
-20
- MOV r1,#ts_VIDCPhys ; Restore full-screen
- ADRL r2,TestVIDCTAB ; border colour.
- [ IO_Type = "IOMD"
- LDR r0,=IOMD_MonitorType
- LDR r0,[r0]
- ANDS r0,r0,#IOMD_MonitorIDMask
- ADDEQ r2,r2,#(TestVVIDCTAB-TestVIDCTAB)
- ]
-30 LDR r0, [r2],#4
- CMP r0, #-1
- STRNE r0, [r1]
- BNE %BT30
- LDR r0,=C_ARMOK ; set initial screen colour
- STR r0, [r1]
-
- B ts_ARMtype_test
-
-;
-; Read the ARM3 identification register.
-; If memory tests failed, this won't be performed since the vector
-; page must exist for error recovery on ARM2 systems.
-;
-
- ROUT
-1
- = "ARM ID:",0
-2
- = "ARM ID",&88,&ff,&ff,&ff,&ff,&ff,&ff,&ff,&ff,0
-3
- = &89,"skipped",0
-
- ALIGN
-
-ts_ARMtype_test
-
- ADR r4,%BT1
- BL ts_SendText
-
- MOV_fiq r0,r12_fiq ; skip this test if memory fault
- LDR r1,=((R_LINFAILBIT :OR: R_MEMFAILBIT) :OR: (R_CAMFAILBIT :OR: R_PROFAILBIT))
- ANDS r0,r0,r1
- BEQ %05
- ADR r4,%BT3
- BL ts_MoreText
- B %08 ; and quit
-
-05
- BL ts_ARM_type
- MOVS r8, r0 ; ready to display ID code
- ADR r4,%BT2
-
- BEQ %FT07 ; ARM 2 : skip cache test
- FAULT #R_ARM3 ; not really a fault, just status
-07
- BL ts_SendText
-
-08
- B ts_Report
-
-
-
-;
-; Report the test results to the user
-;
-; If this was a forced test (test adapter fitted) then pause even when
-; test passed : otherwise, pause only on error.
-;
-
-ts_passmsg
- = "PASS :",&88,&ff,&ff,&ff,&ff,&ff,&ff,&ff,&ff,0
-ts_failmsg
- = "FAIL :",&88,&ff,&ff,&ff,&ff,&ff,&ff,&ff,&ff,0
-
-ts_R00 & 00
-
-ts_Report ROUT
- MOV_fiq r7,r12_fiq ; check for fault bits set
- LDR r0,=R_STATUS
- BICS r0,r7,r0
-
- ADREQ r4, ts_passmsg ; tests passed
- LDREQ r9,=C_PASSED
-
- ADRNE r4, ts_failmsg ; tests failed
- LDRNE r9,=C_FAULT
-
- LDR r0,=ts_VIDCPhys ; write the border colour
- STR r9,[r0]
-
- MOV r8,r7
- BL ts_SendText ; write the message and fault code
-
- ; if the test adapter is present, leave green screen awhile
- ; otherwise, wait only if there's a fault.
-
- LDR r3,=ts_recover_time
-00 ADDS r3,r3,r3 ; 16-loop delay
- BCC %B00 ; - let the adapter recover
- ; from previous bus activity
- ADR r2,ts_R00
- ORR r2,r2,#ts_Alias_bits
- LDR r3,[r2]
- MOV r2,#-1
- ADDS r3,r3,r2
- BCS ts_Report_wait
-
- MOV_fiq r0,r12_fiq
- LDR r2,=R_STATUS
- BICS r0,r0,r2
- BEQ ts_Hardstart
-
-ts_Report_wait ROUT
-
-;
-; Indicate fault found : Set the border to the fault colour and flash
-; the disk LED, using the fault bitmap in r12_fiq to modulate the flashing.
-
-ts_oldLED_on * &be0000 ; assert SEL0 and INUSE
-ts_oldLED_off * &ff0000 ; on machines with 1772 controller
-ts_oldLEDaddr * (ts_S5_base :OR: &40)
-
-ts_710LED_on * &100000 ; assert SEL0 and MotorEN0
-ts_710LED_off * &110000 ; on machines with 82C710 controller
-ts_710LEDaddr * (ts_PCaddress :OR: (&3f2 :SHL: 2))
-
-ts_665LED_on * &10 ; assert SEL0 and MotorEN0
-ts_665LED_off * &11 ; on machines with 37665 controller
- ; and Medusa low-byte I/O world
-ts_665LEDaddr * (ts_PCaddress :OR: (&3f2 :SHL: 2))
-
-
-01 MOV_fiq r6,r12_fiq
- LDR r2,=&11111111
- LDR r7,=(35000 * 8) ; 1/4 second pause loop count
-
- [ IO_Type = "IOMD"
- LDRNE r1,=ts_665LEDaddr ; set up for Medusa disc address
- MOVNE r8,#ts_665LED_on
- MOVNE r9,#ts_665LED_off
- |
- TST r6, #R_IOEB ; determine original / 710 disc controller
- LDREQ r1,=ts_oldLEDaddr ; set up for Archimedes disc address
- MOVEQ r8,#ts_oldLED_on
- MOVEQ r9,#ts_oldLED_off
- LDRNE r1,=ts_710LEDaddr ; set up for Brisbane disc address
- MOVNE r8,#ts_710LED_on
- MOVNE r9,#ts_710LED_off
- ]
-
-02 MOV r0,r7
-03 SUBS r0,r0,#1 ; pause for a 1/4 second
- BNE %03
-
- MOV r0,r8 ; turn the LED on
- STR r0,[r1]
-
- MOV r0,r7
-04 SUBS r0,r0,#1 ; pause for a 1/4 second
- BNE %04
- ADDS r6,r6,r6 ; if a '1' is to be written,
- BCC %06
- MOV r0,r7,LSL #1 ; then pause another 1/2 second
-05 SUBS r0,r0,#1
- BNE %05
-
-06
- MOV r0, r9 ; turn the LED off
- STR r0,[r1]
-
-;
-; Count down 32 bits. Every 4 bits, insert an extra pause to simplify
-; reading the flashes.
-;
- ADDS r2,r2,r2
- BCC %08
- MOV r0,r7,LSL #2 ; then pause another second
-05 SUBS r0,r0,#1
- BNE %05
-08
- ANDS r2,r2,r2 ; all the bits displayed now ?
- BNE %02
- MOV_fiq r0,r12_fiq ; restore the faultcode bits
-
- ANDS r0,r0,#(R_EXTERN :OR: R_TESTED) ; If test adapter present,
- BNE Reset ; repeat test forever
-
- B CONT ; otherwise, run RISC OS
-
-ts_Hardstart
- MOVS r0,#R_HARD ; and report a hard start
- B CONT ; to RISC OS
-
-;
-; Tests skipped : fall into RISC-OS
-;
-
-ts_Self_test_end
-
- LDR r1,=C_WARMSTART
- LDR r0,=ts_VIDCPhys ; write the border colour
- STR r1,[r0]
-
-ts_Softstart
- MOVS r0,#R_SOFT ; soft reset indicator
- B CONT
-
-
- ROUT
-
-;
-; This table consists of a series of address/data pairs for IO
-; initialization.
-; Note that these addresses are likely to be in the IO world,
-; and hence the data written is that from the MOST significant
-; 16 bits of the data bus.
-; An 'address' of -1 terminates the table.
-;
-
-ts_IOinitab
- [ IO_Type = "IOMD"
- |
- & ts_S5_base :OR: &10, &000000 ; Printer port data
- & ts_S5_base :OR: &18, &000000 ; FDC control & printer strobes
- & ts_S5_base :OR: &40, &ff0000 ; FDD select lines
- & ts_S5_base :OR: &48, &000000 ; VIDC clock control
- ]
- & (-1)
-
-
-
-
-
-;
-;
-;---------------------------------------------------------------------------
-
- LTORG
-
-
-; Include test modules executed by call, rather than inline
-
- GET TestSrc.Mem2
- GET TestSrc.Mem3
- GET TestSrc.Mem4
- GET TestSrc.Mem5
- GET TestSrc.Vidc
- GET TestSrc.Ioc
- GET TestSrc.Cmos
- GET TestSrc.Arm3
-
- END
diff --git a/OldTestSrc/Cmos b/OldTestSrc/Cmos
deleted file mode 100644
index 610193c5070a152e06e8749a75abfbfa24d333bd..0000000000000000000000000000000000000000
--- a/OldTestSrc/Cmos
+++ /dev/null
@@ -1,321 +0,0 @@
-; > TestSrc.Cmos
-
- TTL RISC OS 2+ POST battery-backed RAM access
-;
-; A function to read bytes from CMOS, for use in verifying the checksum
-; and reading memory test flag & video modes.
-;------------------------------------------------------------------------
-; History
-;
-; Date Name Comment
-; ---- ---- -------
-; 05-Apr-91 ArtG Initial version, based on IICMod.
-;
-;
-;------------------------------------------------------------------------
-;
-; in:
-; R0 = device address (bit 8 - 15 register address )
-; R1 = length of block to read
-; R2 = initial sum value
-;
-; out: R0 = sum of all bytes in block
-; R1 - R13 trashed
-;
-
-ts_CMOSread ROUT
-
- MOV R13,R14
- MOV R8,R2 ; initialise accumulator
- MOV R7,R1 ; initialise byte counter
- MOV R6,R0 ; stash register address
- MOV R2, #IOC
- MOV R0, #-1 ; ensure timer is ticking
- STRB R0, [R2, #Timer0LL] ; (nonzero in input latch)
- STRB R0, [R2, #Timer0LH]
- STRB R0, [R2, #Timer0GO] ; load the count registers
- BL ts_Start
- BEQ %FT30 ; check clock line toggles OK
- AND R0, R6, #&FE
- BL ts_TXCheckAck ; transmit device address (write)
- BVS %FT30
- MOV R0, R6, LSR #8
- BL ts_TXCheckAck ; write register address
- BVS %FT30
- BL ts_Start ; Extra START bit to switch modes
- AND R0, R6, #&FE
- ORR R0, R0, #1
- BL ts_TXCheckAck ; transmit device address (read)
- BVS %FT30
-20
- BL ts_RXByte ; read byte from bus
- ADD R8, R8, R0 ; accumulate total
- SUBS R7, R7, #1 ; is it last byte ?
- MOVNE R0, #0 ; no, then acknowledge with 0 bit
- MOVEQ R0, #1 ; yes, then don't acknowledge
- BL ts_ClockData ; but always send ack clock pulse
- TEQ R7, #0 ; loop, until last byte
- BNE %BT20
-30
- MOVVS R7, #-1 ; pass error indicator to caller
- BL ts_Stop
- MOV R0, R8
- TEQ R7, #0 ; return zero flag if read OK
- MOV PC,R13
-
-; *****************************************************************************
-;
-; TXCheckACK - transmit a byte and wait for slave to ACK
-;
-; out: Trashes r0,r1,r2,r3,r4,r5,r9,r10,r11,r12
-; V bit set on error.
-;
-
-ts_TXCheckAck ROUT
- MOV R12,R14
- BL ts_TXByte
- BL ts_Acknowledge
- MOVVC PC, R12 ; acknowledged ok, so return
- ORRS PC, R12, #V_bit
-
-; *****************************************************************************
-;
-; SetC1C0 - Set clock and data lines to values in R1 and R0 respectively
-;
-; out: Trashes r0,r1,r2,r11
-;
-
-ts_SetC1C0 ROUT
- MOV R11, R14
- BIC R14, R14, #Z_bit ; indicate not checking clock
-ts_SetOrCheck
- ORR R14, R14, #I_bit ; disable interrupts
- TEQP R14, #0
-
- ADD R0, R0, R1, LSL #1 ; R0 := C0 + C1*2
-
- ORR R0, R0, #&C0 ; make sure two test bits are
- ; always set to 1 !
- MOV R2, #IOC
- STRB R0, [R2, #IOCControl]
-10
- LDREQB R1, [R2, #IOCControl] ; wait for clock
- TSTEQ R1, #i2c_clock_bit ; to read high
- BEQ %BT10
-
- MOV R0, #10 ; delay for >= 10/2 microsecs
-;
-; in-line do-micro-delay to save a stack level
-;
- STRB R0, [R2, #Timer0LR] ; copy counter into output latch
- LDRB R1, [R2, #Timer0CL] ; R1 := low output latch
-20
- STRB R0, [R2, #Timer0LR] ; copy counter into output latch
- LDRB R14, [R2, #Timer0CL] ; R14 := low output latch
- TEQ R14, R1 ; unchanged ?
- MOVNE R1, R14 ; copy anyway
- BEQ %BT20 ; then loop
- SUBS R0, R0, #1 ; decrement count
- BNE %BT20 ; loop if not finished
-;
-; end do-micro-delay
-;
- MOV PC, R11
-
-; Set clock and data lines to R1 and R0 and then wait for clock to be high
-
-ts_SetC1C0CheckClock ROUT
- MOV R11, R14
- ORR R14, R14, #Z_bit ; indicate checking clock
- B ts_SetOrCheck
-
-
-; *****************************************************************************
-;
-; ClockData - Clock a bit of data down the IIC bus
-;
-; in: R0 = data bit
-;
-; out: Trashes r0,r1,r2,r3,r10,r11
-;
-
-ts_ClockData ROUT
- MOV R10,R14
-
- MOV R3, R0 ; save data
- MOV R1, #0 ; clock LO
- BL ts_SetC1C0
-
- MOV R1, #1 ; clock HI
- MOV R0, R3
- BL ts_SetC1C0CheckClock
-
-; Delay here must be >= 4.0 microsecs
-
- MOV R1, #0 ; clock LO
- MOV R0, R3
- BL ts_SetC1C0
-
- MOV PC,R10
-
-; *****************************************************************************
-;
-; Start - Send the Start signal
-;
-; out: Trashes r0,r1,r2,r9,r11
-; R0 (and Z flag) indicates state of clock .. should be NZ.
-;
-
-ts_Start ROUT
- MOV R9,R14
-
- MOV R0, #1 ; clock HI, data HI
- MOV R1, #1
- BL ts_SetC1C0
-
-; Delay here must be >= 4.0 microsecs
-
- MOV R0, #0 ; clock HI, data LO
- MOV R1, #1
- BL ts_SetC1C0
-
-; Make sure clock really is high (and not shorted to gnd)
-
- LDRB R3, [R2, #IOCControl]
-
-; Delay here must be >= 4.7 microsecs
-
- MOV R0, #0 ; clock LO, data LO
- MOV R1, #0
- BL ts_SetC1C0
-
- ANDS R0, R3, #i2c_clock_bit
- MOV PC,R9
-
-; *****************************************************************************
-;
-; Acknowledge - Check acknowledge after transmitting a byte
-;
-; out: Trashes r0,r1,r2,r3,r9,r11
-; V=0 => acknowledge received
-; V=1 => no acknowledge received
-;
-
-ts_Acknowledge ROUT
- MOV R9,R14
-
- MOV R0, #1 ; clock LO, data HI
- MOV R1, #0
- BL ts_SetC1C0
-
- MOV R0, #1 ; clock HI, data HI
- MOV R1, #1
- BL ts_SetC1C0CheckClock
-
-; Delay here must be >= 4.0 microsecs
-
- MOV R2, #IOC
- LDRB R3, [R2, #IOCControl] ; get the data from IOC
-
- MOV R0, #1 ; clock LO, data HI
- MOV R1, #0
- BL ts_SetC1C0
-
- TST R3, #1 ; should be LO for correct acknowledge
- MOV R3, PC
- BICEQ R3, R3, #V_bit ; clear V if correct acknowledge
- ORRNE R3, R3, #V_bit ; set V if no acknowledge
- TEQP R3, #0
-
- MOV PC,R9
-
-; *****************************************************************************
-;
-; Stop - Send the Stop signal
-;
-; out: Trashes r0,r1,r2,r9,r11
-;
-
-ts_Stop ROUT
- MOV R9,R14
-
- MOV R0, #0 ; clock HI, data LO
- MOV R1, #1
- BL ts_SetC1C0
-
-; Delay here must be >= 4.0 microsecs
-
- MOV R0, #1 ; clock HI, data HI
- MOV R1, #1
- BL ts_SetC1C0
-
- MOV PC,R9
-
-; *****************************************************************************
-;
-; TXByte - Transmit a byte
-;
-; in: R0 = byte to be transmitted
-;
-; out: Trashes r0,r1,r2,r3,r4,r5,r9,r10,r11
-;
-
-ts_TXByte ROUT
- MOV R9, R14
- MOV R4, R0 ; byte goes into R4
- MOV R5, #&80 ; 2^7 the bit mask
-10
- ANDS R0, R4, R5 ; zero if bit is zero
- MOVNE R0, #1
- BL ts_ClockData ; send the bit
- MOVS R5, R5, LSR #1
- BNE %BT10
- MOV PC, R9
-
-; *****************************************************************************
-;
-; RXByte - Receive a byte
-;
-; out: R0 = byte received
-; Trashes r1,r2,r3,r4,r9,r11
-;
-
-ts_RXByte ROUT
- MOV R9, R14
- MOV R3, #0 ; byte:=0
- MOV R2, #IOC
- MOV R4, #7
-
- MOV R0, #1 ; clock LO, data HI
- MOV R1, #0
- BL ts_SetC1C0
-10
- MOV R0, #1 ; pulse clock HI
- MOV R1, #1
- BL ts_SetC1C0CheckClock
-
- LDRB R1, [R2, #IOCControl] ; get the data from IOC
- AND R1, R1, #1
- ADD R3, R1, R3, LSL #1 ; byte:=byte*2+(IOC?0)AND1
-
- MOV R0, #1 ; return clock LO
- MOV R1, #0
- BL ts_SetC1C0
-
- SUBS R4, R4, #1
- BCS %BT10
-
- MOV R0, R3 ; return the result in R0
- MOV PC, R9
-
- LTORG
-
- END
-
-
-
-
-
-
-
-
diff --git a/OldTestSrc/ExtCmd b/OldTestSrc/ExtCmd
deleted file mode 100644
index 963d2660804f148cac499eb1115b3119699d0fd9..0000000000000000000000000000000000000000
--- a/OldTestSrc/ExtCmd
+++ /dev/null
@@ -1,1019 +0,0 @@
-; > TestSrc.ExtCmd
-
- TTL RISC OS 2+ POST external commands
-;
-; External test commands for RISC OS ROM.
-;
-; Provides functions to read data, write data and execute code using
-; parameters from an external controlling host.
-;
-; A minimal set of opcodes should be used (ideally, only B, LDR and ADDS)
-; so that a processor test may be validly included in the internal test
-; sequence.
-;
-;------------------------------------------------------------------------
-; History
-;
-; Date Name Comment
-; ---- ---- -------
-; 27-Nov-89 ArtG Initial version
-; 06-Dec-89 ArtG Release 0.2 for integration
-; 30-Mar-90 ArtG Added NOPs (ADDS r0,r0,r0) after ADDS pc,..
-; 19-Apr-90 ArtG Speedups for read/write commands.
-; 15-May-90 ArtG Fixed multiple %13 label in ts_W_FIW
-; 22-May-90 ArtG Fixed bugs in ts_B_MWW, ts_W_RIB
-; 18-Jun-93 ArtG Added Arm600 control instructions
-; 1-Jul-93 ArtG Replaced ADDS pc.. instructions with ADD pc..
-; for compatibility with SVC32_mode.
-;
-;------------------------------------------------------------------------
-
-
-
-;
-; All these routines use registers as follows :
-;
-; r0 - always zero
-; r1
-; r2
-; r3 - undisturbed : used as constant by I/O routine
-; r4 - return value from I/O routine, parameter to I/O routines
-; r5
-; r6
-; r7 - saved value of command byte on entry
-; r8 - operation counter
-; r9 - pointer to data transfer operation
-; r10 - increment value (0, 1 or 4) to add to pointer in r9
-; r11 - decrement constant (-1) to add to counter in r8
-; r12 - checksum accumulator
-; r13 - pointer to operation code
-; r14 - return address for calls to I/O routines
-;
-
- SUBT External command handlers
-;
-; Called by vectoring through command_table.
-; R4 contains command byte (including 3 option bits)
-; Get operation count
-; Get address
-; If single-word data
-; Get data
-; Get checksum
-; Reply with command byte or FF
-; Do operation
-; Else
-; For each word
-; Get data
-; Do operation
-; Get checksum
-; Reply with command byte or FF
-; Return by branching to GetCommand.
-
-ts_write_memory ROUT
-
- ADDS r13,r0,r4 ; save the control byte
- ADDS r7,r0,r4
- ADDS r14, r0, pc ; setup return address for ..
- B ts_GetWord ; .. get operation count word
- ADDS r8, r0, r4 ; r8 is operation count
- ADDS r12,r0,r4 ; initialise checksum
- ADDS r14, r0, pc
- B ts_GetWord ; r9 is initial target address
- ADDS r9, r0, r4
- ADDS r12,r12,r4 ; accumulate checksum
- ADDS r10,r0,r0 ; set initial constants
- LDR r11,%01
- ADD pc,pc,r0
-01
- DCD (0 - 1)
-
-;
-; Check for operations which don't involve reading a block of data.
-; These are acknowledged BEFORE performing the operation.
-;
- ADDS r0,r0,r0
- ADDS r13,r13,r13 ; convert operation code to vector
- ADDS r13,r13,r13
- LDR r4, %02
- ADD pc,pc,r0
-02
- & (ts_write_cmd_table - %03)
- ADDS r4,pc,r4
- ADDS r13,r4,r13
-03
- LDR r13,[r13] ; fetch pointer to code
- LDR r4,%04
- ADD pc,pc,r0
-04
- & (ts_write_cmd_table - ts_W_fetch_operations)
- ADDS r0,r0,r0
- ADDS r4,r4,r13
- BCS ts_Write_getdata ; defer acknowledgement till later
-
- ; check the above test was valid, given code layout
- ; Note - this is also required by code near ts_Write_cmd_done
-
- ASSERT (ts_W_RSW < ts_W_fetch_operations)
- ASSERT (ts_W_RSB < ts_W_fetch_operations)
- ASSERT (ts_W_RIW < ts_W_fetch_operations)
- ASSERT (ts_W_RIB < ts_W_fetch_operations)
- ASSERT (ts_W_FSW >= ts_W_fetch_operations)
- ASSERT (ts_W_FSB >= ts_W_fetch_operations)
- ASSERT (ts_W_FIW >= ts_W_fetch_operations)
- ASSERT (ts_W_FIB >= ts_W_fetch_operations)
-
-;
-; Fetch the first data word and checksum, and acknowledge
-;
-
- ADDS r14,r0,pc ;get next data word
- B ts_GetWord
- ADDS r12,r12,r4 ;accumulate checksum
- ADDS r10,r0,r4
- ADDS r14,r0,pc
- B ts_GetWord ;read transmitted checksum
- ADDS r4,r4,r12 ;tx + total should be zero
- LDR r5,%05
- ADD pc,pc,r0
-05
- & (0 - 1)
- ADDS r5,r5,r4 ;carry set on checksum failure
- BCS ts_cmd_error
-
-;
-; Checksum looks OK. Send the command and the checksum back.
-;
- LDR r4,%06
- ADD pc,pc,r0
-06
- & ts_WriteCmdByte
- ADDS r4,r4,r7 ;restore the original
-
- ADDS r14,r0,pc
- B ts_SendByte
- ADDS r4,r0,r12 ;then send the calculated checksum
- ADDS r14,r0,pc
- B ts_SendWord
-
- ADDS r4,r0,r10 ;restore the data word
- ADDS r10,r0,r0 ;and the zero in r10
- B ts_Write_usedata ;dive off to do the work
-
-;
-; Enter the main loop, repeating the operation labelled in r13.
-;
-
-ts_Write_getdata
- ADDS r9,r9,r10 ;perform increment operation
- ADDS r8,r8,r11 ;countdown repeat counter
- BCC ts_Write_cmd_ack
- ADDS r14,r0,pc ;get next data word
- B ts_GetWord
- ADDS r12,r12,r4 ;accumulate checksum
- B %07
-
-ts_Write_usedata
- ADDS r9,r9,r10 ;perform increment operation
-ts_Write_count
- ADDS r8,r8,r11 ;countdown repeat counter
- BCC ts_Write_cmd_done
-07
- ADD pc,pc,r13 ;jump back to operations
- & 0
-
-;
-; In this table, the operation after any word fetch is vectored by
-; the 3 least significant bits of the command byte to perform some
-; combination of writing with :
-;
-; bit 2 -> 0 R : repeat with same data
-; 1 F : fetch more data for next operation
-;
-; bit 1 -> 0 S : leave address static
-; 1 I : increment address after operation
-;
-; bit 0 -> 0 W : word operation
-; 1 B : byte operation
-;
-
- ASSERT ((ts_write_cmd_table - %07) = 8)
-
-ts_write_cmd_table
-
- DCD (ts_W_RSW - ts_write_cmd_table)
- DCD (ts_W_RSB - ts_write_cmd_table)
- DCD (ts_W_RIW - ts_write_cmd_table)
- DCD (ts_W_RIB - ts_write_cmd_table)
- DCD (ts_W_FSW - ts_write_cmd_table)
- DCD (ts_W_FSB - ts_write_cmd_table)
- DCD (ts_W_FIW - ts_write_cmd_table)
- DCD (ts_W_FIB - ts_write_cmd_table)
-
-;
-; And here are the trailers that perform these operations.
-; Each is started with the data in r4, address in r9 and completes
-; by returning to Write_getdata (to read another word) or Write_usedata
-; (to repeat with the same data) with r10 = increment value (initially 0)
-;
-
-ts_W_RSW
- STR r4,[r9] ;store word, repeat address
- ADDS r8,r8,r11 ;countdown repeat counter
- BCS ts_W_RSW
- B ts_Write_cmd_done
-
-ts_W_RSB
- STRB r4,[r9] ;store byte, repeat address
- ADDS r8,r8,r11
- BCS ts_W_RSB
- B ts_Write_cmd_done
-
-ts_W_RIW
- LDR r10,%11
- ADD pc,pc,r0
-11
- DCD 4
-12
- STR r4,[r9] ;store word, increment word address
- ADDS r9,r9,r10 ;perform increment operation
- ADDS r8,r8,r11 ;countdown repeat counter
- BCS %B12
- B ts_Write_cmd_done
-
-
-ts_W_RIB
- LDR r10,%13
- ADD pc,pc,r0
-13
- DCD 1
-14
- STRB r4,[r9] ;store byte, increment byte address
- ADDS r9,r9,r10
- ADDS r8,r8,r11
- BCS %B14
- B ts_Write_cmd_done
-
-
-
-ts_W_fetch_operations ;all past here fetch new data
- ;on each loop
-
-ts_W_FSW
- STR r4,[r9] ;store word, repeat address
- B ts_Write_getdata
-
-ts_W_FSB
- STRB r4,[r9] ;store byte, repeat address
- B ts_Write_getdata
-
-ts_W_FIW
- STR r4,[r9] ;store word, increment word address
- LDR r10,%15
- B ts_Write_getdata
-15
- DCD 4
-
-ts_W_FIB
- STRB r4,[r9] ;store byte, increment byte address
- LDR r10,%16
- B ts_Write_getdata
-16
- DCD 1
-
-
-;
-; Operations completed. Operations that read multiple data words from
-; the host must now checksum and acknowledge the block (even though
-; it's a bit late to do anything about it)
-;
-
-ts_Write_cmd_ack
-;
-; Operation involved multiple fetches - only now ready to ACK.
-;
- ADDS r14,r0,pc
- B ts_GetWord ;read transmitted checksum
- ADDS r4,r4,r12 ;tx + total should be zero
- LDR r5,%25
- ADD pc,pc,r0
-25
- & (0 - 1)
- ADDS r5,r5,r4 ;carry set on checksum failure
- BCS ts_cmd_error
-
-;
-; Checksum looks OK. Send the command and the checksum back.
-;
- LDR r4,%26
- ADD pc,pc,r0
-26
- & ts_WriteCmdByte
- ADDS r4,r4,r7 ;restore the original
- ADDS r14,r0,pc
- B ts_SendByte
- ADDS r4,r0,r12 ;then send the calculated checksum
- ADDS r14,r0,pc
- B ts_SendWord
-
-ts_Write_cmd_done
- B ts_GetCommand
-
-
-
-; Called by vectoring through command_table.
-; R4 contains command byte (including 3 option bits)
-; Get operation count
-; Get address
-; Reply with command byte or FF
-; Reply with checksum
-; For each word
-; Read data
-; If Verbose option
-; Send data
-; If Quiet option
-; Send result of read operation
-; Send checksum of result packet
-; Return by branching to GetCommand.
-
-ts_read_memory ROUT
-
- ADDS r13,r0,r4 ; save the control byte
- ADDS r7,r0,r4
-
- ADDS r14, r0, pc ; setup return address for ..
- B ts_GetWord ; .. get operation count word
- ADDS r8, r0, r4 ; r8 is operation count
- ADDS r12,r0,r4 ; initialise checksum
-
- ADDS r14, r0, pc
- B ts_GetWord ; r9 is initial target address
- ADDS r9, r0, r4
- ADDS r12,r12,r4 ; accumulate checksum
- ADDS r10,r0,r0 ; set initial constants
- LDR r11,%01
- ADD pc,pc,r0
-01
- DCD (0 - 1)
-;
-; Convert the operation options into a code pointer
-;
- ADDS r0,r0,r0
- ADDS r13,r13,r13 ; convert operation code to vector
- ADDS r13,r13,r13
- LDR r4, %02
- ADD pc,pc,r0
-02
- & (ts_read_cmd_table - %03)
- ADDS r4,pc,r4
- ADDS r13,r4,r13
-03
- LDR r13,[r13] ; fetch pointer to code
-
-;
-; Fetch the checksum, and acknowledge
-;
-
- ADDS r14,r0,pc
- B ts_GetWord ;read transmitted checksum
- ADDS r4,r4,r12 ;tx + total should be zero
- LDR r5,%05
- ADD pc,pc,r0
-05
- & (0 - 1)
- ADDS r5,r5,r4 ;carry set on checksum failure
- BCS ts_cmd_error
-
-;
-; Checksum looks OK. Send the command and the checksum back.
-;
- LDR r4,%06
- ADD pc,pc,r0
-06
- & ts_ReadCmdByte
- ADDS r4,r4,r7 ;restore the original
- ADDS r14,r0,pc
- B ts_SendByte
- ADDS r4,r0,r12 ;then send the calculated checksum
- ADDS r14,r0,pc
- B ts_SendWord
-
- ADDS r12,r0,r0 ;initialise the upload checksum
- B ts_Read_count ;enter the loop
-
-;
-; Enter the main loop, repeating the operation labelled in r13.
-; This loop is for operations that finish with all data sent
-
-ts_Read_Txdata ;send data to host
- ADDS r12,r12,r4 ;accumulate the checksum
- ADDS r14,r0,pc
- B ts_SendWord ;send this word
- ADDS r9,r9,r10 ;perform increment operation
- ADDS r8,r8,r11 ;countdown repeat counter
- BCC ts_Read_cmd_done
- B %07 ;go off to the jump handler
-
-ts_Read_count
- ADDS r8,r8,r11 ;countdown repeat counter
- BCC ts_Read_cmd_read ;send data at finish
-07
- ADD pc,pc,r13 ;jump back to operations
- & 0
-
-;
-; In this table, the operation after any word fetch is vectored by
-; the 2 least significant bits of the command byte to perform some
-; combination of reading with :
-;
-; bit 2 -> 0 Q : read data without reporting it
-; 1 V : Transmit the result of every read operation
-;
-; bit 1 -> 0 S : leave address static
-; 1 I : increment address after operation
-;
-; bit 0 -> 0 W : word operation
-; 1 B : byte operation
-;
-
- ASSERT ((ts_read_cmd_table - %07) = 8)
-
-ts_read_cmd_table
-
- DCD (ts_R_QSW - ts_read_cmd_table)
- DCD (ts_R_QSB - ts_read_cmd_table)
- DCD (ts_R_QIW - ts_read_cmd_table)
- DCD (ts_R_QIB - ts_read_cmd_table)
- DCD (ts_R_VSW - ts_read_cmd_table)
- DCD (ts_R_VSB - ts_read_cmd_table)
- DCD (ts_R_VIW - ts_read_cmd_table)
- DCD (ts_R_VIB - ts_read_cmd_table)
-
-;
-; And here are the trailers that perform these operations.
-; Each is started with the data in r4, address in r9 and completes
-; by returning to Write_getdata (to read another word) or Write_usedata
-; (to repeat with the same data) with r10 = increment value (initially 0)
-;
-
-ts_R_QSW
- LDR r4,[r9] ;read word, repeat address
- ADDS r8,r8,r11 ;countdown repeat counter
- BCS ts_R_QSW
- B ts_Read_cmd_read ;send data at finish
-
-
-ts_R_QSB
- LDRB r4,[r9] ;read byte, repeat address
- ADDS r8,r8,r11
- BCS ts_R_QSB
- B ts_Read_cmd_read
-
-ts_R_QIW
- LDR r10,%11
- ADD pc,pc,r0
-11
- DCD 4
-12
- LDR r4,[r9] ;read word, increment word address
- ADDS r9,r9,r10 ;perform increment operation
- ADDS r8,r8,r11 ;countdown repeat counter
- BCS %B12
- B ts_Read_cmd_read ;send data at finish
-
-
-ts_R_QIB
- LDR r10,%13
- ADD pc,pc,r0
-13
- DCD 1
-14
- LDRB r4,[r9] ;read byte, increment byte address
- ADDS r9,r9,r10 ;perform increment operation
- ADDS r8,r8,r11 ;countdown repeat counter
- BCS %B14
- B ts_Read_cmd_read ;send data at finish
-
-
-ts_R_VSW
- LDR r4,[r9] ;read and tx word, repeat address
- B ts_Read_Txdata
-
-ts_R_VSB
- LDRB r4,[r9] ;read and tx byte, repeat address
- B ts_Read_Txdata
-
-ts_R_VIW
- LDR r4,[r9] ;read and tx word, next word address
- LDR r10,%15
- B ts_Read_Txdata
-15
- DCD 4
-
-ts_R_VIB
- ADDS r0,r0,r0
- LDRB r4,[r9] ;read and tx byte, next byte address
- LDR r10,%16
- B ts_Read_Txdata
-16
- DCD 1
-
-
-;
-; Operations completed. Report final result and checksum back to host.
-; Quiet option only transmits read data here (this is pretty useless
-; except where only one value was read)
-;
-
-ts_Read_cmd_read
- ADDS r12,r12,r4
- ADDS r14,r0,pc ;send result of 'quiet' read
- B ts_SendWord
-ts_Read_cmd_done
- SUBS r4,r0,r12 ;get overall checksum - can't think
- ADDS r14,r0,pc ;how to do this using only ADDS !
- B ts_SendWord
-
- B ts_GetCommand
-
-
-; Called by vectoring through command table.
-; if option 1 set, read processor mode
-; Read address
-; Read and check checksum
-; Reply with command byte or FF
-; Reply with checksum
-; if option 1 set, load SPSR
-; Jump to code
-
-
-ts_execute ROUT
- ADDS r12,r0,r0 ; initialise checksum adder
- LDR r8,%00 ; initialise msr-jumper
- ADD pc,pc,r0
-00
- & 4
- ADDS r7,r4,r4 ; get operation type
- ADDS r7,r7,r7
- ADD pc,pc,r7 ; jump to pc + (r4 * 4)
- & 0
-
- B %FT10
- B %FT08
- B %FT10
- B %FT10
- B %FT10
- B %FT10
- B %FT10
- B %FT10
-
-
-08 ADDS r14,r0,pc ; get new processor mode
- B ts_GetWord
- ADDS r12,r0,r4
- ADDS r8,r0,r0 ; kill msr-jumper
-10
- ADDS r14,r0,pc
- B ts_GetWord ; get jump address
- ADDS r9,r12,r4
- ADDS r14,r0,pc
- B ts_GetWord ; get checksum
- ADDS r4,r4,r9
- LDR r5,%11
- ADD pc,pc,r0
-11
- & (0 - 1)
- ADDS r4,r5,r4 ; compare total chex with zero
- BCS ts_cmd_error ; carry set on error
-
- LDR r4,%12
- ADD pc,pc,r0
-12
- & ts_ExecuteCmdByte
- ADDS r0,r0,r0
- ADDS r14,r0,pc ; echo command byte
- B ts_SendByte
- ADDS r4,r0,r9 ;return checksum (actually, the
- ADDS r14,r0,pc ; entire message ..)
- B ts_SendWord
-
-
-; Now jump to the location given in the message, using the given status bits
-
- ADD pc,pc,r8 ; jump over the msr instruction
- NOP
- & 2_11100001011010011111000000001100 ;
-
- ADDS r14,pc,r0 ; Load the address of %13 into r14
- ; to provide a return address
- ADD pc,r0,r9 ; Do the jump
-13
- B ts_GetCommand
-
-
-
-; Called by vectoring through command table
-; Read operation count
-; Read target addresses
-; Read data
-; Send command byte or FF
-; Send checksum
-; For all operation count
-; write data
-; if read-back option
-; read data
-; Return by branching to GetCommand
-
-
-ts_bus_exercise ROUT
- ADDS r7,r0,r4 ; save the control byte
-
- ADDS r14, r0, pc ; setup return address for ..
- B ts_GetWord ; .. get operation count word
- ADDS r8, r0, r4 ; r8 is operation count
- ADDS r12,r0,r4 ; initialise checksum
-
- ADDS r14, r0, pc
- B ts_GetWord ; r9 is first target address
- ADDS r9, r0, r4
- ADDS r12,r12,r4 ; accumulate checksum
- ADDS r14, r0, pc
- B ts_GetWord ; r10 is second target address
- ADDS r10, r0, r4
- ADDS r12,r12,r4 ; accumulate checksum
-
- ADDS r14, r0, pc
- B ts_GetWord ; r11 is first data word
- ADDS r11, r0, r4
- ADDS r12,r12,r4 ; accumulate checksum
- ADDS r14, r0, pc
- B ts_GetWord ; r13 is second data word
- ADDS r13, r0, r4
- ADDS r12,r12,r4 ; accumulate checksum
-
-;
-; Fetch the checksum, and acknowledge
-;
-
- ADDS r14,r0,pc
- B ts_GetWord ;read transmitted checksum
- ADDS r4,r4,r12 ;tx + total should be zero
- LDR r5,%05
- ADD pc,pc,r0
-05
- & (0 - 1)
- ADDS r5,r5,r4 ;carry set on checksum failure
- BCS ts_cmd_error
-
-;
-; Checksum looks OK. Send the command and the checksum back.
-;
- LDR r4,%06
- ADD pc,pc,r0
-06
- & ts_BusExCmdByte
- ADDS r4,r4,r7 ;restore the original
- ADDS r14,r0,pc
- B ts_SendByte
- ADDS r4,r0,r12 ;then send the calculated checksum
- ADDS r14,r0,pc
- B ts_SendWord
-
- ADDS r12,r0,r13 ; Now addresses are in r9, r10
- ; and data in r11, r12.
-;
-; Convert the operation options into a code pointer
-;
- ADDS r13,r7,r7 ; convert operation code to vector
- ADDS r13,r13,r13
- LDR r4, %02
- ADD pc,pc,r0
-02
- & (ts_busex_cmd_table - %03)
- ADDS r4,pc,r4
- ADDS r13,r4,r13
-03
- LDR r13,[r13] ; fetch pointer to code
- LDR r7, %04 ; set up decrementer in r8
- ADD pc,pc,r0
-04
- DCD (0 - 1)
-07
- ADD pc,pc,r13 ; jump to operation
- & 0
-
-;
-; In this table, the operation after any word fetch is vectored by
-; the 3 least significant bits of the command byte to perform some
-; combination of writing with :
-;
-; bit 2 -> 0 S : Perform separate data write ops
-; 1 M : Use STM / LDM instructions
-;
-; bit 1 -> 0 R : Perform only read operations
-; 1 W : Write before reading
-;
-; bit 0 -> 0 W : word operation
-; 1 B : byte operation
-;
-; Note that byte and multiple operations are mutually
-; exclusive.
-;
-
- ASSERT ((ts_busex_cmd_table - %07) = 8)
-
-ts_busex_cmd_table
-
- DCD (ts_B_SRW - ts_busex_cmd_table)
- DCD (ts_B_SRB - ts_busex_cmd_table)
- DCD (ts_B_SWW - ts_busex_cmd_table)
- DCD (ts_B_SWB - ts_busex_cmd_table)
- DCD (ts_B_MRW - ts_busex_cmd_table)
- DCD (ts_B_MRB - ts_busex_cmd_table)
- DCD (ts_B_MWW - ts_busex_cmd_table)
- DCD (ts_B_MWB - ts_busex_cmd_table)
-
-ts_B_SRW
- LDR r11,[r9] ; read-only separate words
- LDR r12,[r10]
- ADDS r8, r8, r7
- BCS ts_B_SRW
- B ts_B_done
-
-ts_B_SRB
- LDRB r11,[r9] ; read-only separate bytes
- LDRB r12,[r10]
- ADDS r8, r8, r7
- BCS ts_B_SRB
- B ts_B_done
-
-ts_B_SWW
- STR r11,[r9] ; write and read separate words
- STR r12,[r10]
- LDR r1,[r9]
- LDR r2,[r10]
- ADDS r8, r8, r7
- BCS ts_B_SWW
- B ts_B_done
-
-ts_B_SWB
- STRB r11,[r9] ; write and read separate bytes
- STRB r12,[r10]
- LDRB r1,[r9]
- LDRB r2,[r10]
- ADDS r8, r8, r7
- BCS ts_B_SWB
- B ts_B_done
-
-
-ts_B_MRW
- LDMIA r9,{r1,r2} ; read-only multiple words
- LDMIA r10,{r1,r2}
- ADDS r8, r8, r7
- BCS ts_B_MRW
- B ts_B_done
-
-ts_B_MWW
- STMIA r9,{r11,r12} ; write and read multiple words
- LDMIA r9,{r1,r2}
- STMIA r10,{r11,r12}
- LDMIA r10,{r1,r2}
- ADDS r8, r8, r7
- BCS ts_B_MWW
- B ts_B_done
-
-;
-; Orthogonally, these should be multiple byte operations - we can't do that,
-; so they actually do a single/multiple mixture.
-; The first address argument is used for word-aligned operations and the
-; second for byte-aligned operations - so set only the second address
-; to a non-word-aligned address.
-
-ts_B_MRB
- LDMIA r9,{r1,r2} ; read-only multiple words
- LDRB r1,[r10] ; then single bytes
- LDR r1,[r9] ; and single words
- ADDS r8, r8, r7
- BCS ts_B_MRB
- B ts_B_done
-
-ts_B_MWB
- STMIA r9,{r11,r12} ; store multiple words
- STRB r11,[r10] ; write byte
- STR r12,[r9] ; write words
- LDMIA r9,{r1,r2}
- LDRB r1,[r10]
- LDR r1,[r9] ; read single and multiple words
- ADDS r8, r8, r7
- BCS ts_B_MWB
-; B ts_B_done
-
-ts_B_done
- B ts_GetCommand
-
-
-
-;
-; All commands fall through here to respond with FF if the received
-; message block checksums fail.
-;
-
-ts_cmd_error ROUT ; error in command
- LDR r4, %01 ; return error response
- ADD pc,pc,r0
-01
- DCD ErrorCmd
- ADDS r0,r0,r0
- ADDS r14, r0, pc ; send response byte to host
- B ts_SendByte
-
- B ts_GetCommand
-
-
-; generic coprocessor register names
-
-cpr0 CN 0
-cpr1 CN 1
-cpr2 CN 2
-cpr3 CN 3
-cpr4 CN 4
-cpr5 CN 5
-cpr6 CN 6
-cpr7 CN 7
-cpr8 CN 8
-cpr9 CN 9
-cpr10 CN 10
-cpr11 CN 11
-cpr12 CN 12
-cpr13 CN 13
-cpr14 CN 14
-cpr15 CN 15
-
-
-; Called by vectoring through command table.
-; Read transfer value
-; Read and check checksum
-; Extract copro register number
-; Index suitable MRC instruction
-; Perform copro write
-; Reply with command byte or FF
-; Reply with checksum
-
-ts_write_cpr15h ROUT
- ADDS r4,r4,#8 ; adjust opcode for high registers
-ts_write_cpr15l
- ADDS r7,r0,r4 ; save opcode to r7
- ADDS r14,r0,pc
- B ts_GetWord ; get value for copro
- ADDS r9,r0,r4
- ADDS r14,r0,pc
- B ts_GetWord ; get checksum
- ADDS r4,r4,r9
- LDR r5,%01
- ADD pc,pc,r0
-01
- & (0 - 1)
- ADDS r4,r5,r4 ; compare total chex with zero
- BCS ts_cmd_error ; carry set on error
-
- ADDS r13,r7,r7 ; point into instruction table
- ADDS r13,r13,r13
- ADDS r13,r13,r13
- ADD pc,pc,r13 ; jump to pc + (r7 * 8)
- & 0
-
- SetCop r9,cpr0 ; transfer instructions
- B %02
- SetCop r9,cpr1
- B %02
- SetCop r9,cpr2
- B %02
- SetCop r9,cpr3
- B %02
- SetCop r9,cpr4
- B %02
- SetCop r9,cpr5
- B %02
- SetCop r9,cpr6
- B %02
- SetCop r9,cpr7
- B %02
- SetCop r9,cpr8
- B %02
- SetCop r9,cpr9
- B %02
- SetCop r9,cpr10
- B %02
- SetCop r9,cpr11
- B %02
- SetCop r9,cpr12
- B %02
- SetCop r9,cpr13
- B %02
- SetCop r9,cpr14
- B %02
- SetCop r9,cpr15
-
-02
- LDR r4,%03
- ADD pc,pc,r0
-03
- & ts_CPWCmdByte ; build command byte + option
- ADDS r4,r4,r7
- ADDS r14,r0,pc ; echo command byte
- B ts_SendByte
- ADDS r4,r0,r9 ; return checksum
- ADDS r14,r0,pc ;
- B ts_SendWord
-
- B ts_GetCommand
-
-
-
-
-; Called by vectoring through command table.
-; Read and check checksum
-; Extract copro register number
-; Index suitable MCR instruction
-; Perform copro read
-; Reply with command byte or FF
-; Reply with checksum
-; Send transfer results
-; Send checksum
-
-ts_read_cpr15h ROUT
- ADDS r4,r4,#8 ; adjust opcode for high registers
-ts_read_cpr15l
- ADDS r7,r0,r4 ; save opcode in r7
- ADDS r14,r0,pc
- B ts_GetWord ; get checksum to r4
- ADDS r9,r0,r4 ; copy to r9
- LDR r5,%01
- ADD pc,pc,r0
-01
- & (0 - 1)
- ADDS r4,r5,r4 ; compare total chex with zero
- BCS ts_cmd_error ; carry set on error
-
- LDR r4,%02
- ADD pc,pc,r0
-02
- & ts_CPRCmdByte ; build command byte + option
- ADDS r4,r4,r7
- ADDS r14,r0,pc ; echo command byte
- B ts_SendByte
- ADDS r4,r0,r9 ; return checksum
- ADDS r14,r0,pc
- B ts_SendWord
-
- ADDS r13,r7,r7 ; point into instruction table
- ADDS r13,r13,r13
- ADDS r13,r13,r13
- ADD pc,pc,r13 ; jump to pc + (r7 * 8)
- & 0
-
- ReadCop r12,cpr0 ; transfer instructions
- B %03
- ReadCop r12,cpr1
- B %03
- ReadCop r12,cpr2
- B %03
- ReadCop r12,cpr3
- B %03
- ReadCop r12,cpr4
- B %03
- ReadCop r12,cpr5
- B %03
- ReadCop r12,cpr6
- B %03
- ReadCop r12,cpr7
- B %03
- ReadCop r12,cpr8
- B %03
- ReadCop r12,cpr9
- B %03
- ReadCop r12,cpr10
- B %03
- ReadCop r12,cpr11
- B %03
- ReadCop r12,cpr12
- B %03
- ReadCop r12,cpr13
- B %03
- ReadCop r12,cpr14
- B %03
- ReadCop r12,cpr15
-
-03
- ADDS r4,r0,r12 ; return result
- ADDS r14,r0,pc
- B ts_SendWord
- SUBS r4,r0,r12 ; return checksum
- ADDS r14,r0,pc
- B ts_SendWord
-
- B ts_GetCommand
-
-
- END
-
-
diff --git a/OldTestSrc/ExtIO b/OldTestSrc/ExtIO
deleted file mode 100644
index 8ef956a201a997890c60749536a7896ac60b7cad..0000000000000000000000000000000000000000
--- a/OldTestSrc/ExtIO
+++ /dev/null
@@ -1,1089 +0,0 @@
-; > TestSrc.ExtIO
-
- TTL RISC OS 2+ POST external commands
-;
-; External interface for RISC OS ROM.
-; provides entry points to send byte- and word- and string-sized objects
-; and to receive byte- and word-sized objects
-;
-; A minimal set of opcodes should be used (ideally, only B, LDR and ADDS)
-; so that a processor test may be validly included in the internal test
-; sequence.
-;
-;------------------------------------------------------------------------
-; History
-;
-; Date Name Comment
-; ---- ---- -------
-; 06-Dec-89 ArtG Initial version - split from `Begin`
-; Release 0.2 for integration
-; 31-Mar-90 ArtG Added ts_MoreText, cursor position, hex.
-; 19-Apr-90 ArtG Added bus exercise commands
-; 09-May-90 ArtG Changed LCD strobe to 12 pulses
-; 15-May-90 ArtG Added ReadyByte : improves synchronization
-; when ExtCmd execution toggles A21/A22.
-; 18-Jun-90 ArtG Added CPR15 read/write functions
-;
-;
-;------------------------------------------------------------------------
-
-
- SUBT Test adapter interface
-
-;
-; The test adapter senses an access to the ROM with address line A21 high.
-; Current (2M addressing space) ROMs only use address lines A2 to A20,
-; so if A21 to A22 are asserted they will be ignored (the ROMS are aliased
-; into 8M of space). With no test adapter, the aliased ROM location will
-; be read and may be recognised. The test adapter may selectively disable
-; ROMs when A21 is high, causing arbitrary data to be read. This data
-; should be dependent on the previous ROM read operation, and will
-; therefore be predictably not equal to the data read when the ROMs are
-; aliased.
-; The assumption that A21 is unused may be invalidated by a later issue
-; of the PCB. A22 is therefore asserted at the same time : this will then
-; be used on a PCB where A22 is tracked to a test connector and 8Mbit ROMS
-; are used. Machines using larger ROMs than 8 Mbit (4M addressing space)
-; will require explicit decoding or a new communication scheme.
-;
-
-
-;
-; This section determines whether the test interface adapter exists, and
-; what variety is fitted (dumb, display or external)
-; 3 read operations are performed (a WS operation): if all of these
-; find a ROM alias then no adapter is fitted.
-;
-; If an adapter responds, then a RD operation is performed - 4 strobes then
-; clocking 8 bits into r4. These bits may be all zeros (a dumb adapter)
-; or all ones (a display adapter) or some other value (an external
-; adapter)
-;
-
-ts_GetCommand ROUT
-
- LDR r0,%01
- ADD pc,pc,r0
-01
- & 0
-
- ; delay to make a gap before reading
-
- LDR r3,%02
- ADD pc,pc,r0
-02
- & ts_recover_time
-03
- ADDS r3,r3,r3 ; 16-loop delay
- BCC %03
-
- ROUT
-
-;
-; Load up the registers for the test interface communication -
-;
-
- LDR r0,%01 ; set zero in r0
- ADD pc,pc,r0 ;(generally useful constant - especially for skip)
-01
- & 0
- LDR r1,%02 ; set FFFFFFFF in r1
- ADD pc,pc,r0 ;(test value : sets carry when added to non-zero)
-02
- & (-1)
- LDR r2,%03 ; set pointer to test address
- ADD pc,pc,r0 ;(points to aliased copy of a zero word)
-03
- & (ts_Alias_bits + (%01 - %04))
- ADDS r2,pc,r2 ; adjust r2 for ROM-relative address
- ADDS r4,r0,r0 ; clear output accumulator
-04 ; where pc is when added to r2
-
- ; do an RD operation (four strobes) to ensure interface cleared
-
- LDR r3,[r2]
- ADDS r3,r3,r1
- LDR r3,[r2]
- ADDS r3,r3,r1
- LDR r3,[r2]
- ADDS r3,r3,r1
- LDR r3,[r2]
- ADDS r3,r3,r1
-
- ; write a byte (initially, &90) to indicate readiness
-
- LDR r4,%20
- ADD pc,pc,r0
-20
- & ts_ReadyByte_00
- ADDS r14,r0,pc
- B ts_SendByte
-
- ; delay to make a gap between WRS and RD operations
-
- LDR r3,%05
- ADD pc,pc,r0
-05
- & ts_recover_time
-06
- ADDS r3,r3,r3 ; 16-loop delay
- BCC %06
-
- LDR r5,%07 ; counter for first 5 bits
- ADD pc,pc,r0
-07
- & 1 :SHL: (32 - 5)
- LDR r6,%08 ; counter for last 3 bits
- ADD pc,pc,r0
-08
- & 1 :SHL: (32 - 3)
- ADDS r4,r0,r0 ; input accumulator initialisation
-
-; put the test interface into input mode
-
- LDR r3,[r2] ; 3 bit lead-in
- ADDS r3,r3,r1 ; (adapter detects WS operation)
- BCC ts_User_startup ; abort if no adapter present
-
- LDR r3,[r2] ; two more strobes, then waitloop
- ADDS r3,r3,r1
- LDR r3,[r2]
- ADDS r3,r3,r1
-
-; started input operation : wait for interface to be ready
-
-09
- LDR r3,[r2] ; read start bit repeatedly
- ADDS r3,r3,r1 ; (adapter detects RD operation)
- BCC %09 ; loop until interface is ready
-
-; read the first 5 bits into r5 and the second 3 bits into r4
-
-10 LDR r3,[r2] ; read a bit of the byte
- ADDS r3,r3,r1 ; .. if the test adapter is present, carry bit set
- ADCS r4,r4,r4 ; .. shift left and add in carry
-
- ADDS r5,r5,r5 ; loop until 5 bits are read
- BCC %10
-
- ADDS r5,r4,r4 ; copy bits 7..3 to r5, bits 5..1
-
- ADDS r4,r0,r0 ; and read the last 3 bits to r4
-11 LDR r3,[r2] ; read a bit of the byte
- ADDS r3,r3,r1
- ADCS r4,r4,r4
-
- ADDS r6,r6,r6 ; loop until last 3 bits are read
- BCC %11
-
-;
-; Command byte read in (split between r4 and r5)
-; Pass the option bits (r4) to the function identified by r5.
-;
-
- ADDS r5,r5,r5 ; index * 2 -> index * 4
- LDR r3,%12 ; pc-relative ptr to command_table
- ADD pc,pc,r0
-12
- & ts_command_table - %13
- ADDS r3,pc,r3 ; absolute pointer to command table
- ADDS r3,r3,r5
-
-13 LDR r3,[r3] ; get table entry
-14 ADD pc,pc,r3 ; (offset from command_table)
-
- & 0 ; necessary padding : pc must point
- ; to command table when r3 is added.
-
-;
-; This is the table of offsets to all the built-in functions.
-; The top 5 bits of the command are used to index, so there are
-; 32 possible entries, mostly illegal.
-; Decoding of the function modifier bits is performed by multiple
-; entries in this table.
-;
-
-; pc must point here when ADDS pc,r3,pc is executed
-
- ASSERT ((ts_command_table - %14) = 8)
-
-ts_command_table
-
- DCD (ts_Dealer_startup - ts_command_table) ; display interface
-ts_Windex
- DCD (ts_write_memory - ts_command_table) ; external tests
-ts_Rindex
- DCD (ts_read_memory - ts_command_table)
-ts_Eindex
- DCD (ts_execute - ts_command_table)
-ts_Bindex
- DCD (ts_bus_exercise - ts_command_table)
-
- DCD (ts_GetCommand - ts_command_table) ; dummy entry aligns CPR instructions
- ; to allow 4-bit option field
-ts_CWindex
- DCD (ts_write_cpr15l - ts_command_table)
- DCD (ts_write_cpr15h - ts_command_table)
-ts_CRindex
- DCD (ts_read_cpr15l - ts_command_table)
- DCD (ts_read_cpr15h - ts_command_table)
-
- ; pad the table out to 31 entries
- ; (leave space for display vector)
-
-OldOpt SETA {OPT}
- OPT OptNoList
-doffset SETA .
- WHILE doffset < (ts_command_table + (31 * 4)) ; illegal entries
- DCD (ts_GetCommand - ts_command_table)
-doffset SETA doffset + 4
- WEND
- OPT OldOpt
-
- DCD (ts_Forced_startup - ts_command_table) ; dumb interface
-
-;
-; The indexes into the above table are needed in ExtCmd ...
-;
-ts_WriteCmdByte * ((ts_Windex - ts_command_table) :SHL: 1)
-ts_ReadCmdByte * ((ts_Rindex - ts_command_table) :SHL: 1)
-ts_ExecuteCmdByte * ((ts_Eindex - ts_command_table) :SHL: 1)
-ts_BusExCmdByte * ((ts_Bindex - ts_command_table) :SHL: 1)
-ts_CPWCmdByte * ((ts_CWindex - ts_command_table) :SHL: 1)
-ts_CPRCmdByte * ((ts_CRindex - ts_command_table) :SHL: 1)
-
-
-;
-; Primitives for reading data from the external interface
-;
-; - Get a byte from the interface (into r4)
-; - Get a (4 byte) word from the interface (into r4)
-;
-; Required register setup is presumed done by a recent ts_GetCommand.
-; r0, r1 and r2 have critical values
-; r14 is the link address
-;
-
-ts_GetWord ROUT
-
- LDR r6,%01 ; counter for 4 bytes per word
- ADD pc,pc,r0 ; (bit set 4 left shifts from Carry)
-01
- & 1 :SHL: (32 - 4)
- B ts_Getdata
-
-ts_GetByte ROUT
- LDR r6,%01 ; counter for single byte
- ADD pc,pc,r0
-01
- & 1 :SHL: (32 - 1)
-
-ts_Getdata ROUT
- ADDS r4,r0,r0 ; input accumulator initialisation
-
- LDR r3,[r2] ; 3 bit lead-in
- ADDS r3,r3,r1 ; (adapter detects RD operation)
- LDR r3,[r2]
- ADDS r3,r3,r1
- LDR r3,[r2]
- ADDS r3,r3,r1
-
-; started input operation : now loop until r6 shifts into Carry
-
-02
- LDR r5,%03 ; counter for 8 bits per byte
- ADD pc,pc,r0
-03
- & 2_00000001000000010000000100000001
-04
- LDR r3,[r2] ; read start bit repeatedly
- ADDS r3,r3,r1
- BCC %04 ; loop until interface is ready
-05
- LDR r3,[r2] ; read a bit of the byte
- ADDS r3,r3,r1
- ADCS r4,r4,r4 ; SHL r4, add carry bit.
-
- ADDS r5,r5,r5 ; loop until byte is read
- BCC %05
-
- ADDS r6,r6,r6 ; loop until word is read
- BCC %04
-
- ADD pc,r0,r14 ; back to the caller
-
-
-;
-; Primitives for sending data to the interface
-;
-; - Send a byte to the interface (from r4 lsb)
-; - Send a (4 byte) word to the interface (from r4)
-;
-; Required register setup is presumed done by a recent ts_GetCommand.
-; r0, r1 and r2 have critical values
-; r14 is the link address
-;
-
-ts_SendWord ROUT
- LDR r6,%01 ; counter for 4 bytes per word
- ADD pc,pc,r0 ; (bit set 4 left shifts from Carry)
-01
- & 1 :SHL: (32 - 4)
- B ts_Putdata
-
-ts_SendByte ROUT
- LDR r6,%01 ; counter for single byte
- ADD pc,pc,r0
-01
- & (3 :SHL: 7)
-02 ADDS r4,r4,r4 ;shift byte into highest 8 bits
- ADDS r6,r6,r6
- BCC %02 ;stop when byte shifted,
- ;leaving bit 31 set in r6
-
-ts_Putdata ROUT
-
-; Wait - gap between successive WS attempts or successive bytes
-
-01 LDR r3,%02
- ADD pc,pc,r0
-02
- & ts_recover_time
-03 ADDS r3,r3,r3 ; 16-loop delay
- BCC %03
-
- LDR r3,[r2] ; Test for adapter ready for data
- ADDS r3,r3,r1 ; (adapter detects WS operation)
- LDR r3,[r2]
- ADDS r3,r3,r1
- BCC %10 ; skip out if adapter not present
- LDR r3,[r2]
- ADDS r3,r3,r1
- BCC %01 ; loop back until adapter is ready
-
-; Adapter ready - loop around all the bits in the byte
-
- LDR r5,%04 ; load bits-per-byte counter
- ADD pc,pc,r0
-04
- & (1 :SHL: (32-8))
-
-05 LDR r3,%06 ; delay before sending bit
- ADD pc,pc,r0
-06
- & ts_recover_time
-07 ADDS r3,r3,r3 ; 16-loop delay
- BCC %07
-
- ; Send a single bit : 1 pulse for 1, 2 pulses for 0
-
- LDR r3,[r2]
- ADDS r4,r4,r4 ; shift current bit into Carry
- LDRCC r3,[r2] ; second pulse if bit is 0
-
- ; repeat until 8 bits are sent
-
- ADDS r5,r5,r5
- BCC %05
-
-; Repeat for all the bytes to be sent (1 or 4)
-
- ADDS r6,r6,r6
- BCC %01
-
-; Go to TXRDY to ensure the host sees the transmit request
-
- LDR r3,%08 ; delay before sending pattern
- ADD pc,pc,r0
-08
- & ts_recover_time
-09 ADDS r3,r3,r3 ; 16-loop delay
- BCC %09
-
- LDR r3,[r2]
- ADDS r3,r3,r1 ; dummy - space between pulses
- LDR r3,[r2]
- ADDS r3,r3,r1
- LDR r3,[r2]
-
-; All sent - r14 holds the caller's return address
-10
- ADD pc,r0,r14
-
-
-
-;
-; Reporting primitive
-;
-; - Send the text (nul-terminated, at r4) to the display
-;
-; Interface registers need to be set up : this function is called from test
-; code rather than external interface code.
-;
-; The display is assumed to be a standard 16 character LCD module using
-; the Hitachi HD44780 display controller.
-; The 16-digit module uses a single 44780. This is an abnormal use of the
-; controller, and requires it to be set to two-line mode, with the first
-; 8 displayed characters on the first 'line', and the second 8 on the
-; second 'line'. Characters sent to the second line must be written at
-; character position 40 +. In order to permit different modules to be
-; fitted to later adapters, it is suggested that the first 7 characters
-; be treated as a 'title' line, and the second 8 as a 'comment' line.
-; A space should always be placed at the end of the title line to
-; split the display fields, unless there is no 'comment' line.
-; Do not display characters across the two areas as though they adjoined
-; (even though they do :-) ).
-;
-; The controller is operated in its 4-bit mode, which allows the interface
-; to drive 4 bits of alpha information and 4 bits of control information.
-; The bits in a transmitted byte are assigned as :
-;
-; bit 0 - D4 } 4-bit mode data bus
-; 1 - D5 }
-; 2 - D6 }
-; 3 - D7 }
-;
-; 4 - RS Register Select : 0 for control, 1 for data
-;
-; 5 - } Unassigned
-; 6 - }
-;
-; 7 - CPEN Interface control : 0 for enable,
-; 1 for disable
-;
-; For each message sent, the display is first initialised, using the
-; following sequence (each byte is sent as 2 bytes, high nibble first,
-; with RS clear in bit 4 of each byte)
-; After each byte, an RD operation is performed : this is used by the
-; interface hardware to strobe the data into the display.
-;
-;
-; The message addressed by r4 is then sent (data mode : RS set in each byte)
-; until a 0 byte is encountered.
-;
-
-;
-; This is the command sequence sent to initialise the display
-;
-
-ts_initialise
- = &30,&30,&30,&20 ; power-up initialisation
- = &20,&80 ; 4 bit mode, two line, Font 0
- = &00,&C0 ; Display on, no cursor visible
- = &00,&60 ; Incrementing display position, no shift
- = &80,&00 ; Set DD RAM address 0
- = &00,&20 ; Cursor home
- = &00,&10 ; Display clear
-ts_initialise_end
-
- ASSERT ((ts_initialise_end - ts_initialise) / 2) < 32
-
-
-;
-; This is the command sequence sent when continuation text is sent
-;
-
-ts_extend
- = &00,&C0 ; Display on, cursor invisible
- = &00,&60 ; Incrementing display position, no shift
-ts_extend_end
-
- ASSERT ((ts_extend_end - ts_extend) / 2) < 32
-
-;
-; One of these commands are sent when offset text is required
-;
-
-ts_offset_table
- = &80,&00 ; Set DD RAM address 0
-ts_offset_table_1
- = &80,&10 ; Set DD RAM address 1
- = &80,&20 ; Set DD RAM address 2
- = &80,&30 ; Set DD RAM address 3
- = &80,&40 ; Set DD RAM address 4
- = &80,&50 ; Set DD RAM address 5
- = &80,&60 ; Set DD RAM address 6
- = &80,&70 ; Set DD RAM address 7
- = &C0,&00 ; Set DD RAM address 40
- = &C0,&10 ; Set DD RAM address 41
- = &C0,&20 ; Set DD RAM address 42
- = &C0,&30 ; Set DD RAM address 43
- = &C0,&40 ; Set DD RAM address 44
- = &C0,&50 ; Set DD RAM address 45
- = &C0,&60 ; Set DD RAM address 46
- = &C0,&70 ; Set DD RAM address 47
-
-
-; This assertion is forced by the code : each sequence assumed 2 bytes.
-
- ASSERT ((ts_offset_table_1 - ts_offset_table) = 2)
-
-
-
- ALIGN
-
-;
-; Here starts the code ...
-;
-
-ts_SendQuit ROUT ; put this code BEFORE %16
- ADD pc,r0,r14 ;
-
-
-
-;
-; Entry point for initialising the display and sending r4 text.
-;
-
-
-ts_SendText ROUT
-
-;
-; Point to the command sequence to setup and clear the display
-;
-
- LDR r0,%10 ; set zero in r0
- ADD pc,pc,r0
-10
- & 0
- LDR r7,%11 ; pointer to init sequence
- ADDS r7,pc,r7
- ADD pc,pc,r0
-11
- & (ts_initialise - .)
- LDR r6,%12 ; length of init sequence
- ADD pc,pc,r0
-12
- & (1 :SHL: (32 - (ts_initialise_end - ts_initialise)))
- B ts_SendLCDCmd
-
-
-;
-; Entry point for adding text to current cursor position
-;
-
-ts_MoreText ROUT
-
- LDR r0,%10 ; set zero in r0
- ADD pc,pc,r0
-10
- & 0
- LDR r7,%11 ; pointer to command sequence
- ADDS r7,pc,r7
- ADD pc,pc,r0
-11
- & (ts_extend - .)
- LDR r6,%12 ; length of command sequence
- ADD pc,pc,r0
-12
- & (1 :SHL: (32 - (ts_extend_end - ts_extend)))
- B ts_SendLCDCmd
-
-
-ts_PosText ROUT
-
-;
-; Entry point for adding text at a specific cursor position
-; Used iteratively by SendText, etc if cursor position command found.
-; Offset into display is given in r6.
-;
-
- LDR r0,%10 ; set zero in r0
- ADD pc,pc,r0
-10
- & 0
- LDR r7,%11 ; pointer to command sequence
- ADDS r7,pc,r7
- ADD pc,pc,r0
-11
- & (ts_offset_table - .) ; offset * 2 into table of
- ADDS r6,r6,r6 ; offset command sequences
- ADDS r7,r7,r6
-
- LDR r6,%12 ; length of command sequence
- ADD pc,pc,r0
-12
- & (1 :SHL: (32 - 2))
-
-
-;
-; Entry point for writing arbitrary command strings.
-; Set r7 to point to command string, r6 length (as tables above),
-; Set r4 to point to following Data string (null-terminated).
-;
-
-ts_SendLCDCmd
-
- LDR r0,%01 ; set zero in r0
- ADD pc,pc,r0
-01
- & 0
- LDR r1,%02 ; set FFFFFFFF in r1
- ADD pc,pc,r0 ;(test value : sets carry when added to non-zero)
-02
- & (-1)
- LDR r2,%03 ; set pointer to test address
- ADD pc,pc,r0 ;(points to aliased copy of a zero word)
-03
- & (ts_Alias_bits + (%01 - %04))
- ADDS r2,pc,r2 ; adjust r2 for ROM-relative address
- ADDS r0,r0,r0 ; dummy (to keep labels nearby !)
-04 ; where pc points when added to r2
-
-
-; Wait - gap between successive WS attempts or successive bytes
-
-ts_send_command_byte ROUT
-
- LDR r3,%14
- ADD pc,pc,r0
-14
- & ts_recover_time
-15 ADDS r3,r3,r3 ; 16-loop delay
- BCC %15
- LDR r1,%16 ; reload test register
- ADD pc,pc,r0
-16
- & (-1)
-
- LDR r3,[r2] ; Test for adapter ready for data
- ADDS r3,r3,r1 ; (adapter detects WS operation)
- BCC ts_SendQuit ; skip output : adapter not present
- ; (backward jump helps ensure LDR r3,[r2]
- ; only reads zero when adapter absent
- LDR r3,[r2] ; since previous bus data is nonzero)
- ADDS r3,r3,r1
- LDR r3,[r2]
- ADDS r3,r3,r1
- BCC ts_send_command_byte ; loop back until adapter is ready
-
-; Adapter ready - loop around all the bits in the byte
-
-
- LDR r5,%21 ; load byte-shift counter ...
- ADD pc,pc,r0 ; ... and bits-per-byte counter
-21
- & (1 :SHL: 8) + 1 ; 24 shifts + 8 shifts
- LDRB r1,[r7]
-22 ADDS r1,r1,r1 ; shift byte up into m.s.d.
- ADDS r5,r5,r5
- BCC %22
-
- ; Send a single bit : 1 pulse for 1, 2 pulses for 0
-
-23 LDR r3,[r2]
- ADDS r1,r1,r1 ; shift current bit into Carry
- LDRCC r3,[r2] ; second pulse if bit is 0
-
- ; and wait for the inter-bit time
-
- LDR r3,%24
- ADD pc,pc,r0
-24
- & ts_recover_time
-25 ADDS r3,r3,r3 ; 16-loop delay
- BCC %25
-
- ; repeat until 8 bits are sent
-
- ADDS r5,r5,r5
- BCC %23
-
- ; do a RD operation to strobe the data out
-
- LDR r5,%26
- ADD pc,pc,r0
-26
- & (1 :SHL: (32 - 12))
-27
- LDR r3,[r2]
- ADDS r5,r5,r5
- BCC %27
-
-; Repeat for all the bytes to be sent (ts_initialise_end - ts_initialise)
-
- LDR r3,%33
- ADD pc,pc,r0
-33
- & 1
- ADDS r7,r7,r3 ; bump the pointer
- ADDS r6,r6,r6 ; bump the counter (shift left)
- BCC ts_send_command_byte
-
-
-;
-; Then send all the display bytes (in 4-bit mode) until a nul-terminator
-; is reached.
-;
-
-;
-; Send a single character (as two separate 4-bit fields)
-; First, look to see if it's one of :
-;
-; NUL - end of text string
-; 0x80 - 0xfe - cursor positioning
-; 0xff - introduce a hex digit
-;
-
-ts_send_text_byte ROUT
-
- LDR r1,%40 ; reload test register
- ADD pc,pc,r0
-40
- & (-1)
-
- LDRB r7,[r4]
- ADDS r3,r7,r1 ; test for nul terminator
- BCC ts_SendEnd
-
-;
-; Byte isn't null. Check for >= 0x80.
-;
-
- LDR r6,%42 ; test for cursor control
- ADD pc,pc,r0
-42
- & (-&80) ; &8x means column x.
- ADDS r6,r7,r6
- BCC ts_printable_char ; < &80 : write a character
-
-;
-; Carry set : r6 now holds (value - 0x80). Check for numeric escape (&ff).
-;
- LDR r3,%43
- ADD pc,pc,r0
-43
- & (-&7f)
- ADDS r3,r6,r3
- BCC %47
-
-;
-; Carry set : fetch a nybble from the top of r8 and display that.
-;
-
- ADDS r8,r8,r8
- ADCS r6,r0,r0
- ADDS r8,r8,r8
- ADCS r6,r6,r6
- ADDS r8,r8,r8
- ADCS r6,r6,r6
- ADDS r8,r8,r8
- ADCS r6,r6,r6
-
- LDRB r7,[pc,r6]
- B ts_printable_char
-45
- = "0123456789ABCDEF"
-
-;
-; Not &ff : r6 holds cursor positioning offset (< &80). Skip over
-; the cursor control byte and iterate thro' PosText to move
-; typing position.
-;
-
-47
- LDR r3, %48
- ADD pc,pc,r0
-48
- & 1
- ADDS r4,r3,r4
- B ts_PosText
-
-;
-; Character is normal text : write it to the LCD.
-; The shift loop is used to generate the inter-byte delay normally
-; provided by ts_recover_time. Always make sure this is long enough.
-;
-
-ts_printable_char
-
- ADDS r6,r0,r7 ; take a copy of character
- LDR r5,%51 ; load byte-shift counter ...
- ADD pc,pc,r0 ; ... and bits-per-byte counter
-51 ; as a bitmask of the shift pattern
- & (1:SHL:8)+(1:SHL:4)+1 ; 24 shifts + 4 shifts + 4 shifts
-52 ADDS r6,r6,r6 ; shift byte up into m.s.d.
- ADDS r0,r0,r0 ; slow this loop down - ensure it's
- ADDS r0,r0,r0 ; always slower than ts_recover_time
- ADDS r5,r5,r5
- BCC %52
-
- LDR r3,[r2] ; Test for adapter ready for data
- ADDS r3,r3,r1 ; (adapter detects WS operation)
- LDR r3,[r2]
- ADDS r3,r3,r1
- LDR r3,[r2]
- ADDS r3,r3,r1
- BCC ts_printable_char ; loop back until adapter is ready
-
-; Adapter ready - loop around all the bits in the byte
-
-ts_send_tbit_upper
-
- ; wait for the inter-bit time
-
- LDR r3,%55
- ADD pc,pc,r0
-55
- & ts_recover_time
-56 ADDS r3,r3,r3 ; 16-loop delay
- BCC %56
-
- ; Send a single bit : 1 pulse for 1, 2 pulses for 0
-
- LDR r3,[r2]
- ADDS r6,r6,r6 ; shift current bit into Carry
- LDRCC r3,[r2] ; second pulse if bit is 0
-
- ; repeat until upper 4 bits are sent
-
- ADDS r5,r5,r5
- BCC ts_send_tbit_upper
-
- ; then send the interface control bits
-
- LDR r1,%57
- ADD pc,pc,r0
-57
- & (8 :SHL: 28) ; assert RS control pin
-
-ts_send_cbit_upper
-
- ; wait for the inter-bit time
-
- LDR r3,%58
- ADD pc,pc,r0
-58
- & ts_recover_time
-59 ADDS r3,r3,r3 ; 16-loop delay
- BCC %59
-
- ; Send a single bit : 1 pulse for 1, 2 pulses for 0
-
- LDR r3,[r2]
- ADDS r1,r1,r1 ; shift current bit into Carry
- LDRCC r3,[r2] ; second pulse if bit is 0
- ADDS r5,r5,r5
- BCC ts_send_cbit_upper
-
-;
-; do a RD operation to strobe the data out
-;
-
- LDR r3,%61
- ADD pc,pc,r0
-61
- & ts_recover_time
-62 ADDS r3,r3,r3 ; 16-loop delay
- BCC %62
-
- LDR r5,%63
- ADD pc,pc,r0
-63
- & (1 :SHL: (32 - 12))
-64
- LDR r3,[r2]
- ADDS r5,r5,r5
- BCC %64
-
- ; prepare to send the lower 4 bits out
-
- LDR r5,%70 ; bitcount mask for 4 data bits
- ADD pc,pc,r0 ; and 4 interface control bits
-70
- & (((1 :SHL: 4) + 1) :SHL: 24)
-
-ts_send_text_lower
- LDR r3,%71
- ADD pc,pc,r0
-71
- & ts_recover_time
-72 ADDS r3,r3,r3 ; 16-loop delay
- BCC %72
-
- LDR r1,%73
- ADD pc,pc,r0
-73
- & (-1)
-
- LDR r3,[r2] ; Test for adapter ready for data
- ADDS r3,r3,r1 ; (adapter detects WS operation)
- LDR r3,[r2]
- ADDS r3,r3,r1
- LDR r3,[r2]
- ADDS r3,r3,r1
- BCC ts_send_text_lower ; loop back until adapter is ready
-
-ts_send_tbit_lower
-
- ; wait for the inter-bit time
-
- LDR r3,%76
- ADD pc,pc,r0
-76
- & ts_recover_time
-77 ADDS r3,r3,r3 ; 16-loop delay
- BCC %77
-
- ; Send a single bit : 1 pulse for 1, 2 pulses for 0
-
- LDR r3,[r2]
- ADDS r6,r6,r6 ; shift current bit into Carry
- LDRCC r3,[r2] ; second pulse if bit is 0
-
- ; repeat until lower 4 bits are sent
-
- ADDS r5,r5,r5
- BCC ts_send_tbit_lower
-
-
- ; then send the interface control bits
-
- LDR r1,%78
- ADD pc,pc,r0
-78
- & (8 :SHL: 28) ; assert RS control pin
-
-ts_send_cbit_lower
-
- ; wait for the inter-bit time
-
- LDR r3,%80
- ADD pc,pc,r0
-80
- & ts_recover_time
-81 ADDS r3,r3,r3 ; 16-loop delay
- BCC %81
-
- ; Send a single bit : 1 pulse for 1, 2 pulses for 0
-
- LDR r3,[r2]
- ADDS r1,r1,r1 ; shift current bit into Carry
- LDRCC r3,[r2] ; second pulse if bit is 0
-
- ADDS r5,r5,r5
- BCC ts_send_cbit_lower
-
-;
-; do a RD operation to strobe the data out
-;
-
- ; wait for the inter-bit time
-
- LDR r3,%82
- ADD pc,pc,r0
-82
- & ts_recover_time
-83 ADDS r3,r3,r3 ; 16-loop delay
- BCC %83
-
- LDR r5,%84
- ADD pc,pc,r0
-84
- & 1 :SHL: (32 - 12)
-85
- LDR r3,[r2]
- ADDS r5,r5,r5
- BCC %85
-
-; Repeat for all the bytes to be sent (until nul terminator is found)
-
- LDR r3,%86
- ADD pc,pc,r0
-86
- & 1
- ADDS r4,r3,r4 ; bump text pointer
- B ts_send_text_byte
-
-;
-; Wait for about 1 seconds worth of LCD operation delays to
-; permit the operator to read the text.
-; Use of the interface's monitor allows this delay to be increased
-; or decreased externally.
-;
-
-ts_SendEnd ROUT
-
- LDR r7, %01
- ADD pc,pc,r0
-01
- & (ts_pause_time + 1) ; must be an odd number
- ; to ensure pairs of zeros
- ASSERT ((ts_pause_time :AND: 1) = 0)
-
-02
- LDR r3,%03
- ADD pc,pc,r0
-03
- & ts_recover_time
-04 ADDS r3,r3,r3 ; 16-loop delay
- BCC %04
- LDR r1,%05 ; reload test register
- ADD pc,pc,r0
-05
- & (-1)
-
- LDR r3,[r2] ; Test for adapter ready for data
- ADDS r3,r3,r1 ; (adapter detects WS operation)
- BCC ts_SendQuit ; skip output : adapter not present
- LDR r3,[r2]
- ADDS r3,r3,r1
- LDR r3,[r2]
- ADDS r3,r3,r1
- BCC %02 ; loop back until adapter is ready
-
-; Adapter ready - loop around all the bits in the byte
-; Note that each byte is actually 4 bits to the LCD module,
-; so a even number must be sent or the display will get out
-; of sync until the next display reset sequence.
-
- LDR r5,%10 ; bits-per-byte counter
- ADD pc,pc,r0
-10
- & (1 :SHL: 24)
- LDR r3,%11
- ADD pc,pc,r0
-11
- & ts_recover_time ; wait before sending data bits
-12 ADDS r3,r3,r3 ; for byte timing.
- BCC %12
-
- ; Send a single bit : always 2 pulses for 0
-
-13 LDR r3,[r2]
- LDR r3,[r2]
-
- ; and wait for the inter-bit time
-
- LDR r3,%14
- ADD pc,pc,r0
-14
- & ts_recover_time
-15 ADDS r3,r3,r3 ; 16-loop delay
- BCC %15
-
- ; repeat until 8 bits are sent
-
- ADDS r5,r5,r5
- BCC %13
-
- ; do a RD operation to strobe the data out
-
- LDR r5,%16
- ADD pc,pc,r0
-16
- & 1 :SHL: (32 - 12)
-17
- LDR r3,[r2]
- ADDS r5,r5,r5
- BCC %17
-
- ; repeat until a sufficient number of nuls are done
-
- ADDS r7,r7,r1 ; count down loop counter
- BCS %02
-
- ADD pc,r0,r14 ; back to caller
-
-
- END
diff --git a/OldTestSrc/Ioc b/OldTestSrc/Ioc
deleted file mode 100644
index 5ec8b152fdf554b2189b3c4302c3bfcde1514918..0000000000000000000000000000000000000000
--- a/OldTestSrc/Ioc
+++ /dev/null
@@ -1,92 +0,0 @@
-; > TestSrc.IOC
-
- TTL RISC OS 2+ POST IO controller
-;
-; This initial IOC test simply reports the content of the IRQ and FIRQ
-; registers, to show any unexpected pending IRQs.
-; Certain of these should really be cleared, and the effect of an
-; interrupt tested.
-;
-;------------------------------------------------------------------------
-; History
-;
-; Date Name Comment
-; ---- ---- -------
-; 18-Dec-89 ArtG Initial version
-; 29-Nov-91 ArtG Added IOC bus test using mask registers
-; 20-Jun-93 ArtG Modified for 29-bit IOMD test
-;
-;
-;------------------------------------------------------------------------
-
- [ IO_Type = "IOMD"
-ts_IObase * IOMD_Base
-ts_IOmask * &1fffffff
-ts_IOreg1 * IOMD_VIDCUR
-ts_IOreg2 * IOMD_VIDSTART
-ts_IObswap * 32
-ts_IOMD_ID * &D4E7
- |
-ts_IObase * IOC
-ts_IOmask * &ff0000
-ts_IOreg1 * IOCIRQMSKA
-ts_IOreg2 * IOCIRQMSKB
-ts_IObswap * 16
- ]
-
-ts_IOCreg
- MOV r0,#0 ; zero error accumulator
- LDR r3, =ts_IObase
- MOV r1,#(1 :SHL: 31) ; initialise bit-set test mask
-0
- MVN r2,r1 ; make bit-clear test mask
- ANDS r4,r1,#ts_IOmask
- BEQ %FT1 ; skip if this bit isn't tested
- STR r1,[r3,#ts_IOreg1]
- STR r2,[r3,#ts_IOreg2]
- LDR r4,[r3,#ts_IOreg1]
-; EOR r4, r4, r1, LSR #ts_IObswap ; check bit-set test was OK
- EOR r4, r4, r1 ; check bit-set test was OK
- ORR r0, r0, r4 ; accumulate errors in r0
- LDR r4,[r3,#ts_IOreg2]
-; EOR r4, r4, r2, LSR #ts_IObswap ; check bit-clear test was OK
- EOR r4, r4, r2 ; check bit-clear test was OK
- ORR r0, r0, r4 ; accumulate errors in r0
-1
- MOV r1, r1, LSR #1 ; shift mask downwards
- TEQ r1,#0
- BNE %BT0 ; and loop until all bits tested
-
- ANDS r8, r0, #ts_IOmask
- MOV pc,r14 ; return error if any bit failed
-
-ts_IOCstat
- LDR r3, =ts_IObase
- MOV r0,#0
- [ IO_Type = "IOMD"
- LDRB r1,[r3,#IOMD_ID1]
- ORR r0,r0,r1, LSL #(32-24)
- LDRB r1,[r3,#IOMD_ID0]
- ORR r0,r0,r1
- LDR r1,=ts_IOMD_ID
- CMPS r0,r1 ; check IOMD identity
- MOV r0,r0,LSL #16
- LDRB r1,[r3,#IOMD_VERSION]
- ORR r8,r0,r1, LSL #12
- MOV pc,r14
- |
- LDRB r1,[r3,#IOCControl]
- ORR r0,r0,r1, LSL #(32 - 8)
- LDRB r1,[r3,#IOCIRQSTAA]
- ORR r0,r0,r1, LSL #(32 - 16)
- LDRB r1,[r3,#IOCIRQSTAB]
- ORR r0,r0,r1, LSL #(32 - 24)
- LDRB r1,[r3,#IOCFIQSTA]
- ORR r8,r0,r1
- ANDS r1,r1,#0 ; return zero flag (OK)
-
- MOV pc,r14
- ]
-
- END
-
diff --git a/OldTestSrc/MEMC1 b/OldTestSrc/MEMC1
deleted file mode 100644
index 847df36843534aee6f4bee0f4244300f5e4bff17..0000000000000000000000000000000000000000
--- a/OldTestSrc/MEMC1
+++ /dev/null
@@ -1,552 +0,0 @@
-; > MEMC1
-
-; MEMC interface file - MEMC1 version
-
-; Created by TMD 10-Aug-90
-
-VInit * &03600000
-VStart * &03620000
-VEnd * &03640000
-CInit * &03660000
-; SStart * &03680000
-; SEnd * &036A0000
-; SPtr * &036C0000
-
-; *****************************************************************************
-;
-; SetDAG - Program DMA address generator R1 with physical address R0
-;
-; in: r0 = physical address
-; r1 = index of DMA address generator to program, as defined in vdudecl
-;
-; out: All registers preserved, operation ignored if illegal
-;
-
- [ {FALSE}
-SetDAG ENTRY "r0"
- CMP r1, #MEMCDAG_MaxReason
- EXIT HI
- ADR r14, DAGAddressTable
- LDR r14, [r14, r1, LSL #2] ; load base address in MEMC1
- MOV r0, r0, LSR #4 ; bottom 4 bits irrelevant
- CMP r0, #(1 :SHL: 15) ; ensure in range
- ORRCC r14, r14, r0, LSL #2
- STRCC r14, [r14] ; any old data will do
- EXIT
-
- GBLA DAGIndex
-DAGIndex SETA 0
-
- MACRO
- DAGTab $reason, $address
- ASSERT ($reason)=DAGIndex
- & $address
-DAGIndex SETA DAGIndex + 1
- MEND
-
-DAGAddressTable
- DAGTab MEMCDAG_VInit, VInit
- DAGTab MEMCDAG_VStart, VStart
- DAGTab MEMCDAG_VEnd, VEnd
- DAGTab MEMCDAG_CInit, CInit
- ]
-;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-; CAM manipulation utility routines
-
-BangCamUpdate ROUT
-
-; R2 = CAM entry no
-; R3 = logaddr
-; R9 = current MEMC value
-; R11 = PPL
-; set and update tables
-
- MOV R4, #0
- LDR R4, [R4, #CamEntriesPointer]
- ORR r0, r3, r11, LSL #28 ; top nibble is PPL
- STR r0, [R4, R2, LSL #2]
-
-BangCam
-
-; r0 corrupted
-; r1 corrupted
-; R2 = CAM entry no
-; R3 = logaddr
-; r4 corrupted
-; r5 spare!
-; r6 corrupted
-; r7, r8 spare
-; R9 = current MEMC value
-; r10 spare
-; R11 = PPL
-; r12 spare
-
- AND R4, R9, #&C ; pagesize
- ADR R0, PageMangleTable
- LDR R0, [R0, R4] ; load data table pointer
- MOV R4, #0
-01 LDR R1, [R0], #4
- CMP R1, #-1
- BEQ %FT02
- AND R6, R2, R1
- LDR R1, [R0], #4
- CMP R1, #0
- RSBMI R1, R1, #0
- ORRPL R4, R4, R6, LSL R1
- ORRMI R4, R4, R6, LSR R1
- B %BT01
-
-02 LDR R1, [R0], #4
- CMP R1, #-1
- BEQ %FT03
- AND R6, R3, R1
- LDR R1, [R0], #4
- CMP R1, #0
- RSBMI R1, R1, #0
- ORRPL R4, R4, R6, LSL R1
- ORRMI R4, R4, R6, LSR R1
- B %BT02
-
-03 ORR R4, R4, #CAM
- ORR R4, R4, R11, LSL #8 ; stuff in PPL
- STR R4, [R4] ; and write it
- MOV PC, LR
-
-; Data to drive CAM setting
-
-PageMangleTable
- & PageMangle4K
- & PageMangle8K
- & PageMangle16K
- & PageMangle32K
-
-; For each page size, pairs of masks and shift factors to put the bits in the
-; right place. Two sets: operations on Physical Page Number, operations on
-; Logical Page Number.
-
-; Shifts are Shift Left values (<<). Each section terminated by -1
-
-PageMangle4K
-; PPN:
- & 2_011111111
- & 0 ; bits in right place
- & -1
-; LPN:
- & 2_1100000000000:SHL:12
- & (11-12)-12 ; LPN[12:11] -> A[11:10]
- & 2_0011111111111:SHL:12
- & (22-10)-12 ; LPN[10:0 ] -> A[22:12]
- & -1
-
-PageMangle8K
-; PPN:
- & 2_010000000
- & 7-7 ; PPN[7] -> A[7]
- & 2_001000000
- & 0-6 ; PPN[6] -> A[0]
- & 2_000111111
- & 6-5 ; PPN[5:0] -> A[6:1]
- & -1
-; LPN:
- & 2_110000000000:SHL:13
- & (11-11)-13 ; LPN[11:10] -> A[11:10]
- & 2_001111111111:SHL:13
- & (22-9)-13 ; LPN[9:0] -> A[22:13]
- & -1
-
-PageMangle16K
-; PPN:
- & 2_010000000
- & 7-7 ; PPN[7] -> A[7]
- & 2_001100000
- & 1-6 ; PPN[6:5] -> A[1:0]
- & 2_000011111
- & 6-4 ; PPN[4:0] -> A[6:2]
- & -1
-; LPN:
- & 2_11000000000:SHL:14
- & (11-10)-14 ; LPN[10:9] -> A[11:10]
- & 2_00111111111:SHL:14
- & (22-8)-14 ; LPN[8:0] -> A[22:14]
- & -1
-
-PageMangle32K
-; PPN:
- & 2_100000000
- & 12-8 ; PPN[8] -> A[12]
- & 2_010000000
- & 7-7 ; PPN[7] -> A[7]
- & 2_001000000
- & 1-6 ; PPN[6] -> A[1]
- & 2_000100000
- & 2-5 ; PPN[5] -> A[2]
- & 2_000010000
- & 0-4 ; PPN[4] -> A[0]
- & 2_000001111
- & 6-3 ; PPN[3:0] -> A[6:3]
- & -1
-; LPN:
- & 2_1100000000:SHL:15
- & (11-9)-15 ; LPN[9:8] -> A[11:10]
- & 2_0011111111:SHL:15
- & (22-7)-15 ; LPN[7:0] -> A[22:15]
- & -1
-
-PageSizes
- & 4*1024 ; 0 is 4K
- & 8*1024 ; 4 is 8K
- & 16*1024 ; 8 is 16
- & 32*1024 ; C is 32
-
-PageShifts
- = 12, 13, 0, 14 ; 1 2 3 4
- = 0, 0, 0, 15 ; 5 6 7 8
-
-; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-; SWI OS_UpdateMEMC: Read/write MEMC1 control register
-
-SSETMEMC ROUT
-
- AND r10, r0, r1
- MOV r12, #0
- TEQP pc, #SVC_mode+I_bit+F_bit
- LDR r0, [r12, #MEMC_CR_SoftCopy] ; return old value
- BIC r11, r0, r1
- ORR r11, r11, R10
- BIC r11, r11, #&FF000000
- BIC r11, r11, #&00F00000
- ORR r11, r11, #MEMCADR
- STR r11, [r12, #MEMC_CR_SoftCopy]
- STR r11, [r11]
- TEQP pc, #SVC_mode+I_bit
- ExitSWIHandler
-
-; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-;
-; ClearPhysRAM - Routine to clear "all" memory
-;
-; While this routine is running, keyboard IRQs may happen. For this reason
-; it avoids LogRAM 0..31 (where hardware IRQ vector is) and PhysRAM
-; 0..31 where the IRQ workspace is.
-;
-
-ClearPhysRAM ROUT
- MOV R0, #0
- MOV R1, #0
- MOV R2, #0
- MOV R3, #0
- MOV R4, #0
- MOV R5, #0
- MOV R6, #0
- MOV R11, #0
- MOV R8, #PhysRam
- CMP R13, #512*1024
- ADDEQ R10, R8, #(512-64)*1024 ; get address that's logram 0
- ADDNE R10, R8, #512*1024
- ADD R13, R13, #PhysRam ; end of memory
- ADD R8, R8, #4*8 ; skip minimal startup workspace
-10 CMP R8, R10
- ADDEQ R8, R8, #4*8 ; skip physram that's logram 0
- STMNEIA R8!, {R0-R6, r11}
- CMP R8, R13
- BNE %BT10
- SUB R13, R13, #PhysRam
-
- LDR R0, =OsbyteVars + :INDEX: LastBREAK
- MOV R1, #&80
- STRB R1, [R0] ; flag the fact that RAM cleared
- MOV pc, lr
-
-; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-;
-; InitMEMC - Initialise memory controller
-;
-
-InitMEMC ROUT
- LDR R0, ResetMemC_Value
- STR R0, [R0] ; set ROM access times, refresh on flyback, no DMA
- MOV pc, lr
-
-; -> MemSize
-
-; (non-destructive) algorithm to determine MEMC RAM configuration
-;
-; Dave Flynn and Alasdair Thomas
-; 17-March-87
-;
-; Spooling checkered by NRaine and SSwales !
-; 8MByte check bodged in by APT
-;
-; NOTE: Routines MemSize and TimeCPU are called by the power-on test software,
-; so their specifications MUST not change.
-;
-; Set MEMC for 32-k page then analyse signature of possible
-; external RAM configurations...
-; The configurations are:
-;
-; Ram Size Page Size Configuration (Phys RAM) Signature
-;--------------------------------------------------------------------
-; 16MByte 32k 4*32*1Mx1 A13,A20,A21,A22,A23,A23.5 distinct
-; 16MByte 32k 16*8*256kx4 A13,A20,A21,A22,A23,A23.5 distinct
-;
-; 12MByte 32k 3*32*1Mx1 A13,A20,A21,A22,A23 OK, A23.5 fail
-; 12MByte 32k 12*8*256kx4 A13,A20,A21,A22,A23 OK, A23.5 fail
-;
-; 8MByte 32k 2*32*1Mx1 A13,A20,A21,A22 distinct, A23 fail
-; 8MByte 32k 8*8*256kx4 A13,A20,A21,A22 distinct, A23 fail
-;
-; 4Mbyte 32k 32*1Mx1 A13,A21,A20 distinct, A22,A23 fail
-; 4Mbyte 32k 4*8*256kx4 A13,A21,A20 distinct, A22,A23 fail
-;
-; 2Mbyte 32k expandable 2*8*256kx4 A13,A20 distinct, A21 fails
-; 2Mbyte ??? 16k fixed 2*8*256kx4 A13,A21 distinct, A20 fails
-;
-; 1Mbyte 8k 32*256kx1 A13,A20 fail, A19,A18,A12 distinct
-; 1Mbyte 8k 8*256kx1 A13,A20 fail, A19,A18,A12 distinct
-; 1Mbyte 8k 4*8*64kx4 A13,A20 fail, A19,A18,A12 distinct
-;
-; 512Kbyte 8k expandable 2*8*64kx4 A13,A20,A19 fail, A12,A18 distinct
-; 512Kbyte 4k fixed 2*8*64kx4 A13,A20,A12 fail, A19,A18 distinct
-;
-; 256Kbyte 4K 8*64kx4 A13,A20,A12,A18 fail, A21,A19 ok
-; 256Kbyte 4K 32*64kx1 A13,A20,A12,A18 fail, A21,A19 ok
-;
-
-Z_Flag * &40000000
-
-; MemSize routine... enter with 32K pagesize set
-; R0 returns page size
-; R1 returns memory size
-; R2 returns value set in MEMC
-; uses R3-R7
-
-MemSize ROUT
- MOV r7, lr
- MOV r0, #PhysRam
- ADD r1, r0, #A13
- BL DistinctAddresses
- BNE %10
- ADD r1, r0, #A21
- BL DistinctAddresses
- MOVNE r0, #Page32K
- MOVNE r1, #2048*1024
- BNE MemSizeDone
-
- MOV r0, #PhysRam
- ADD r1, r0, #4*1024*1024
- BL DistinctAddresses
- MOVNE r0, #Page32K
- MOVNE r1, #4*1024*1024
- BNE MemSizeDone
-
- MOV r0, #PhysRam
- ADD r1, r0, #8*1024*1024
- BL DistinctAddresses
- MOVNE r0, #Page32K
- MOVNE r1, #8*1024*1024
- BNE MemSizeDone
-
- MOV r0, #PhysRam
- ADD r1, r0, #12*1024*1024
- BL DistinctAddresses
- MOV r0, #Page32K
- MOVNE r1, #12*1024*1024
- MOVEQ r1, #16*1024*1024
- B MemSizeDone
-
-10 ADD r1, r0, #A20
- BL DistinctAddresses
- BNE %20
- MOV r0, #Page16K
- MOV r1, #2048*1024
- B MemSizeDone
-
-20 ADD r1, r0, #A19
- BL DistinctAddresses
- BEQ %30
- MOV r0, #Page8K
- MOV r1, #512*1024
- B MemSizeDone
-
-30 ADD r1, r0, #A18
- BL DistinctAddresses
- BEQ %40
- MOV r0, #Page4K
- MOV r1, #256*1024
- B MemSizeDone
-
-40 ADD r1, r0, #A12
- BL DistinctAddresses
- BEQ %50
- MOV r0, #Page4K
- MOV r1, #512*1024
- B MemSizeDone
-
-50 MOV r0, #Page8K
- MOV r1, #1024*1024
-
-MemSizeDone
- LDR r2, ResetMemC_Value
- BIC r2, r2, #&C
- ORR r2, r2, r0
- STR r2, [r2] ; set MEMC to right state
- MOV pc, r7
-
-
-; DistinctAddresses routine...
-; r0,r1 are the addresses to check
-; uses r2-5
-; writes interleaved patterns (to prevent dynamic storage...)
-; checks writing every bit low and high...
-; return Z-flag set if distinct
-
-DistinctAddresses ROUT
- LDR r2, [r0] ; preserve
- LDR r3, [r1]
- LDR r4, Pattern
- STR r4, [r0] ; mark first
- MOV r5, r4, ROR #16
- STR r5, [r1] ; mark second
- LDR r5, [r0]
- CMP r5, r4 ; check first
- BNE %10 ; exit with Z clear
- LDR r5, [r1] ; check second
- CMP r5, r4, ROR #16 ; clear Z if not same
- BNE %10
-; now check inverse bit writes
- STR r4, [r1] ; mark second
- MOV r5, r4, ROR #16
- STR r5, [r0] ; mark first
- LDR r5, [r1]
- CMP r5, r4 ; check second
- BNE %10 ; exit with Z clear
- LDR r5, [r0] ; check first
- CMP r5, r4, ROR #16 ; clear Z if not same
-10 STR r3, [r1] ; restore
- STR r2, [r0]
- ORREQ lr, lr, #Z_Flag
- BICNE lr, lr, #Z_Flag
- MOVS pc, lr
-
-Pattern
- & &AAFF5500 ; shiftable bit check pattern
-
-; init state with masked out page size
-
-ResetMemC_Value
- & &E010C :OR: MEMCADR ; slugged ROMs + flyback refresh only + 32K page
-
-; Constants
-;
-A21 * 1:SHL:21
-A20 * 1:SHL:20
-A19 * 1:SHL:19
-A18 * 1:SHL:18
-A13 * 1:SHL:13
-A12 * 1:SHL:12
-
-Page32K * &C ; in MEMC control reg patterns...
-Page16K * &8
-Page8K * &4
-Page4K * &0
-
-
-; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-; In r0-r6 trashable
-; r9 = Current MEMC CR
-
-; Out r9 MEMC value with slowest ROM speed, correct pagesize
-; r7 processor speed in kHz, tbs -> MEMC1a
-
-ncpuloops * 1024 ; don't go longer than 4ms without refresh !
-nmulloops * 128
-
-TimeCPU ROUT
-
- BIC r9, r9, #3 :SHL: 8
- STR r9, [r9] ; turn off refresh for a bit
-
-; Time CPU/Memory speed
-
- LDR r1, =&7FFE ; 32K @ 2MHz = ~16ms limit
- MOV r3, #IOC
-
- MOV r0, r1, LSR #8
- STRB r1, [r3, #Timer1LL]
- STRB r0, [r3, #Timer1LH]
- LDR r0, =ncpuloops
- STRB r0, [r3, #Timer1GO] ; start the timer NOW
- B %FT10 ; Looks superfluous, but is required
- ; to get ncpuloops pipeline breaks
-
-10 SUBS r0, r0, #1 ; 1S
- BNE %BT10 ; 1N + 2S
-
- STRB r0, [r3, #Timer1LR] ; latch count NOW
- LDRB r2, [r3, #Timer1CL]
- LDRB r0, [r3, #Timer1CH]
- ADD r2, r2, r0, LSL #8 ; count after looping is ...
-
- SUB r2, r1, r2 ; decrements !
- MOV r2, r2, LSR #1 ; IOC clock decrements at 2MHz
-
-; Time CPU/MEMC Multiply time
-
- MOV r4, #-1 ; Gives worst case MUL
-
- MOV r0, r1, LSR #8
- STRB r1, [r3, #Timer1LL]
- STRB r0, [r3, #Timer1LH]
- LDR r0, =nmulloops
- STRB r0, [r3, #Timer1GO] ; start the timer NOW
- B %FT20 ; Looks superfluous, but is required
- ; to get nmulloops pipeline breaks
-
-20 MUL r5, r4, r4 ; 1S + 16I
- MUL r5, r4, r4 ; 1S + 16I
- SUBS r0, r0, #1 ; 1S
- BNE %BT20 ; 1N + 2S
-
- STRB r0, [r3, #Timer1LR] ; latch count NOW
- LDRB r4, [r3, #Timer1CL]
- LDRB r0, [r3, #Timer1CH]
- ADD r4, r4, r0, LSL #8 ; count after looping is ...
-
- SUB r4, r1, r4 ; decrements !
- MOV r4, r4, LSR #1 ; IOC clock decrements at 2MHz
-
- ORR r9, r9, #1 :SHL: 8 ; set refresh on flyback
- STR r9, [r9] ; restore MEMC state a.s.a.p.
-
-; In ROM - each cpu loop took 4R cycles @ 8/f*500ns/cycle
-
- LDR r0, =4*(8*500/1000)*ncpuloops*1000
- DivRem r7, r0, r2, r1 ; r2 preserved
- MOV r0, #&80 ; At 8 MHz and below, run fast ROMs
- LDR r1, =8050 ; Over 8 MHz, need medium ROMs
- CMP r7, r1
- MOVHI r0, #&40
- LDR r1, =13000 ; Over 13 MHz, need slowest ROMs
- CMP r7, r1
- MOVHI r0, #&00
- ORR r9, r9, r0
- STR r9, [r9] ; Set ROM speed appropriately
-
- ASSERT ncpuloops = 8*nmulloops ; for given ratio cutoff <------------
-
- MOV r4, r4, LSL #10 ; *1024 to get resolution on divide
- DivRem r0, r4, r2, r1
- LDR r1, =1100 ; Cutoff point; MEMC1 longer than this
- CMP r0, r1
- ORRLO r7, r7, #1 :SHL: 16 ; Note MEMC1a prescence
-
- MOV pc, lr
-
-; Typical figures give (in ROM at 8MHz):
-
-; MEMC1 2048 CPU, 2432 MEMC -> MUL ratio 1216
-; MEMC1a 2048 864 432
-
-; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-
- END
diff --git a/OldTestSrc/Mem1IOMD b/OldTestSrc/Mem1IOMD
deleted file mode 100644
index f1b6a14ea10f568c6dc3079989535a0db79daa94..0000000000000000000000000000000000000000
--- a/OldTestSrc/Mem1IOMD
+++ /dev/null
@@ -1,481 +0,0 @@
-; > TestSrc.Mem1IOMD
-
- TTL RISC OS 2+ POST memory linetest
-;
-; This test code is used to perform basic integrity tests on DRAM.
-; It doesn't test all locations - just walks patterns through data
-; and address lines.
-;
-;------------------------------------------------------------------------
-; History
-;
-; Date Name Comment
-; ---- ---- -------
-; 1-Jun-93 ArtG Derived from Mem1 for use on Medusa
-;
-;
-;------------------------------------------------------------------------
-
-;
-; Test the data and address and byte strobe lines for uniqueness.
-;
-
- LTORG
- ROUT
-
-1
- = "VRAM :",0
-2
- = "VRAM-F",&88,&ff,&ff,&ff,&ff,&ff,&ff,&ff,&ff,0
-3
- = "DRAM ",&ff,":",0
-4
- = "Data :",0
-5
- = &88,&ff,&ff," MByte",0
-
- ALIGN
-
-ts_LineTest
-
- ADR r4,%BT1
- BL ts_SendText ; Start data line tests on VRAM
-
- MOV r0,#0
- MOV_fiq r9,r0 ; r9-fiq records VRAM or low DRAM address
-
- MOV r12, #IOMD_Base
- MOV r2, #IOMD_VREFCR_VRAM_256Kx64 :OR: IOMD_VREFCR_REF_16 ; assume 2 banks of VRAM by default
- STRB r2, [r12, #IOMD_VREFCR]
-
-; Find the size, using MemSize's method
-
- MOV r0, #VideoPhysRam ; point at VRAM
- ADD r1, r0, #A2 ; test A2
- BL DistinctAddresses
- MOVEQ r9, #2 ; we've got 2M of VRAM
- BEQ %FT21
-
- MOV r2, #IOMD_VREFCR_VRAM_256Kx32 :OR: IOMD_VREFCR_REF_16
- STRB r2, [r12, #IOMD_VREFCR]
- ADD r1, r0, #A2 ; check for any VRAM at all
- BL DistinctAddresses
- MOVEQ r9, #1 ; we've got 1M of VRAM
- MOVNE r9, #0 ; no VRAM
-21
- BNE %FT22
- MOV_fiq r9,r0 ; record VRAM address
- FAULT #R_VRAM ; indicate VRAM present
-
-; Report size .. if this is non-zero and the data line test fails,
-; RISC OS will have problems.
-
-22
- ADR r4,%BT5 ; Add size (in hex Mbyte)
- MOV r8,r9, LSL #24 ; to "VRam : " message
- BL ts_MoreText
-
-; Worked out what size VRAM is, and set up IOMD register.
-; Do a data line test on the resulting array, repeated at oddword address to
-; ensure both banks get tested with walking 0 and walking 1
-
- ADR r4,%BT4
- BL ts_SendText
- MOV r1, #VideoPhysRam
- BL ts_Dataline
- ADDEQ r1,r1,#4
- BLEQ ts_Dataline
- BEQ %FT25 ; looks OK - carry on with VRAM test
-;
-; Data line test failed. Report the bitmap that failed, then carry on.
-;
- ADR r4,%BT2
- MOV r8,r0 ; report data fault mask
- BL ts_SendText
- B %FT30
-
-;
-; If there was some VRAM found here, and it passed the dataline test,
-; do the address and bytestrobe tests on it too.
-;
-
-25
- ADRL r4,%FT75 ; announce start of address line test
- BL ts_SendText
- MOV r1,#VideoPhysRam
- MOV r0,r9,LSL #20 ; size in MB determined before dataline test
- BL ts_Addrline
- BEQ %FT26
- ADRL r4,%FT76 ; failed - report error mask
- MOV r8,r0
- BL ts_SendText
- FAULT #R_LINFAILBIT ; and record failure
- B %FT30
-26
- ADRL r4,%FT77 ; announce start of byte test
- BL ts_SendText
- MOV r1,#VideoPhysRam
- BL ts_Byteword
- ADDEQ r1,r1,#4 ; retest at an oddword boundary
- BLEQ ts_Byteword
- BEQ %FT27
- ADRL r4,%FT78 ; failed - report error mask
- MOV r8,r0,LSL #16
- BL ts_SendText
- FAULT #R_LINFAILBIT ; and record failure
-27
-
-
-; Similarly, test each DRAM bank in turn, reporting failures or sizes for each
-
-30
- MOV r11, #IOMD_DRAMCR_DRAM_Large * &55 ; set all banks to be large initially
- MOV r14, #IOMD_Base
- STRB r11, [r14, #IOMD_DRAMCR]
- MOV r0,#MMUC_D ; enable 32-bit addressing of data
- SetCop r0,CR_Control
-
- MOV r10, #0 ; indicate no RAM found yet
- MOV r9, #IOMD_DRAMCR_DRAM_Small ; bit to OR into DRAMCR
- MOV r12, #DRAM0PhysRam
-35
- MOV r8,r12,LSL #2 ; indicate bank under test
- AND r8,r8,#(3 :SHL: 28)
- ADR r4,%BT3
- BL ts_SendText
-
- MOV r8,#0 ; r8 indicates RAM found in this bank
- MOV r0, r12
- ADD r1, r12, #A10 ; this should be OK for both configurations
- BL DistinctAddresses
- BNE %FT50 ; [no RAM in this bank at all]
-
- MOV_fiq r2,r9 ; if this is the first bank of DRAM or VRAM,
- TEQS r2,#0 ; put it's address in r9_fiq
- BNE %FT36
- MOV_fiq r9,r0
-
-36 ADD r1, r12, #A11 ; test for 256K DRAM
- BL DistinctAddresses
- ORRNE r11, r11, r9 ; it is, so select small multiplexing
- MOVNE r14, #IOMD_Base
- STRNEB r11, [r14, #IOMD_DRAMCR] ; store new value of DRAMCR, so we can use memory immediately
- MOVNE r8, #1024*1024 ; must be 1Mbyte at this address
- BNE %FT50
-
-; it's bigger than 256K words, so test address lines A21-A25 in sequence
-; we assume that the size of each bank is a power of 2
-
- MOV r8, #A21 ; now go through address lines A21-A25
-40
- ADD r1, r12, r8 ; see if this address line is unique
- BL DistinctAddresses
- BNE %FT50 ; if we've failed then r8 is true size, so exit
- MOV r8, r8, LSL #1 ; else shift up to next
- TEQ r8, #A26 ; only test up to A25
- BNE %BT40
-
-50
- MOV r13,r8 ; remember size of this bank in bytes
- MOV r8,r13,LSL #(24 - 20) ; and display it in 2 digits, in MBytes.
- ADR r4,%BT5
- BL ts_MoreText
-
- ADRL r4,%FT73 ; announce data line test
- BL ts_SendText
- MOV r1,r12 ; do walking bit test
- BL ts_Dataline
- BEQ %FT55 ; looks OK, carry on to next bank
-
- ADRL r4,%FT74 ; bit test failed, so report it
- MOV r8,r0
- BL ts_SendText ; and bit fault mask
-
- CMPS r13,#0 ; was any RAM thought to be here ?
- BEQ %FT55
- FAULT #R_LINFAILBIT ; if so, it's faulty.
- MOV r13,#0 ; so ignore it
-55
-
-;
-; If there was some RAM found here, and it passed the dataline test,
-; do the address and bytestrobe tests on it too.
-;
- CMPS r13,#0
- BEQ %FT60
-
- ADR r4,%FT75 ; announce start of address line test
- BL ts_SendText
- MOV r1,r12 ; test address lines in this block
- MOV r0,r13
- BL ts_Addrline
- BEQ %FT56
- ADR r4,%FT76 ; failed - report error mask
- MOV r8,r0
- BL ts_SendText
- FAULT #R_LINFAILBIT ; and record failure
- MOV r13,#0 ; then forget this memory block
-
-56
- ADR r4,%FT77 ; announce start of byte test
- BL ts_SendText
- MOV r1,r12
- BL ts_Byteword
- BEQ %FT60
- ADR r4,%FT78 ; failed - report error mask
- MOV r8,r0,LSL #16
- BL ts_SendText
- FAULT #R_LINFAILBIT ; and record failure
- MOV r13,#0 ; then forget this memory block
-60
-
-
-; If the RAM found still seems OK, add it's size into the r10 accumulator
-; Working or not, carry on to check the next bank.
-
- ADD r10,r10,r13 ; accumulate DRAM if any found
- ADD r12, r12, #DRAM1PhysRam-DRAM0PhysRam ; move onto next bank
- MOV r9, r9, LSL #2 ; shunt up position in DRAMCR
- CMP r9, #&100 ; if more banks to do
- BCC %BT35 ; then loop
-
- ADR r4,%FT70
- BL ts_SendText ; None found .. print message
-
- MOVS r8,r10,LSL #(24 - 20) ; all finished ..
- ADREQ r4,%FT71 ; did we find any DRAM?
- ADRNE r4,%FT72
- BNE %FT65
- FAULT #R_LINFAILBIT ; fault if we didn't
-65
- BL ts_MoreText
- B ts_endline
-
-
-70
- = "DRAM",0
-71
- = &88,"Failed",0
-72
- = &88,&ff,&ff," MByte",0
-73
- = "Data :",0
-74
- = "Data-F",&88,&ff,&ff,&ff,&ff,&ff,&ff,&ff,&ff,0
-75
- = "Addrs :",0
-76
- = "Addrs-F",&88,&ff,&ff,&ff,&ff,&ff,&ff,&ff,&ff,0
-77
- = "Byte :",0
-78
- = "Byte-F",&88,&ff,&ff,&ff,&ff,0
-
-
-;
-; Data line test.
-;
-; In : r1 - start address for test
-;
-; Out : r0 - failing data pattern
-; r1 - address of failure
-;
-;
-; This exercises data lines in attempt to find shorts/opens.
-; It goes something like :
-;
-; for (ptr = address, pattern = 1; pattern != 0; pattern <<= 1)
-; *ptr++ = pattern;
-; *ptr++ = ~pattern;
-; for (ptr = address, pattern = 1; pattern != 0; pattern <<= 1)
-; result |= pattern ^ *ptr++;
-; result |= ~pattern ^ *ptr++;
-; return result and address
-;
-
-ts_Dataline ROUT
-
-;
-; Write all walking-zero, walking-one patterns
-;
-10 MOV r6,r1 ; set pointer for a write loop
- MOV r5,#1 ; set initial test pattern
- MVN r4,r5 ; and it's inverse
-11
- STMIA r6!,{r4-r5} ; write the patterns
-
- ADDS r5,r5,r5 ; shift the pattern (into Carry)
- MVN r4,r5
- BCC %BT11 ; repeat until all bits done
-;
-; Read back and accumulate in r0 any incorrect bits
-;
- MOV r6,r1 ; set pointer for a read loop
- MOV r5,#1 ; set initial test pattern
- MVN r4,r5 ; and it's inverse
- MOV r0,#0 ; accumulate result
-21
- LDMIA r6!,{r2-r3} ; read the patterns
- EOR r2,r2,r4
- ORR r0,r0,r2 ; OR any failed bits into r0
- EOR r3,r3,r5
- ORR r0,r0,r2
-
- ADDS r5,r5,r5 ; shift the pattern (into Carry)
- MVN r4,r5
- BCC %BT21 ; repeat until all bits done
-;
-; After all checks at this address group, report back errors
-;
- MOVS r0,r0 ; check for any result bits set
- MOV pc,r14 ; return r0 with error map (or 0)
-
-
-
-;
-; Address line test
-;
-; In : r0 - size of memory block
-; r1 - start address of memory block
-;
-; Out : r0 - failing address bit mask
-;
-; This exercises address lines in an attempt to find any which don't
-; work (i.e., don't select unique addresses).
-;
-; It works something like :
-;
-; MaxRam = PhysRam | (Memory size - 4);
-; for (pattern = 4; pattern < memsize; pattern <<= 1 )
-; *(PhysRam ^ pattern) = pattern;
-; *(MaxRam ^ pattern) = ~pattern;
-; for (pattern = 4; pattern < memsize; pattern <<= 1 )
-; if (*PhysRam == *(PhysRam ^ pattern))
-; result |= pattern;
-; if (*MaxRam == *(MaxRam + pattern))
-; result |= pattern;
-; return result
-;
-
-
-ts_Addrline ROUT
-
- MOVS r7,r0 ; Save memory size
- SUB r6,r0,#4 ; Calculate MaxRam
- ADD r6,r6,r1 ; (all-bits-set memory address)
-;
-; Mark (walking one, walking 0) addresses with unique patterns
-;
- LDR r5,=&5A5AA5A5 ; initialize end markers
- STR r5,[r6]
- MVN r4,r5
- MOV r3,r1
- STR r4,[r3]
-
- MOV r5,#4 ; initialize pattern
-02
- MVN r4,r5
- EOR r3,r5,r1 ; point to (start ^ pattern)
- STR r4,[r3]
- EOR r3,r5,r6 ; point to (end ^ pattern)
- STR r5,[r3]
-
- MOV r5,r5,LSL #1 ; shift test pattern up
- CMPS r5,r7 ; test bit still inside memory ?
- BCC %02 ; reached top bit - end this loop
-;
-; Check (walking one, walking 0) addresses for effectivity
-;
- MOV r5,#4 ; initialize pattern
- MOV r3,r1
- MOV r0,#0
-04
- MVN r4,r5
- EOR r2,r5,r3 ; point to (start ^ pattern)
- LDR r2,[r2]
- LDR r1,[r3]
- CMPS r1,r2 ; do contents differ ?
- ORREQ r0,r0,r5 ; no - record ineffective bit
-
- EOR r2,r5,r6 ; point to (end ^ pattern)
- LDR r2,[r2]
- LDR r1,[r6]
- CMPS r1,r2 ; do contents differ ?
- ORREQ r0,r0,r5 ; no - record ineffective bit
-
- MOV r5,r5,LSL #1 ; shift test pattern up
- CMPS r5,r7 ; test bit still inside memory ?
- BCC %04 ; reached top bit - end this loop
-
- MOVS r0,r0 ; any result bits set - return error
- MOV pc,r14
-
-
-;
-; Byte / word test
-;
-; In : r1 - memory start
-;
-; Out : r0 - Failure indication
-;
-; This test ensures that individual bytes may be written to each part of a word
-; without affecting the other bytes in the word.
-;
-; for (byte = 0; byte < 4; byte ++)
-; address[0] = word_signature
-; address[1] = ~word_signature
-; address + byte = byte_signature
-; if (address[0] !=
-; (word_signature & (~ff << byte * 8))
-; | (byte_signature << byte * 8) )
-; result |= (1 << byte)
-; if (result != 0
-; result |= address; /* fail at address, byte(s) */
-; return result; /* pass */
-;
-
-ts_Byteword ROUT
-
- LDR r3,=&AABBCCDD ; word signature
- MOV r0,#0
- MOV r2,r0
-;
-; byte test loop ( for bytes 0 to 4 ...)
-;
-02
- MVN r4,r3
- STMIA r1,{r3,r4} ; write word signature
- STRB r2,[r1,r2] ; write byte (0, 1, 2 or 3)
-
- MOV r4,r2,LSL #3 ; calculate expected result
- MOV r5,#&ff
- MVN r5,r5,LSL r4
- AND r5,r5,r3 ; word signature, byte removed
- ORR r5,r5,r2,LSL r4 ; byte signature inserted
-
- LDR r4,[r1,#4] ; read (probable) inverse data to precharge bus
- LDR r4,[r1] ; read modified word
- CMPS r4,r5
- MOV r5,#1
- MOV r4,r2,LSL #2
- ORRNE r0,r0,r5,LSL r4 ; fault : set bit in result mask
-;
-; Loop for next byte
-;
- ADD r2,r2,#1 ; Bump byte counter
- CMPS r2,#4 ; ... until 4 byte strobes tested
- BLO %BT02
-;
-; byte strobes all tested : check for errors
-;
- CMPS r0,#0
- MOV pc,r14 ; Result : return address and fault mask.
-
-;
-; End of RAM line tests
-;
-
-ts_endline
-
- END
-
\ No newline at end of file
diff --git a/OldTestSrc/Mem1MEMC1 b/OldTestSrc/Mem1MEMC1
deleted file mode 100644
index 632c9bf2b8e5b33faf87dc5ac37826a43174df3d..0000000000000000000000000000000000000000
--- a/OldTestSrc/Mem1MEMC1
+++ /dev/null
@@ -1,390 +0,0 @@
-; > TestSrc.Mem1
-
- TTL RISC OS 2+ POST memory linetest
-;
-; This test code is used to perform basic integrity tests on DRAM.
-; It doesn't test all locations - just walks patterns through data
-; and address lines.
-;
-;------------------------------------------------------------------------
-; History
-;
-; Date Name Comment
-; ---- ---- -------
-; 18-Dec-89 ArtG Initial version
-; 1-Jun-93 ArtG Reorganised to allow separate module for Medusa
-;
-;
-;------------------------------------------------------------------------
-
-;
-; Test the data and address and byte strobe lines for uniqueness.
-;
-
- LTORG
- ROUT
-
-1
- = "Data :",0
-2
- = "Data @",&89,&ff,&ff,&ff,&ff,&ff,&ff,&ff,0
-3
- = "Data-F",&88,&ff,&ff,&ff,&ff,&ff,&ff,&ff,&ff,0
-4
- = "Data-P",&88,&ff,&ff,&ff,&ff,&ff,&ff,&ff,&ff,0
-
-
-
- ALIGN
-
-ts_LineTest
-
- ADR r4,%BT1
- BL ts_SendText ; Start data line tests
-
- MOV_fiq r0,r10_fiq
- MOV r1, #PhysRam
- BL ts_Dataline
- BEQ ts_address ; OK : continue to next test
-;
-; Data line test failed. This probably also means that RISCOS got the
-; configuration wrong, so set it to 32K pages and repeat - otherwise
-; the data line test result may be garbage.
-;
- ADR r4,%BT2
- MOV r11,r0 ; save data & report fault address
- MOV r8,r1,LSL #4
- BL ts_SendText
-
- MOV r8,r11
- ADR r4,%BT3 ; report data fault mask
- BL ts_SendText
-
- LDR r0,=(&E000C :OR: MEMCADR) ; set 32K page size
- STR r0,[r0]
- MOV_fiq r11_fiq,r0
-
- MOV r0,#ts_RamChunk ; limit test to 1 block
- MOV r1,#PhysRam
- BL ts_Dataline
-
- MOV r8,r0
- ADR r4,%BT4 ; ready to report data fault mask
- B ts_linefault
-
-;
-; Start the address line tests
-;
- ROUT
-
-4
- = "Addrs :",0
-5
- = "Addrs",&89,&ff,&ff,&ff,&ff,&ff,&ff,&ff,0
-6
- = "Byte :",0
-7
- = "Byte",&89,&ff,&ff,&ff,&ff,&ff,&ff,&ff,0
-
-
-
-ts_address
- ADR r4,%BT4
- BL ts_SendText ; Start address line tests
-
- MOV_fiq r0,r10_fiq
- BL ts_Addrline
-
- ADR r4,%BT5
- MOV r8,r0,LSL #4
- BEQ %30 ; Failed : report address fault
-
-ts_linefault
- FAULT #R_LINFAILBIT
- B %31
-
-30 ADR r4,%BT6 ; Start Byte/Word test
- BL ts_SendText
-
- MOV_fiq r0,r10_fiq ; get memory size
- BL ts_Byteword
-
- MOV r8,r0,LSL #4 ; Get result to top of r8
- BEQ %40
- FAULT #R_LINFAILBIT
-
- ADR r4,%BT7
-
-31 BL ts_SendText
- B %42
-;
-; Line tests passed. Do a short test on memory that isn't there,
-; in case it's supposed to be and we want to know why it's not ..
-
-40
- MOV_fiq r0, r10_fiq ; if there's less than 16Mbytes ..
- CMP r0, #(16 * 1024 * 1024)
- BCS %F42
- ADR r4, %FT44 ; briefly test the next bit of ram
- BL ts_SendText ; in case it's a duff expansion
-
- MOV_fiq r1,r10_fiq
- ADD r1,r1,#PhysRam
- MOV r0,#ts_RamChunk
- BL ts_Dataline
- ADR r4, %FT45
- MOV r11, r0 ; report the result even if OK
- MOV r8,r1,LSL #4
- BL ts_SendText ; report address
-
- MOV r8,r11
- ADR r4,%FT46 ; report data fault mask
- BL ts_SendText
-;
-; End of line tests
-;
-
-42
- B ts_IOCTest
-
-44
- = "Exp? :",0
-45
- = "Exp? @",&89,&ff,&ff,&ff,&ff,&ff,&ff,&ff,0
-46
- = "Exp?",&88,&ff,&ff,&ff,&ff,&ff,&ff,&ff,&ff,0
-
-
-
-;
-; Data line test.
-;
-; In : r0 - size of memory
-; r1 - start address for test
-;
-; Out : r0 - failing data pattern
-; r1 - address of failure
-;
-;
-; This exercises data lines in attempt to find shorts/opens.
-; It goes something like :
-;
-; for (address = start; address < end of ram; address += ts_RamChunk)
-; for (ptr = address, pattern = 1; pattern != 0; pattern <<= 1)
-; *ptr++ = pattern;
-; *ptr++ = ~pattern;
-; for (ptr = address, pattern = 1; pattern != 0; pattern <<= 1)
-; result |= pattern ^ *ptr++;
-; result |= ~pattern ^ *ptr++;
-; if (result |= 0)
-; return result and address
-;
-
-ts_Dataline ROUT
-
- ADD r7,r1,r0 ; end address
-;
-; Write all walking-zero, walking-one patterns
-;
-10 MOV r6,r1 ; set pointer for a write loop
- MOV r5,#1 ; set initial test pattern
- MVN r4,r5 ; and it's inverse
-11
- STMIA r6!,{r4-r5} ; write the patterns
-
- ADDS r5,r5,r5 ; shift the pattern (into Carry)
- MVN r4,r5
- BCC %BT11 ; repeat until all bits done
-;
-; Read back and accumulate in r0 any incorrect bits
-;
- MOV r6,r1 ; set pointer for a read loop
- MOV r5,#1 ; set initial test pattern
- MVN r4,r5 ; and it's inverse
- MOV r0,#0 ; accumulate result
-21
- LDMIA r6!,{r2-r3} ; read the patterns
- EOR r2,r2,r4
- ORR r0,r0,r2 ; OR any failed bits into r0
- EOR r3,r3,r5
- ORR r0,r0,r2
-
- ADDS r5,r5,r5 ; shift the pattern (into Carry)
- MVN r4,r5
- BCC %BT21 ; repeat until all bits done
-;
-; After all checks at this address group, report back errors
-;
- MOVS r0,r0 ; check for any result bits set
- MOVNE pc,r14 ; return on error
-;
-; Bump to another address group
-;
- ADD r1,r1,#ts_RamChunk
- CMPS r1,r7 ; test for loop end
- BLO %10
-
- SUBS r1,r1,#ts_RamChunk ; no fault - last tested address
- MOVS r0,r0
- MOV pc,r14 ; test complete - no failures.
-
-
-;
-; Address line test
-;
-; In : r0 - size of memeory
-;
-; Out : r0 - failing address bit mask
-;
-; This exercises address lines in an attempt to find any which don't
-; work (i.e., don't select unique addresses).
-;
-; It works something like :
-;
-; MaxRam = PhysRam | (Memory size - 4);
-; for (pattern = 4; pattern < memsize; pattern <<= 1 )
-; *(PhysRam ^ pattern) = pattern;
-; *(MaxRam ^ pattern) = ~pattern;
-; for (pattern = 4; pattern < memsize; pattern <<= 1 )
-; if (*PhysRam == *(PhysRam ^ pattern))
-; result |= pattern;
-; if (*MaxRam == *(MaxRam + pattern))
-; result |= pattern;
-; return result
-;
-
-
-ts_Addrline ROUT
-
- MOVS r7,r0 ; Save memory size
- SUB r6,r0,#4 ; Calculate MaxRam
- ADD r6,r6,#PhysRam ; (all-bits-set memory address)
-;
-; Mark (walking one, walking 0) addresses with unique patterns
-;
- LDR r5,=&5A5AA5A5 ; initialize end markers
- STR r5,[r6]
- MVN r4,r5
- MOV r3,#PhysRam
- STR r4,[r3]
-
- MOV r5,#4 ; initialize pattern
-02
- MVN r4,r5
- EOR r3,r5,#PhysRam ; point to (start ^ pattern)
- STR r4,[r3]
- EOR r3,r5,r6 ; point to (end ^ pattern)
- STR r5,[r3]
-
- MOV r5,r5,LSL #1 ; shift test pattern up
- CMPS r5,r7 ; test bit still inside memory ?
- BCC %02 ; reached top bit - end this loop
-;
-; Check (walking one, walking 0) addresses for effectivity
-;
- MOV r5,#4 ; initialize pattern
- MOV r3,#PhysRam
- MOV r0,#0
-04
- MVN r4,r5
- EOR r2,r5,r3 ; point to (start ^ pattern)
- LDR r2,[r2]
- LDR r1,[r3]
- CMPS r1,r2 ; do contents differ ?
- ORREQ r0,r0,r5 ; no - record ineffective bit
-
- EOR r2,r5,r6 ; point to (end ^ pattern)
- LDR r2,[r2]
- LDR r1,[r6]
- CMPS r1,r2 ; do contents differ ?
- ORREQ r0,r0,r5 ; no - record ineffective bit
-
- MOV r5,r5,LSL #1 ; shift test pattern up
- CMPS r5,r7 ; test bit still inside memory ?
- BCC %04 ; reached top bit - end this loop
-
- MOVS r0,r0 ; any result bits set - return error
- MOV pc,r14
-
-
-;
-; Byte / word test
-;
-; In : r0 - memory size
-;
-; Out : r0 - address of physical ram where failure occured
-;
-; This test ensures (for each of four possible MEMCs fitted)
-; that individual bytes may be written to each part of a word
-; without affecting the other bytes in the word.
-;
-; for (address = PhysRam; address < PhysRam + Memsize; address += 4Mbyte)
-; for (byte = 0; byte < 4; byte ++)
-; address[0] = word_signature
-; address[1] = ~word_signature
-; address + byte = byte_signature
-; if (address[0] !=
-; (word_signature & (~ff << byte * 8))
-; | (byte_signature << byte * 8) )
-; result |= (1 << byte)
-; if (result != 0
-; result |= address; /* fail at address, byte(s) */
-; return result;
-; return result; /* pass */
-;
-
-ts_Byteword ROUT
-
- ADD r7,r0,#PhysRam ; Set test limit address
- MOV r1,#PhysRam ; Initial test address
- LDR r3,=&AABBCCDD ; word signature
-;
-; MEMC test loop (for addresses 4M, 8M, ...)
-;
-01
- MOV r0,#0 ; clear result register
- MOV r2,#0 ; clear byte count
-;
-; byte test loop ( for bytes 0 to 4 ...)
-;
-02
- MVN r4,r3
- STMIA r1,{r3,r4} ; write word signature
- STRB r2,[r1,r2] ; write byte
-
- MOV r4,r2,LSL #3 ; calculate expected result
- MOV r5,#&ff
- MVN r5,r5,LSL r4
- AND r5,r5,r3 ; word signature, byte removed
- ORR r5,r5,r2,LSL r4 ; byte signature inserted
-
- LDR r4,[r1,#4]
- LDR r4,[r1] ; read modified word
- CMPS r4,r5
- MOV r5,#1
- ORRNE r0,r0,r5,LSL r2 ; fault : set bit in result mask
-;
-; Loop for next byte
-;
- ADD r2,r2,#1 ; Bump byte counter
- CMPS r2,#4 ; ... until 4 byte strobes tested
- BLO %BT02
-;
-; byte strobes all tested : check for errors
-;
- CMPS r0,#0
- ORRNE r0,r0,r1
- MOVNE pc,r14 ; Error : return address and fault.
-;
-; Loop for next MEMC
-;
- ADD r1,r1,#&400000 ; Bump to next MEMC
- CMPS r1,r7
- BLO %01
-
- MOVS r0,#0 ; Passed - return OK
- MOV pc,r14
-
-
- END
-
\ No newline at end of file
diff --git a/OldTestSrc/Mem2 b/OldTestSrc/Mem2
deleted file mode 100644
index 89f5bc2d3a13a7acf9b701c7cdf5a16209c3fec9..0000000000000000000000000000000000000000
--- a/OldTestSrc/Mem2
+++ /dev/null
@@ -1,278 +0,0 @@
-;> MEM2C
-;
-; RISC OS 2+ BOOT TEST SOFTWARE
-; MEMORY TEST 2 VERSION A.
-; BRIAN RICE 30-10-89
-; 06-Apr-90 ArtG 0.1 Test variable memory size
-;
-; This file will perform a simple test on all DRAM.
-; The test code for this test was taken from thhe A680 Quick memory
-; test software. The software was copied straight but the number of times
-; the test looped arround was cut down to two loops, because of time
-; constraints when testing the memory.
-
-Test_wks_msize * &40 ; Space for test block size
-Test_wks_return1 * &44 ; Space for return addresses
-Test_wks_return2 * &48
-Test_code_off * &4C ; Where testing starts
-
-test_size * 13 * 4 ; Size of test group
-test_mem_rsvd * Test_code_off+test_mem_template_end-test_mem_template
-
-;
-; Quick test the RAM (pre boot style)
-;
-
-ts_RamTest ROUT
- MOV r13,r0
- STR r14,[r13,#Test_wks_return1]
- STR r1,[r13,#Test_wks_msize]
-
- LDR r0, test_quick_pattern
- BL test_mem_code
- ORRS r0,r0,r0
- BNE test_mem_quit
-;
- LDR r0, test_quick_pattern
- MVN r0, r0 ; inverse pattern
- BL test_mem_code
- ORRS r0,r0,r0
-
-test_mem_quit
- ADR r12,%22
- BEQ %10
-
-; If fault detected, exit with zero flag clear, r0 pointing to failing
-; location, r1 containing faulty data and r2 pointing a suitable error
-; message indicating whether all-0 or all-1 data was expected.
-
- LDR r2,[r14] ; fetch failing instructiom
- ANDS r2,r2,#1 ; calculate expected data
- ADREQ r12,%20 ; and load suitable message
- ADRNE r12,%21
- MOVS r0,r0 ; with zero flag set for PASS.
-10
- LDR pc,[r13,#Test_wks_return1]
-
-; Fail messages indicate incorrect data read after WRote 0 or Wrote 1
-; to all bits at that location.
-
-20
- = "WR-0 RD",&88,&ff,&ff,&ff,&ff,&ff,&ff,&ff,&ff,0
-21
- = "WR-1 RD",&88,&ff,&ff,&ff,&ff,&ff,&ff,&ff,&ff,0
-22
- = "??",0
-
- ALIGN
-
-test_quick_pattern & &0f76
-
-; Large Memory test. Generates the write + test routines in memory
-; then calls them. The routine tests patterns as defined by the bottom
-; 13 bits of r0.
-;
-; N.B. The test start address must be calculated to ensure that
-; the loops finish exactly with r0 equal to End_memory
-;
-; The routine returns with eq true if the memory is OK.
-
-
-test_mem_code
- ROUT
-
- STR r14, [r13, #Test_wks_return2]
-;
-; Copy the ram test code into low ram, modifying MOV instructions
-; to MVN in accordance with the test pattern.
-;
- ADR r1, test_mem_template
- ADD r2, r13, #Test_code_off
- LDMIA r1!, {r3-r4} ; copy initial 2 instrucions
- STMIA r2!, {r3-r4}
- MOV r4, #1
-0 MOVS r0, r0, ROR #1
- LDR r3, [r1], #4
- ORRCS r3, r3, #&00400000 ; Convert MOV => MVN
- STR r3, [r2], #4
- ADD r4, r4, #1
- CMP r4, #13
- BLE %B0
-;
-; Copy the load loop control and verify start instructions
-;
- LDMIA r1!, {r5-r9}
- STMIA r2!, {r5-r9}
-;
-; Copy and modify the CMP instructions
-;
- MOV r0, r0, ROR #32-13
- MOV r4, #1
-1 MOVS r0, r0, ROR #1
- LDR r3, [r1], #4
- ORRCS r3, r3, #&00200000 ; Convert CMP => cmn
- ORRCS r3, r3, #&00000001 ; Convert #0 => #1
- STR r3, [r2], #4
- ADD r4, r4, #1
- CMP r4, #13
- BLE %B1
-;
-; Copy the verify loop control and finishing-up instructions
-;
- LDMIA r1!, {r5-r12}
- STMIA r2!, {r5-r12}
- LDMIA r1!, {r5-r12}
- STMIA r2!, {r5-r12}
- LDMIA r1!, {r5-r12}
- STMIA r2!, {r5-r12}
-
-; check we've copied enough
- ASSERT ((test_mem_stadd - test_mem_chk) = (24 * 4))
-;
-; Calculate the test start and end addresses
-;
- LDR r0, [r13, #Test_wks_msize] ; size of test area
- ADD r14, r13, r0 ; end of test area
- SUB r1, r0, #test_mem_rsvd ; testable size
-
- MOV r2, #test_size ; adjust r1 to (r1 / 13*4) * (13*4)
- DivRem r3, r1, r2, r4
- MUL r1, r3, r2
- SUB r0, r14, r1 ; rounded test start address
-
-; Do it.
- MOV r1, #Test_code_off
- ADD r1, r1, r13 ; pointer to copied code
- MOV pc, r1
-
-;
-; The following code is copied (and modified) into RAM for execution
-;
-
-test_mem_template
- ROUT
- STR r0, test_mem_stadd ; save initial RAM address
- STR r13, test_mem_base ; save test area base address
- MOV r1, #0 ; Converted to MVN if bit = 1
- MOV r2, #0 ; Converted to MVN if bit = 1
- MOV r3, #0 ; Converted to MVN if bit = 1
- MOV r4, #0 ; Converted to MVN if bit = 1
- MOV r5, #0 ; Converted to MVN if bit = 1
- MOV r6, #0 ; Converted to MVN if bit = 1
- MOV r7, #0 ; Converted to MVN if bit = 1
- MOV r8, #0 ; Converted to MVN if bit = 1
- MOV r9, #0 ; Converted to MVN if bit = 1
- MOV r10, #0 ; Converted to MVN if bit = 1
- MOV r11, #0 ; Converted to MVN if bit = 1
- MOV r12, #0 ; Converted to MVN if bit = 1
- MOV r13, #0 ; Converted to MVN if bit = 1
-0
- STMIA r0!, {r1-r13}
- CMP r0, r14
- BLO %B0
-
- LDR r0, test_mem_stadd
-1
- LDMIA r0!, {r1-r13}
-2
- CMP r1, #0 ; Converted to cmn if bit = 1
- CMPEQ r2, #0 ; Converted to cmneq if bit = 1
- CMPEQ r3, #0 ; Converted to cmneq if bit = 1
- CMPEQ r4, #0 ; Converted to cmneq if bit = 1
- CMPEQ r5, #0 ; Converted to cmneq if bit = 1
- CMPEQ r6, #0 ; Converted to cmneq if bit = 1
- CMPEQ r7, #0 ; Converted to cmneq if bit = 1
- CMPEQ r8, #0 ; Converted to cmneq if bit = 1
- CMPEQ r9, #0 ; Converted to cmneq if bit = 1
- CMPEQ r10, #0 ; Converted to cmneq if bit = 1
- CMPEQ r11, #0 ; Converted to cmneq if bit = 1
- CMPEQ r12, #0 ; Converted to cmneq if bit = 1
- CMPEQ r13, #0 ; Converted to cmneq if bit = 1
-test_mem_chk
- BNE %F5 ; go report fault data
- CMP r0, r14
- BLO %B1 ; else loop for next batch
- MOVS r0, #0 ; All OK : return with NULL r0
-4
- LDR r13,test_mem_base
- LDR pc, [r13, #Test_wks_return2]
-
-; Failed : repeat the last batch of tests one at a time, to determine
-; the first failing address and data.
-; Note that the test instructions are copied to %8 to permit individual
-; execution, and %7 is overwritten with an instruction used to copy
-; the failing data into r1. Change this code very carefully !
-
-5
- LDR r14,%2 ; Obtain first test in the set
- STR r14,%8 ; and re-execute it
- SUB r0,r0,#(13*4) ; adjust pointer to bad data
- ADR r14,%2 ; point to first test.
-7
- B %8 ; make sure %8 is refetched
-8
- & 0 ; redo the test here :
- BNE %4 ; if it failed, exit with
- ; r0 = ptr to memory
- ; r1 = wrongly read data
- ; r14 => failing instruction
-
- LDR r1,[r14,#4]! ;fetch next instruction
- AND r1,r1,#&f0000 ;make an instruction
- MOV r1,r1,LSR #16 ;to copy the next register
- ORR r1,r1,#&E1000000 ;down to r1
- ORR r1,r1,#&00A00000 ;e.g. CMPEQ r10,#0
- ORR r1,r1,#&00001000
- STR r1,%7 ;and put it at %7
- LDR r1,[r14] ;then copy the next test
- STR r1,%8 ;to %8
- ADD r0,r0,#4 ;bump the fault pointer
- B %7 ;and execute %7 and %8.
-
-test_mem_stadd ; address of first test location
- & 0
-test_mem_base
- & 0 ; address of test block
-
-test_mem_template_end
-
-;
-; Copy the L2 page table from r1 to r0, then remap the translation table's
-; base address in the MMU to point to an L1 page table within it.
-;
- ROUT
-
-ts_remap_ttab
- MOV r2,#FixedAreasL2Size
- ADD r0,r0,r2 ; point to locations in PhysSpace
- ADD r0,r0,#PhysSpace
- ADD r1,r1,r2
- ADD r1,r1,#PhysSpace
-10
- ASSERT ((FixedAreasL2Size :AND: ((8*4)-1)) = 0)
- LDMDB r1!,{r3-r10} ; copy the page & section tables
- STMDB r0!,{r3-r10}
- SUBS r2,r2,#(8*4)
- BNE %BT10
-
- SUB r9,r1,r0 ; r9 = offset from original to copy
- ADD r0, r0, #DRAMOffset_L1PT-DRAMOffset_L2PT ; r0 -> copy of L1Phys
- SUB r10, r0, #PhysSpace ; keep real address of L1PT for MMU
- ADD r2,r0,#((1 :SHL: (32-20))*4) ; size of L1PT - 1 word per meg of memory
-11 LDR r3,[r0],#4 ; check each L1 table entry
- ANDS r4,r3,#3
- CMPS r4,#L1_Page ; if it's page mapped ..
- SUBEQ r3,r3,r9 ; adjust the page table base address
- STREQ r3,[r0,#-4]
- CMPS r0,r2 ; repeat for all the level 1 table
- BNE %BT11
-
- SetCop r10, CR_TTabBase ; set up MMU pointer to L1
- SetCop r0, CR_IDCFlush ; flush cache + TLB just in case
- SetCop r0, CR_TLBFlush ; (data written is irrelevant)
-
- MOV pc,r14
-
-
- END
-
diff --git a/OldTestSrc/Mem3 b/OldTestSrc/Mem3
deleted file mode 100644
index 1313275f4a55e6f7eb344e50900cdd97407b5f33..0000000000000000000000000000000000000000
--- a/OldTestSrc/Mem3
+++ /dev/null
@@ -1,119 +0,0 @@
- ;> RomCheck
-;
-; RISC OS 2+ BOOT TEST SOFTWARE
-; MEMORY TEST 3 VERSION A.
-; BRIAN RICE 01-11-89
-; 24.04.90 0.10 ArtG Added ROM size test
-; 15.05.90 1.00 ArtG Changed to put checksum at (end - 2 words)
-; 17.05.90 1.01 ArtG Changed to get ROM length from vectot table
-;
-;
-; This file will perform quick checksum test on the OS ROMS.
-;
-;
-; The test code for this test is a simple additive checksum routine.
-; The software will read eight words from ROM then add the contents from ROM
-; to a register. When the test is complete the contents of the checksum
-; register is checked by adding the final word in ROM - this should give
-; zero.
-; The program will be run from ROM, at slowest speed.
-;
-; All except the last two words are checksummed : these hold the numbers
-; that cause each individual ROM to CRC to zero, so they can't simultaneously
-; be included in an all-zero additive checksum.
-
-ts_CRCsize * (2 * 4)
-
-;
-;
-;r0 IS A POINTER TO THE LOCATIONS IN MEMORY.
-;r1 HAS THE CALCULATED CHECKSUM.
-;r2 HOLDS A COUNTER INDICATION HOW MANY WORDS ARE LEFT TO GET
-;r3 is a temporary variable
-;r4 TO r11 ARE USED TO LOAD THE CONTENTS OF 8 LOCATIONS FROM THE ROM.
-;
- ROUT
-
-ts_ROM_checksum
-
- MOV r1, #&00 ; initialise accumulator
- LDR r0, =PhysROM ; initialise pointer
- LDR r2, [r0, #ts_ROMSIZE] ; initialise endstop
- ADD r2, r2, r0 ; - must be at least 8 words
- SUB r2, r2, #(10 * 4) ; below the real endpoint
-
-loop1 LDMIA r0!, {r4 - r11} ;LOAD r4 TO r11 WITH THE CONTENTS
- ;OF LOCATIONS POINTED TO BY r0
- ;WHICH IS INCREMEMTED AUTOMATICALLY
- ;TO POINT TO THE NEXT LOCATION
-01
- ADD r1, r1, r4 ;ADD r4 TO CHECKSUM
- ADD r1, r1, r5 ;ADD r5 TO CHECKSUM
- ADD r1, r1, r6 ;ADD r6 TO CHECKSUM
- ADD r1, r1, r7 ;ADD r7 TO CHECKSUM
- ADD r1, r1, r8 ;ADD r8 TO CHECKSUM
- ADD r1, r1, r9 ;ADD r9 TO CHECKSUM
- ADD r1, r1, r10 ;ADD r10 TO CHECKSUM
- ADD r1, r1, r11 ;ADD r11 TO CHECKSUM
-02
- ASSERT ((%02 - %01) = 32) ; else r2 won't count down correctly
-
- CMPS r0, r2
- BCC loop1 ;loop until pointer reaches endstop
-
- LDMIA r0!, {r4 - r9} ; get last 6 words (miss last 2 in ROM)
-03
- ADD r1, r1, r4 ;ADD r4 TO CHECKSUM
- ADD r1, r1, r5 ;ADD r5 TO CHECKSUM
- ADD r1, r1, r6 ;ADD r6 TO CHECKSUM
- ADD r1, r1, r7 ;ADD r7 TO CHECKSUM
- ADD r1, r1, r8 ;ADD r8 TO CHECKSUM
- ADD r1, r1, r9 ;ADD r9 TO CHECKSUM
-04
- ASSERT (((%04 - %03) + (2*4)) = 32) ; Change this if you like -
- ; but be careful to count nearly
- ; to the top in eights, then add
- ; add in the last few words.
-
- MOVS r0,r1 ; should be zero if all OK
-
- MOV pc,r14 ;return with zero flag set on OK
- ;and the calculated sum in r0.
-
-
-;
-; ROM alias check.
-; This test looks for an aliased copy of the vector table at varying
-; distances from the start of ROM space.
-; 16K is fairly arbitrary but corresponds approximately with the size of
-; the POST. If there's an alias below that, we've probably already crashed !
-;
-; This test is only called if the checksum fails, in order to indicate a
-; possible high ROM address line failure.
-
-ts_ROM_alias ROUT
-
- MOV r0,#PhysROM ; get some words from ROM start
- LDR r3,[r0, #ts_ROMSIZE] ; get the ROM length word
- LDMIA r0,{r4,r5,r6,r7}
- MOV r1,#(16 * 1024)
-
-01 ADD r2,r0,r1 ; get some words from possible alias
- LDMIA r2,{r8,r9,r10,r11}
- CMPS r4,r8
- CMPNE r5,r9
- CMPNE r6,r10
- CMPNE r7,r11
- BEQ %10 ; aliased : found MS ROM address bit
-
- MOVS r1, r1, LSL #1 ; test the next (more significant) bit
- CMPS r1, r3 ; reached the limit yet ?
- BLT %01 ; no - try again.
-
-10 MOV r0,r1 ; reached the end, or an alias.
- MOV pc,lr
-
-
- LTORG
-
- END
diff --git a/OldTestSrc/Mem4 b/OldTestSrc/Mem4
deleted file mode 100644
index 8d73e78c45242b07452cbc64e675df452f4b3f7a..0000000000000000000000000000000000000000
--- a/OldTestSrc/Mem4
+++ /dev/null
@@ -1,630 +0,0 @@
-;> MEM4H_SCR
-;
-; RISC OS 2+ BOOT TEST SOFTWARE.
-; MEMORY TEST 4 VERSION H. BRIAN RICE 12-01-90.
-; 04-Apr-90 ArtG 0.1 Added ts_count_cams, improved reporting
-; 11-Apr-90 ArtG 0.2 Use RISC OS routine BangCams for
-; alternate MEMC configurations.
-; 17-Apr-90 ArtG 0.3 rationalise page-counting code
-;
-; This file will be called by MEM6x_SCR for the purposes of assembly.
-; This file will perform quick walking bit test on the CAM Entry points.
-; The test code for this test was taken from the A680 test code.
-;
-; The module requires the running of the memory sizing routine used by
-; the OS to set up the page size for this module.
-;
-; This test module was designed to operate on all current and future
-; machines. The module is designed to handle up to 512 physical pages
-; which is the maximum number of pages in a 16 MByte FOX.
-;
-; A 16 MB FOX has 4 MEMCs in use, each MEMC is addressed by Bits 7 and
-; 12 of the logical to physical address translator. The use of bit 12
-; does have a problem in that on machines with 0.5MB of memory this is
-; used to define the logical page number. Machine with 1MB or greater bit
-; 12 is not used, therefore this test may hit problems on A305's. The
-; intention is that A305 owners will upgrade to A310's when upgrading to
-; RISC OS 2+.
-;
-; Because FOX can have up to 4 MEMCs fitted the following addressing is
-; used to determine the MEMC accessed, bit 12, bit 7
-; 0 0 = Master MEMC = MEMC 0
-; 0 1 = Slave MEMC 1 = MEMC 1
-; 1 0 = Slave MEMC 2 = MEMC 2
-; 1 1 = Slave MEMC 3 = MEMC 3
-;
-;
-; This test will initialise the CAM entries for up to 512 physical pages.
-; The physical pages will be mapped to logical page 5. Each page will have
-; a copy of test routine vectors and a page marker. The page marker consists
-; of the page number and a code to indicate which MEMC was used. The code for
-; the MEMC used is as follows :- MEMC 0 0001 1110 = &1E
-; MEMC 1 0010 1101 = &2D
-; MEMC 2 0100 1011 = &4B
-; MEMC 3 1000 0111 = &87
-;
-; The page marker is arranged as follows &mm5Apppp
-; | |
-; | \-- Page Number &0000 ‰ &01FF.
-; \--------MEMC Code as above.
-;
-; The patterns are chosen so that if two or more MEMCs are accessed
-; together and both RAM outputs get enabled onto the data bus simultaneously,
-; then there is a reasonable chance that the data returned will show the
-; presence of a fault.
-;
-; When the CAM entries have been initialised the module will then check that
-; all the pages are mapped correctly. A simple walking one pattern is used
-; to check that the page is not present anywhere else in the memory area.
-; This isn't really sufficient, but keeps the test time low.
-;
-; The tests are performed with the memory protection level set to 0.
-;
-; This version uses the "my abort" routine in MEM5x_SCR instead of the
-; ts_dab_exp0 .. 5 method as taken from the A680 code.
-;
-
-ts_rst_msg = "RST",0
-ts_uni_msg = "UDF",0
-ts_swi_msg = "SWI",0
-ts_pab_msg = "PAB",0
-ts_dab_msg = "DAB",0
-ts_aex_msg = "ADX",0
-ts_irq_msg = "IRQ",0
-ts_fiq_msg = "FIQ",0
-ts_bxc_msg = &85,"@",&88,&ff,&ff,&ff,&ff,&ff,&ff,&ff,&ff,0
- ALIGN
-
-
-ts_rst ; Unused exception vectors
- ADR r4, ts_rst_msg
- B ts_bad_exception
-ts_uni
- ADR r4, ts_uni_msg
- B ts_bad_exception
-ts_swi
- ADR r4, ts_swi_msg
- B ts_bad_exception
-ts_pab
- ADR r4, ts_pab_msg
- B ts_bad_exception
-ts_dab_unexp
- ADR r4, ts_dab_msg
- B ts_bad_exception
-ts_aex
- ADR r4, ts_aex_msg
- B ts_bad_exception
-ts_irq
- ADR r4, ts_irq_msg
- B ts_bad_exception
-ts_fiq
- ADR r4, ts_fiq_msg
- B ts_bad_exception
-
-
-ts_bad_exception
- SUBS r8, r14, #8 ; remember aborted instruction
- BL ts_SendText
- ADR r4, ts_bxc_msg ; display aborted address
- BL ts_MoreText
- B Reset
-
-
-;
-ts_rom_base * ROM ; Base address of the OS ROMS.
-ts_phys_mem * (32*1024*1024) ; Physical Memory area.
-ts_pagemark * &005A0000 ; + phys page number + MEMC code.
-ts_pmark_pos * 32 ; Position of page mark (avoiding vectors).
-ts_cam_base * &3800000 ; Base address of the CAM table in MEMC.
-ts_vrest * &5 ; Unused page which all pages are mapped to.
-ts_MAX_CAMS * 512 ; Most CAMs ever expected
-ts_memc_codes = &1E, &2D, &4B, &87 ; List of the memc_codes to be used.
-;
-ts_logpages ; List of Logical pages.
- & &0001
- & &0002
- & &0004
- & &0008
- & &0010
- & &0020
- & &0040
- & &0080
- & &0100
- & &0200
- & &03FF
- & &03FE
- & &03FD
- & &03FB
- & &03F7
- & &03EF
- & &03DF
- & &03BF
- & &037F
- & &02FF
- & &01FF
- & &0000 ; Terminator for the list.
-ts_logpagesend ; End of the list.
-;
-;
-; Exception vectors : copied to start of each page to ensure that they will always
-; exist on page zero when arbitrary pages are mapped there.
-;
-ts_vectors
- B (ts_vectors-ts_start)+ts_rom_base+ts_rst
- B (ts_vectors-ts_start)+ts_rom_base+ts_uni
- B (ts_vectors-ts_start)+ts_rom_base+ts_swi
- B (ts_vectors-ts_start)+ts_rom_base+ts_pab
-ts_dab_vector
- B (ts_vectors-ts_start)+ts_rom_base+ts_dab
- B (ts_vectors-ts_start)+ts_rom_base+ts_aex
- B (ts_vectors-ts_start)+ts_rom_base+ts_irq
- B (ts_vectors-ts_start)+ts_rom_base+ts_fiq
-
-
-; ***************************************************************************
-;
-ts_CAM
-;
-; CAM test (full or partial)
-; Start of the CAM test, all physical pages have a copy of the vectors
-; so they may be mapped as page 0. Then each page is mapped at a series
-; of (walking 1, walking 0) logical pages and tested to be correctly
-; mapped. Other pages are set to an unused logical page by set_cam_idle
-; to prevent any CAM clashes.
-;
-; Copy the test vectors and page marker into all the pages.
-;
- ROUT ; Local Branches.
- MOV r13, lr ; Preserve link register in r13.
- BL ts_count_CAMs ; get log2 pagesize
- MOV r0, #ts_MAX_CAMS ; r0 = last page to test
- SUB r0, r0, #1
-0 BL ts_copy_vectors ; Gosub ts_vectors.
- SUBS r0, r0, #&01 ; bump down to next page
- BGE %B0 ; repeatuntil all pages set.
-;
-; 'C' pseudocode for the test routine.
-;
-; for (i = &1ff; i >= 0; i--)
-; set_cam_idle(i);
-;
-; find maximum page number.
-; if (max_page != ts_count_CAMS)
-; report CAM number error
-;
-; for (phys = &max_page; phys >= 0; phys--) {
-; for (logp = &logpages[0]; logp < &logpages[sizof(logpages)]; logp++) {
-; if (*logp == 0) {
-; set_cam(*logp, phys);
-; check_mapped(*logp, phys);
-; } else {
-; int zphys = (phys + 1) % num_pages;
-; set_cam(0, zphys);
-; set_cam(*logp, phys);
-; check_mapped(*logp, phys);
-; set_cam_idle(zphys);
-; }
-; }
-; set_cam_idle(phys);
-; }
-;
-; Idle the pages.
-;
- ROUT ; Local Branches.
- MOV r12, #ts_MAX_CAMS ; always clear all 512 - just in case 4 MEMCs.
- SUB r12, r12, #&01 ; Subtract 1 to make max page #.
-0 MOV r1, r12 ; r1 = page number.
- BL ts_set_cam_idle
- SUBS r12, r12, #&01 ; bump to next page downwards
- BGE %B0 ; repeatuntil page 0 done
-;
-; We need to find out what the maximum number of pages is, after running the above routine
-; all the pages will have the pagemark programed in to each page. As stated in the intro
-; programing the pages from the top down will ensure that, irrespective of the number of
-; MEMCs available, that the bottom pages are programed correctly. Therefore if we start
-; at the top, read in a page, check it's page number & memc code are correct, if so then
-; that is possibly the maximum page number. If not then subtract 1 from the page number and
-; try again until a possible good page is found.
-;
- ROUT ; Local Branches.
-
- BL ts_count_CAMs ; get log2 pagesize to r1
- MOV r8, #ts_MAX_CAMS ; r8= max. number of physical pages.
-0 SUBS r8, r8, #&01 ; Subtract 1 to make it r8 - 1 Pages.
- BEQ ts_bad_CAM_count ; no pages ? - shouldn't hit this!
-;
-; Calculate the expected page marker, in r4, for the current page, in r8.
-;
- ADR r4, ts_memc_codes ; r4 = address of table with the memc codes.
- LDRB r4, [r4, r8, LSR#7] ; r4 = Loc pointed to by r4 + (r1 >> 7).
- ORR r4, r8, r4, LSL #24 ; r4 = page number OR (MEMC code << 24).
- ORR r4, r4, #ts_pagemark ; r4 = page id OR magic number
-;
-; The calculated page marker is now in r4, ref_p_mark.
-; Current page in r8 - convert to physical address in r9.
-; the pagesize power-of-2 is in r1 (from ts_count_CAMs)
-;
- MOV r9, r8, LSL r1 ; convert PPN to phys offset
- ORR r9, r9, #ts_phys_mem ; add offset to start of phys mem
-;
-; r9 now has the address of the current page - read the page marker for that page.
-;
- LDR r9, [r9, #ts_pmark_pos] ; r9 = contents of loc pointed to by
- ; r9 + ts_pmark_pos.
-;
-; Check that read_p_mark is valid.
-;
-; Either the value read is the expected pagemark, junk (no memory) or an
-; aliased pagemark - if it's aliased, then either the memory or the MEMC
-; isn't decoded that far.
-; Bump down and try a bit lower, until it's OK.
-;
- CMP r4, r9 ; Is page-mark expected value ?
- BNE %B0
-
-;
-; Found a pagemarker in the proper place. Check that the number of pages that
-; appear to be present are the same as the number found by ts_count_CAMs
-; (i.e. the memory size / page size).
-;
- SUB r0, r0, #1 ; convert count -> max page number
- CMPS r0, r8
- BNE ts_bad_CAM_count
-;
-; If all is well, we should have the maximum usable page number in r8.
-;
-; Need to reset page 0 in the CAM entries, currently all pages are mapped to page 5.
-; We need to have logical page 0 mapped to physical page 0.
-;
- MOV r0, #&00 ; r0 = &00, the page to map.
- MOV r1, #&00 ; r1 = &00, the page to map to.
- MOV r2, #&00 ; r2 = &00, set the protection level.
- BL ts_set_camp
-;
-; Check we can still see the data abort vector at physical page zero
-; - no good continuing if we can't.
-;
- MOV r0, #ts_phys_mem
- LDR r0, [r0, #(ts_dab_vector - ts_vectors)]
- LDR r1, ts_dab_vector
- CMPS r0, r1
- BNE ts_bad_dab_vector
-
-;
-; Now lets get on with the testing.
-;
-
-2 ADRL r10, ts_logpages ; logp = &logpages[0]
-
-3 LDR r0, [r10] ; r0 = page to test
- CMP r0, #&00 ; last entry ?
- BNE %F4
- MOV r1, r8 ; r1 = r8, page under test
- BL ts_set_cam ; Gosub ts_set_cam.
- LDR r0, [r10] ; r0 current logical test page
- MOV r1, r8 ; r1 = current test page
- BL ts_check_mapped ; Gosub ts_check_mapped.
- B %F5
-
-4 ADD r12, r8, #&01
- BL ts_count_CAMs ; get total number of pages
- SUB r0,r0,#1 ; make a mask for useable page
- AND r0,r0,#&7f ; numbers - min(128, num_pages)
- AND r12, r12, r0 ; r12 -> (r12 + 1) masked
- MOV r0, #&00 ; to useable page numbers.
- MOV r1, r12
- BL ts_set_cam ; Setup a page for vectors
- LDR r0, [r10] ; r0 = current logical test page.
- MOV r1, r8 ; r1 = current physical test page.
- BL ts_set_cam ; Setup a page to test
-
- LDR r0, [r10] ; look up logical page again.
- MOV r1, r8 ; recall physical page.
- BL ts_check_mapped ; check the ts_set_cam worked.
- MOV r1, r12 ; unmap the vector page
- BL ts_set_cam_idle
-
-5 ADD r10, r10, #&04 ; next entry in test list.
- ADRL r0, ts_logpagesend ; r0 = ts_logpagesend.
- CMP r10, r0 ; repeat until list of logical
- BLO %B3 ; pages all done.
-
- MOV r1, r8 ; unmap the page we just tested
- BL ts_set_cam_idle
-
- SUBS r8, r8, #1 ; bump phys page counter down.
- ANDS r8,r8,r8
- BGE %B2 ; If r8 >= 0 Then branch back to 2.
-
- ANDS r0,r0,#0
- MOV pc,r13 ; all done and passed
-
-;
-; ****************************************************************************
-;
-ts_copy_vectors
-;
-; Copies the vectors to the physical page in r0 (preserved) also copies
-; pagemark + phypage.
-; Expects r1 (preserved) to hold log2 of pagesize
-;
- ROUT ; Local Branches.
-
- ADR r2, ts_vectors ; r2 = source address
- LDMIA r2, {r4-r11} ; r4 - r11 = loc pointed to by r2, post inc.
-
- MOV r3, r0, LSL r1 ; r3 = r0 * 2**r1 .
- ORR r3, r3, #ts_phys_mem ; r3 = r3 OR ts_phys_mem.
- STMIA r3, {r4-r11} ; loc pointed to by r3, post inc = r4 to r11.
-;
-; find out which memc is handling the page (r0), then assign the appropiate memc_code.
-; Add in the page number and pagemark, then store into the required position in the
-; page in question.
-;
- ADR r2, ts_memc_codes ; r2 = address of table with the memc codes.
- LDRB r2, [r2, r0, LSR#7] ; r2 = memc code for this phys page.
- ORR r2, r0, r2, LSL #24 ; OR in phys page number.
- ORR r2, r2, #ts_pagemark ; OR in pagemark.
- STR r2, [r3, #ts_pmark_pos] ; loc pointed to by r1 + ts_pmark_pos = pagemark.
- MOV pc, lr ; Return to caller.
-;
-; ****************************************************************************
-;
-ts_set_cam_idle
-;
-; This module will program the physical page (r1) to the logical page 5, ts_vrest and
-; continue onto the next section ts_set_cam.
-;
- ROUT ; Local Branches.
- MOV r0, #ts_vrest ; r0 = ts_vrest, = unused logical page.
-;
-; ****************************************************************************
-;
-ts_set_cam
-;
-; This module will program the physical page (r1) to the logical page (r0) at
-; protection mode 0 and continue onto the next section ts_set_camp.
-;
- MOV r2, #&00 ; r2 = &00, memory prot level 0.
-;
-; ****************************************************************************
-;
-ts_set_camp
-;
-; This module will map a range the physical pages (r1) to the logical page (r0) and
-; set the protection mode (r2). This module will return to the location from where
-; either itself or ts_set_cam or ts_set_cam_idle were called from.
-;
-; Corrupts r0,r1,r2,r3,r4,r6,r9,r11
-;
-; Calls the RISC OS routine BangCam to do the PPNO, LPNO bit switching.
-; First, jumble the registers to suit BangCam ..
-;
-; r2 = CAM entry (PPNO)
-; r3 = logical address
-; r9 = current MEMC setting (for pagesize)
-; r11 = PPL
-;
- MOV r3,r0 ; logical page number
- MOV r11,r2 ; protection level
- MOV r2,r1 ; physical page number
- MOV_fiq r0, r11_fiq ; MEMC configuration
- MOV r9, r0 ; keep a copy in r9
- MOV r1, r9, LSR #2
- AND r1, r1, #3 ; calculate pagesize shift
- ADD r1, r1, #12
- MOV r3, r3, LSL r1 ; convert LPN to logaddr
- B BangCam ; return thro' BangCam
-
-;
-; ****************************************************************************
-;
-ts_check_mapped
-;
-; This routine will check that the CAM has been programed correctly and that the required
-; page is responding when asked. A quick test is made to check that other pages are not
-; responding as well.
-;
-; logical page in r0,
-; physical page in r1,
-; test that they are the same.
-;
-; No return value : reports faults directly and returns thro' r13
-;
-; Uses (corrupts) r0,r1,r2,r3,r4,r5,r6,r7
-;
-; Find out which memc is handling the page (r1), then assign the appropiate memc_code.
-; Add in the page number and pagemark, then compare that pagemark with those found
-; in memory at the expected logical and physical addresses.
-;
-; This code assumes that any system with multiple MEMCs will always have 32K pages.
-;
- ROUT ; Local Branches.
-
- MOV r3, r0 ; save the current logical pagenumber.
- MOV r5, lr ; Preserve link register in case of Abort.
- ADR r2, ts_memc_codes ; r2 = address of table with the memc codes.
- LDRB r2, [r2, r1, LSR#7] ; fetch the memc code for this page.
- ORR r2, r1, r2, LSL #24 ; build the page number into the pagemark
- ORR r2, r2, #ts_pagemark ; build in the pagemark magic number
-;
-; r2 should now have the page_mark for the current page (r1).
-; calculate the shift to convert page number to memory offset.
-;
- MODE FIQ_mode
- MOV r4, r11_fiq, LSR #2 ; pagesize / 4K
- MODE SVC_mode
- AND r4, r4, #3
- ADD r4, r4, #12
-;
-; if the mapping failed completely, the test might abort
-;
- MOV r6, #&00 ; r6 = &00, clear expected abort flag.
- MOV r7, #&94 ; r7 = &94, set abort expected flag.
-;
-; make the pointers and test the contents
-;
- MOV r0, r0, LSL r4 ; r0 = LPN * pagesize.
- LDR r0, [r0, #ts_pmark_pos] ; r0 = contents of loc in r0 + ts_pmark_pos.
- CMP r6, #94 ; did that fetch abort ?
- ADREQ r4, %F14 ; mapping totally failed
- BEQ ts_CAM_fail
- MOV r1, r1, LSL r4 ; r1 = PPN * pagesize.
- ORR r1, r1, #ts_phys_mem ; r1 = r1 ORed with ts_phys_mem.
- LDR r1, [r1, #ts_pmark_pos] ; r1 = contents of loc in r1 + ts_pmark_pos.
- CMP r0, r1 ; Are the read pagemarks equal ??
- ADRNE r4, %F10
- BNE ts_CAM_fail ; Failed : mapping not equal.
- CMP r0, r2 ;
- ADRNE r4, %F11
- BNE ts_CAM_fail ; Failed : map equal, but corrupt
-;
-; test that the page doesn't exist anywhere else
-;
- MOV r2, #1
-0 EOR r0, r2, r3 ; Flip a (walking) bit in the LPN.
- CMP r0, #ts_vrest ; Is r0 = ts_vrest ?? Where all the pages are
- ; mapped to.
- BEQ %F1 ; If r0 = ts_vrest then branch forward to 1.
-;
-; The following instruction should abort.
-;
- MOV r0, r0, LSL r4 ; r0 = LPN * pagesize.
- MOV r6, #&00 ; r6 = &00, clear abort handled flag.
- MOV r7, #&94 ; r7 = &94, set abort expected flag.
- LDR r0, [r0, #ts_pmark_pos] ; get a possible pagemark from this page.
- CMP r6, #&94 ; Did we go thro' the abort handler ?
- BEQ %F1 ; If equal then an abort happened, good !
-;
-; Not aborted - is it page zero, where the vectors live ?
-;
- TEQS r2, r3
- BEQ %F1 ; yes - that SHOULDN'T abort
-;
-; Fault - is the page mapped there the same as our test page ?
-;
- CMP r0, r1
- ADREQ r4, %F12 ; Failed : phys page also mapped here
- ADRNE r4, %F13 ; Failed : page not unmapped
- EOR r3, r2, r3 ; remake the duff LPN for the error display
- B ts_CAM_fail
- ; If equal then no abort happened, not good !!
-
-1 MOV r2, r2, LSL#1 ; bump to next-bit-set page number
- CMP r2, #(ts_MAX_CAMS :SHL: 1) ; Hit number of logical pages ?
- BLT %B0 ; If r2 < maximum number then loop again.
-
- MOV r7, #0 ; no longer expecting aborts
- MOV pc, r5 ; Return to caller.
-
-;
-; Indicate that CAM mapping test failed (PPN is not at LPN)
-; Display r8, the physical page number and r3, the logical page.
-;
-; ***This error exit returns to the CALLER of check_mapped, thro' r13***
-;
-
-10
- = "CAM map",&88,&ff,&ff,&ff,".",&ff,&ff,&ff,&ff,0
-11
- = "CAM pmk",&88,&ff,&ff,&ff,".",&ff,&ff,&ff,&ff,0
-12
- = "CAM als",&88,&ff,&ff,&ff,".",&ff,&ff,&ff,&ff,0
-13
- = "CAM unm",&88,&ff,&ff,&ff,".",&ff,&ff,&ff,&ff,0
-14
- = "CAM abo",&88,&ff,&ff,&ff,".",&ff,&ff,&ff,&ff,0
-
- ALIGN
-
-
-ts_CAM_fail
- MOV r0, r8, LSL #16 ; physical page #
- LDR r1, =&ffff
- AND r1, r1, r3
- ORR r0, r0, r1 ; add logical page #
- MOV r8, r0, LSL #4
- MOV r6, #0 ; no longer expecting aborts
- ORRS r0, r0, #1
- MOV pc, r13
-
-;
-; **************************************************************************
-;
-
-; Routine to return expected number of physical pages in r0.
-; Uses memory size determination from r10_fiq and page mode from r11_fiq.
-; Returns pagesize as power-of-two in r1, for pagenumber->address calcs.
-
-ts_count_CAMs
-
- MODE FIQ_mode
- MOV r0,r10_fiq,LSR #12 ; get values determined
- MOV r1,r11_fiq,LSR #2 ; by MemSize
- MODE SVC_mode
-
- AND r1,r1,#3 ; memory / pagesize
- MOV r0,r0,LSR r1
- ADD r1,r1,#12 ; page bit-shift value
-
- MOVS pc,lr
-
-
-;
-; **************************************************************************
-;
- ROUT
-
-; Indicate that an unexpected number of CAM pages were found.
-;
-; Display as "CAM ## eee.fff"
-;
-; where eee is the expected maximum page number (r0), fff is the number
-; of of the highest page actually found (r8).
-
-0
- = "CAM ##",&89,&ff,&ff,&ff,".",&ff,&ff,&ff,0
- ALIGN
-
-ts_bad_CAM_count
- ADD r8, r8, r0, LSL #12
- MOV r8, r8, LSL #8
- ADR r4, %B0
- ORRS r0, r0 ,#1
- MOV pc, r13
-;
-; **************************************************************************
-;
-
-; Indicate that the DAB vector wasn't visible in physmem
-
-0
- = "CAM vec",&88,&ff,&ff,&ff,&ff,&ff,&ff,&ff,&ff,0
- ALIGN
-
-ts_bad_dab_vector
- ADR r4, %B0
- EOR r8,r0,r1 ; indicate which bits are lost
- ORRS r0, r0, #1
- MOV pc, r13
-;
-; **************************************************************************
-
-; Routine to indicate that an unexpected abort was found.
-
-0
- = "DAB @",&88,&ff,&ff,&ff,&ff,&ff,&ff,&ff,&ff, 0
- ALIGN
-
-ts_unxvect
- ADR r4, %B0
- SUBS r8, r14_svc, #8 ; indicate the aborting instruction
- BL ts_SendText
- ORRS r0, r0, #1
- MOV pc, r13
-
-
-
- LTORG
-
- END
diff --git a/OldTestSrc/Mem5 b/OldTestSrc/Mem5
deleted file mode 100644
index 607a8b8e1d1c47c9ac1c027c522a3acc14133554..0000000000000000000000000000000000000000
--- a/OldTestSrc/Mem5
+++ /dev/null
@@ -1,316 +0,0 @@
-;>MEM5D_SCR
-;
-; RISC OS 2+ BOOT TEST SOFTWARE.
-; MEMORY TEST 5 VERSION D. BRIAN RICE 10-01-90.
-; 04-Apr-90 ArtG 0.1 Use memory size to determine page count
-; 11-Apr-90 ArtG 0.2 Changes to permit use of BangCam
-;
-; This file will be called by MEM6x_SCR for the purposes of assembly.
-; This file requires the assembly of MEM4x_SCR to be perfromed at the
-; same time. The program will call the cam setting routines in the cam
-; test program.
-;
-; This file will test MEMCs ability to assert its protection over
-; logical pages.
-; The test code for this test was taken from the A680 test code.
-; The Arm CPU has three mode of operation, Supervisor, Operating System.
-; and User. Most of the time the machine will operate in user mode, in this.
-; mode the designers do not want the user to have full access to the memory.
-; map, therefore the MEMC(s) will check that the CPU has the appropiate
-; level of authorisation to access specific area of memory.
-; User mode is the lowest mode, allowing limited R/W access to the ram.
-; Operating System is next up the list and is allowed some more access to
-; to the ram than user mode.
-; Supervisor mode this is the highest and the CPU has unlimited access to
-; the entire memory map.
-;
-; This version has the "my abort" routine in it not the ts_dab_exp0..5 routine as
-; coded from the A680 code.
-;
-; Set up some variables.
-;
-ts_wks_word * 36 ; Offset of word for workspace.
-;
-; ****************************************************************************
-;
-ts_memc_prot
-;
-; This module will map and assign protection mode 0 to all the pages. The
-; module will then perfrom a read and write operations in supervisor and
-; user modes. This is repeated for the three (four) protection modes.
-; The module will check after every protection mode level that the required
-; responses have been returned.
-;
-; Set up the memory, map and assign protection mode 0.
-;
- ROUT ; Local Branches.
- MOV r13, lr ; Preserve the link register.
- MOV r12, #&00 ; r12 = The physical page to test.
-
-0 ADD r8, r12, #&01 ; Get a page to use as vectors,
- BL ts_count_CAMs ; get total number of pages
- SUB r0,r0,#1 ; make a mask for useable page
- AND r0,r0,#&7f ; numbers - min(128, num_pages)
- AND r8, r8, r0
-
- MOV r1, r8 ; r1 = r8, r1 = physical page 0.
- MOV r0, #&00 ; r0 = &00, r0 = logical page 0.
- BL ts_set_cam ; Gosub ts_set_cam, set the CAM up.
-;
-; Set protection mode 0 and test that page.
-;
- MOV r2, #&00 ; r2 = &00, r2 = protection mode 0.
- BL ts_mem_prot ; Gosub ts_mem_prot.
- CMP r3,#&0F ; Is r3 = &0F ? r3 = Super Read/Write ok.
- ; O/S Read/Write ok.
- ; User Read/Write ok.
- MOV r2, #0
- BNE ts_prot_fail ; If r3 <> &0F Then branch to fail routine.
-;
-; Set protection mode 1 and test that page.
-;
- MOV r2, #&01 ; r2 = &01, r2 = protection mode 1.
- BL ts_mem_prot ; Gosub ts_mem_prot.
- [ CPU_Type = "ARM600"
- CMP r3,#&0f ; no ABORT line to ARM600
- |
- CMP r3,#&0B ; Is r3 = &0B ? r3 = Super Read/Write ok.
- ] ; O/S Read/Write ok.
- ; User Read only ok.
-
- MOV r2,#1
- BNE ts_prot_fail ; If r3 <> &0B Then branch to fail routine.
-;
-; Set protection mode 2 and test that page.
-;
- MOV r2, #&02 ; r2 = &02, r2 = protection mode 2.
- BL ts_mem_prot ; Gosub ts_mem_prot.
- [ CPU_Type = "ARM600"
- CMP r3,#&0f ; no ABORT line to ARM600
- |
- CMP r3,#&03 ; Is r3 = &03 ? r3 = Super Read/Write ok.
- ] ; O/S Read only ok.
- ; User No Access ok.
- MOV r2,#2
- BNE ts_prot_fail ; If r3 <> &03 Then branch to fail routine.
-;
-; Set protection mode 3 and test that page.
-;
- MOV r2, #&03 ; r2 = &03, r2 = protection mode 3.
- BL ts_mem_prot ; Gosub ts_mem_prot.
- [ CPU_Type = "ARM600"
- CMP r3,#&0f ; no ABORT line to ARM600
- |
- CMP r3, #&03 ; Is r3 = &03 ? r3 = Super Read/Write ok.
- ] ; O/S Read only ok.
- ; User No Access ok.
- MOV r2,#3
- BNE ts_prot_fail ; If r3 <> &03 Then branch to
- ; fail routine.
-;
-; Reset the page used to idle.
-;
- MOV r0, r12 ; r0 = r12, idle the pages
- ; being used.
- BL ts_set_cam_idle ; Gosub ts_set_cam_idle.
- MOV r0, r8 ; r0 = r8, idle the pages
- ; being used.
- BL ts_set_cam_idle ; Gosub ts_set_cam_idle.
-;
-; Increment the physical page counter and check that all the pages are
-; done, else finish.
-;
- BL ts_count_CAMs
- ADD r12, r12, #&01 ; do the next physical page.
- CMP r12, r0 ; Done all pages ?
- BLT %B0 ; If r12 <= cam_entries,
- ; branch back to 0.
-
- ANDS r0, r0, #0 ; set zero flag : test passed
- MOV pc, r13 ; Return to caller.
-;
-; **************************************************************************
-;
-; Branch here when ts_memc_prot fails to get the proper result from
-; ts_mem_prot.
-;
-; At this point,
-;
-; r3 is a map of permitted ops (user read, user write, sys read, sys write)
-; r2 is the memc protection mode
-; r12 is the physical page number.
-;
-; This is displayed as :
-;
-; PPL bad l.a.pppp
-;
-; where l is the PPL set on that page (0, 1, 2 or 3)
-; a is a bitmap of the actual operations permitted (ur.uw.or.ow)
-; p is the physical page number tested
-;
-
-0
- = "PPL bad",&88,&ff,".",&ff,".",&ff,&ff,&ff,&ff,0
- ALIGN
-
-ts_prot_fail
- AND r2, r2, #&0f
- MOV r0, r2, LSL #20 ; mode bits
- AND r3, r3, #&0f
- ORR r0, r0, r3, LSL #16 ; permitted ops bits
- BIC r12, r12, #&ff000000
- BIC r12, r12, #&ff0000
- ORR r0, r0, r12 ; current page number
-
-
- ADR r4, %B0 ; get fail message
- MOV r8, r0, LSL #8 ; shift number to suit ts_SendText
- ORRS r0, r0, #1 ; fail flag
- MOV pc, r13
-
-
-;
-;
-; This section will test that the physical page referenced in r12 at the set
-; protection mode. During the operation of this module, aborts are expected to happen.
-; The aborts are handled by the routine ts_dab.
-;
-; The system is running in supervisor mode and thus to check the user mode read / writes
-; the address translator flag is used. The CPU has a signal called -TRANS which when used
-; with MEMC forces the an address translation to be performed, this is not done whilst
-; in supervisor mode because it has unlimited access to the memory map. The address
-; translator falg (T) is used with STR and LDR instructions only, the effective result of
-; adding the (T) to the opcode is to force the instruction to be executed as if the CPU
-; was in user mode, thus unauthorised accesses will cause an abort to occur.
-;
-; IN:
-; r12 - physical page.
-; r2 - protection mode.
-; OUT:
-; r3 - access pattern.
-; r3 = &0F, Super Read/Write ok, O/S Read/Write ok, User Read/Write ok.
-; r3 = &0B, Super Read/Write ok, O/S Read/Write ok, User Read only ok.
-; r3 = &03, Super Read/Write ok, O/S Read only ok, User No Access ok.
-;
-ts_mem_prot
-;
-; Set up data to write and read from memory.
-;
- MOV r10, lr ; Preserve link register.
- MOV r1, r12 ; r1 = physical page.
- MOV r0, #&01 ; r0 = logical page 1.
- BL ts_set_camp
-
- MOV r3, #&00 ; Initialise access pattern.
- MOV_fiq r5, r11_fiq ; get MEMC control
- AND r5, r5, #&C
- ADR r9, ts_ppl_tptrs
- LDR r9, [r9, r5] ; get test address for this pagesize
-;
-; Test 1 system mode - write.
-;
- MOV r6, #&00 ; r6 = &00, clear expected abort flag.
- MOV r7, #&94 ; r7 = &94, set abort expected flag.
-;
-; The following instruction may abort.
-;
- STR r1, [r9] ; Store r1 at loc pointed to by r9.
- CMP r6, #&00 ; Is r6 = &00 ? If not then abort happened.
- ORREQ r3, r3, #&01 ; If r6 = &00, Then update r3, access pattern.
-;
-; Test 2 system mode - read.
-;
- MOV r6, #&00 ; r6 = &00, clear expected abort flag.
- MOV r7, #&94 ; r7 = &94, set abort expected flag.
-;
-; The following instruction may abort.
-;
- LDR r1, [r9] ; Load r1 from loc pointed to by r9.
- CMP r6, #&00 ; Is r6 = &00 ? If not then abort happened.
- ORREQ r3, r3, #&02 ; If r6 = &00 Then update r3, access pattern.
-;
-; Test 3 user mode - write.
-;
- MOV r6, #&00 ; r6 = &00, clear expected abort flag.
- MOV r7, #&94 ; r7 = &94, set abort expected flag.
-;
-; The following instruction may abort.
-;
- STRT r1, [r9] ; Store r1 at loc pointed to by r9.
- CMP r6, #&00 ; Is r6 = &00 ? If not then abort happened.
- ORREQ r3, r3, #&04 ; If r6 = &00 Then update r3, access pattern.
-;
-; Test 4 user mode - read.
-;
- MOV r6, #&00 ; r6 = &00, clear expected abort flag.
- MOV r7, #&94 ; r7 = &94, set expected expected flag.
-;
-; The following instruction may abort.
-;
- LDRT r1, [r9] ; Load r1 from loc pointed to by r9.
- CMP r6, #&00 ; Is r6 = &00 ? If not then abort happened.
- ORREQ r3, r3, #&08 ; If r6 = &00 Then update r3, access pattern.
- MOV pc, r10 ; Return to caller.
-
-;
-; addresses (a short way up page 1) to test PPL aborts
-;
-
-ts_ppl_tptrs
- & ( 4 * 1024) + ts_wks_word
- & ( 8 * 1024) + ts_wks_word
- & (16 * 1024) + ts_wks_word
- & (32 * 1024) + ts_wks_word
-;
-;
-ts_dab
-;
-; This routine provides the handling when a DATA ABORT occurs.
-; The routine will if the abort was DATA cause the program to skip over the instruction
-; that caused the abort first place.
-; Data aborts could come from a variety of sources, in this module we are only concerned
-; about a select group of aborts. This abort routine is called instead of the "usuall"
-; abort routine. All that is required from this abort routine is to set a flag to
-; indicate that an abort occured. Therefore this routine needs to be told that the
-; abort that caused the routine to be called is either one of mine or not, (expected
-; or unexpected). To achive this &94 is placed in r7. The abort routine will check
-; for the presence of &94 in r7, if present then the abort is an expected abort.
-; The abort routine will then copy r7 into r6, which is used as a flag to indicate
-; that an abort occured and that it was an expected abort. Then the routine will
-; return control to the program at the location after the instruction that caused to
-; abort to occur.
-; The return address is stored by the CPU into the link regester lr (r14), sort off.
-; It must be remembered that the PC is always 2 instructions ahead. E.G. if the
-; instruction that causes the abort is at &2000, then the lr will have &2008 in it,
-; but we want to return to the location after the abort instruction, &2004. Therefore to
-; return to the correct location &04 is removed from the lr and this is put into the pc.
-; If the abort was not expected then the routine will jump to the end and another
-; routine will show that an unexpected abort was generated.
-;
-; IN:
-; r6 - Equals &00, cleared just before the instruction that could cause an abort.
-; r7 - Equals &94, set just before the instruction that could cause an abort.
-;
-; OUT:
-; r6 - Equals &94, set if an abort happened and was expected.
-; r7 - Equals &94, preserved.
-;
- ROUT ; Local Branches.
-;
-; Check that it is an expected abort and not an unexpected abort.
-;
- CMP r7, #&94 ; Is r7 = &94, abort expected value.
- BNE ts_dab_unexp ; If <> &94, Then branch to unexpected
- ; abort handler.
-;
-; It is an expected abort, so handle it.
-;
- MOV r6, r7 ; r6 = r7, indicates that an abort happened.
- SUB pc, lr, #&04 ; pc = link reg - &04.
- ; Skip over aborting instruction.
- ; By reloading the pc we return to the area
- ; of code where the abort occured but 4
- ; locations further on.
-
-
- END
diff --git a/OldTestSrc/TestMain b/OldTestSrc/TestMain
deleted file mode 100644
index 22fcf0d1dada040ca950d51cadf2854ae7a70079..0000000000000000000000000000000000000000
--- a/OldTestSrc/TestMain
+++ /dev/null
@@ -1,78 +0,0 @@
-; > TestMain
-
-
-; Main assembly file for isolated assembly of machine test software
-
-MEMCADR * &3600000
-ROM * &3800000
-
- [ MEMC_Type = "IOMD"
-VideoPhysRam * &02000000 ; Amazing - it's in the same place!
-DRAM0PhysRam * &10000000 ; 4 DRAM banks
-DRAM1PhysRam * &14000000
-DRAM2PhysRam * &18000000
-DRAM3PhysRam * &1C000000
-DRAMBaseAddressMask * &1C000000 ; used to mask off bits after stealing video RAM
-PhysSpaceSize * &20000000 ; IOMD physical map is 512M big
-PhysROM * &00000000 ; and real ROM starts at 0
-SAMLength * 512*4 ; SAM length in bytes for 1 bank of VRAM
-EASISpacePhys * &08000000
-EASISpace * PhysSpace + EASISpacePhys
- |
-VideoPhysRam * &02000000
-PhysSpaceSize * &04000000 ; MEMC1 physical map is 64M big
-PhysROM * &03800000
-PhysRamPhys * &02000000 ; physical space starts here
- ]
-
- ORG ROM
-
- GET TestSrc/Begin
-CONT
- ADRL r2,TestVIDCTAB
- LDR r0,=IOMD_MonitorType
- LDR r0,[r0]
- ANDS r0,r0,#IOMD_MonitorIDMask
- ADDEQ r2,r2,#(TestVVIDCTAB-TestVIDCTAB)
- MOV r0,#ts_VIDCPhys
-08 LDR r1, [r2],#4
- CMP r1, #-1
- STRNE r1, [r0]
- BNE %BT08
-
- MOV r9,#0
-10
- ORR r9,r9,#&40000000
- STR r9,[r0] ; write the border colour
- ADD r9,r9,#&00000005
- ADD r9,r9,#&00000300
- ADD r9,r9,#&00010000
- AND r9,r9,#&00ffffff
-
- MOV r1,#&10000
-12 ADDS r1,r1,#(-1)
- BNE %BT12
-
- B %BT10
-
-;
-; The RISC-OS MEMC setup code is re-used to ensure similar
-; detection of memory configuration. The MEMC1 code is modified only
-; to remove an unnecessary function.
-
- GBLL Module
-Module SETL {FALSE}
- GBLL AssembleSAtest
-AssembleSAtest SETL {FALSE}
-
-DynAreaFlags_DoublyMapped * 1 :SHL: 6
-DynAreaFlags_NotCacheable * 1 :SHL: 5
-DynAreaFlags_NotBufferable * 1 :SHL: 4
-DynAreaFlags_APBits * 15 :SHL: 0 ; currently onl
-
-
- END
-
-
-
-
diff --git a/OldTestSrc/Vidc b/OldTestSrc/Vidc
deleted file mode 100644
index 3aedb0b009aab7548ae66aa3a952f3154fdfa721..0000000000000000000000000000000000000000
--- a/OldTestSrc/Vidc
+++ /dev/null
@@ -1,530 +0,0 @@
-; > TestSrc.VIDC
-
- TTL RISC OS 2+ POST video controller
-;
-; The video outputs cannot be tested directly, and VIDC permits only
-; write operations on its registers.
-; This module performs two tests to verify VIDC's operation
-;
-; - measure mode 0 FLBK period against IOC timer
-; - check that sound DMA occurs (MEMC reports DMA complete)
-;
-; This code contains timing loops affected by gross changes in processor
-; speed, and will re-initialise MEMC with 4K pages and continous refresh.
-;
-;------------------------------------------------------------------------
-; History
-;
-; Date Name Comment
-; ---- ---- -------
-; 18-Dec-89 ArtG Initial version
-; 04-Apr-90 ArtG Use saved MEMC control register setting
-; 20-Jun-93 ArtG Medusa VIDC20 / IOMD changes
-;
-;
-;------------------------------------------------------------------------
-
-
-VIDC_CLOCK_CONTROL * ts_S5_base :OR: &0048 ; Fox VIDC clock control
-VIDC_CLOCK_NORMAL * &0
-
-VIDC_VFLYWAIT * 72000 ; 200mS timeout loop
-VIDC_SOUNDWAIT * 40000 ; 100mS timeout loop
-
-MEMC_Sstart * MEMCADR :OR: &80000
-MEMC_SendN * MEMCADR :OR: &A0000
-MEMC_Sptr * MEMCADR :OR: &C0000
-MEMC_Son * &00800
-
-ts_Soundbuf * &200 ; relative to PhysRam
-ts_Soundbuf_length * &400
-
- [ VIDC_Type = "VIDC20"
-VIDSTIM0 * &A0000000 ; base VIDC20 register values
-VIDSTIM1 * &A1000000
-VIDSFR * &B0000000
-VIDSCR * &B1000005
-VIDDMAoff * &94000024
-VIDVCOWAIT * &5
-VIDVCOFREQ * &D0000404
- |
-VIDSTIM0 * &60000000 ; base VIDC register values
-VIDSTIM1 * &64000000
-VIDSFR * &C0000100
- ]
-
- SUBT FLBK period test
-;
-; This test attempts to validate the video timing system by checking for
-; the proper period from the vertical flyback pulse. To make life easier,
-; the test is performed only in mode 0 - i.e a 20mS period.
-;
-; This test contains a processor-clock timed loop as an outer limit :
-; it assumes that the processor will never run more than a factor of ten
-; faster than an 8Mhz ARM2.
-; This is valid provided that this code isn't run with an ARM3 cache enabled.
-;
-
-; Initialise video clock control (for FOX)
-; Initialise VIDC
-; Clear IR interrupt request in IOC
-; Poll IOC until IR appears (if ever)
-; Set IOC timer 0 to 32 mS
-; Clear IR interrupt request in IOC
-; Poll IOC until IR appears (if ever)
-; Check timer 0 has counted down 20 mS (19.8 - 20.2 mS)
-; Return zero flag set on OK, clear on test failure.
-
-
-ts_VIDC_period ROUT
-
- ; Initialise VIDC clock and VIDC
-
- [ VIDC_Type = "VIDC1a"
- LDR r3, =VIDC_CLOCK_CONTROL ;
- MOV r1, #VIDC_CLOCK_NORMAL
- STRB r1, [r3]
- ]
-
- MOV r7, #0
- MOV r1, #ts_VIDCPhys
- ADRL r6, TestVIDCTAB
-00 LDR r0, [r6],#4 ; setup using main table
- CMP r0, #-1
- STRNE r0, [r1]
- BNE %BT00
-01 LDR r0, [r6],#4 ; enable DMA using 2nd table
- CMP r0, #-1
- STRNE r0, [r1]
- BNE %BT01
-
- ; Wait for the start of a flyback period
-
-04
- LDR r3, =IOC
- [ MEMC_Type = "IOMD"
- LDR r1, [r6] ; get FSIZE value from end of TestVIDCTAB
- STR r1, [r3, #IOMD_FSIZE]
- ]
- MOV r1, #vsync_bit
- STRB r1, [r3, #IOCIRQCLRA]
- LDR r2, =VIDC_VFLYWAIT ; long timeout loop - C 200mS
-
-05 LDRB r1, [r3, #IOCIRQSTAA]
- ANDS r1, r1, #vsync_bit
- BNE %06
- SUBS r2, r2,#1
- BNE %05
-
- LDR r0,=&fffff
- ORRS r0, r0,r7, LSL #20 ; Failed : clear 0 flag
- MOV pc, r14 ; ... and quit
-
- ; Set up IOC timer 0
-06
- LDR r1, =(32 * 1000 * 2) ; 32mS upper limit
- STRB r1, [r3, #Timer0LL]
- MOV r0, r1, LSR #8
- STRB r0, [r3, #Timer0LH]
- MOV r0, #0
- STRB r0, [r3, #Timer0GO] ; start the timer
-
- ; clear the IR and T0 bits
-
- MOV r0, #(vsync_bit :OR: timer0_bit)
- STRB r0, [r3,#IOCIRQCLRA]
-
- ; wait for what should be a complete vflyback period
-
-10 LDR r2, =VIDC_VFLYWAIT ; timeout loop - C 200 msec
-11 LDRB r0, [r3,#IOCIRQSTAA]
- TSTS r0, #vsync_bit
- BNE %14 ; wait for end of vsync
-
- TSTS r0, #timer0_bit ; or timer underflow
- BNE %13
-
-12 SUBS r2, r2, #1 ; or last-ditch timeout
- BNE %11
-
-13 ORRS r0, r0,#1 ; Failed : clear 0 flag
- MOV r0, #0 ; but return a zero
- MOV pc, r14 ; ... and quit
-
- ; finished in reasonable time : check against margins.
-
-14 STRB r0, [r3, #Timer0LR] ; latch the current count
- LDRB r2, [r3, #Timer0CL]
- LDRB r0, [r3, #Timer0CH]
- ADD r2, r2, r0, LSL #8
-
- SUB r2, r1, r2
- MOV r0, r2, LSR #1 ; Vertical flyback time in uS
-
- LDR r1, =19800 ; inside limits ?
- SUBS r2, r0, r1
- BLE %F20
-
- LDR r1, =400 ; 19.8 -> 20.2 mS
- CMPS r2, r1
- BGE %F20
- MOV r1,#0 ; OK - 0 indicates pass
-
- ; After success using the 24MHz reference clock, select the
- ; VCO clock (also at 24MHz) and ensure the test is passed after
- ; a few cycles to allow the VCO to settle.
-
-20
- [ VIDC_Type = "VIDC20"
-
- TEQ r7,#0 ; if this is the first loop ..
- BNE %FT21
- TEQ r1,#0 ; and it passed OK ..
- BNE %FT25
- MOV r2,#ts_VIDCPhys
- LDR r3,=VIDVCOFREQ ; set the vco to 24MHz
- LDR r4,=&E0000400 ; and use the vco clock
- STMIA r2,{r3,r4}
- MOV r7,#VIDVCOWAIT ; set the vco test loop count
- B %BT04 ; and run around again
-
-21 ORR r0,r0,r7,LSL #20
- SUBS r7,r7,#1 ; if all attempts now made
- BEQ %FT25 ; return final result
- TEQ r1,#0 ; else repeat until passed
- BNE %BT04
- ]
-
- ; return with zero flag set if timers were OK
- ; measured time (in uS) in r0 if flyback was wrong,
- ; bits 20+ show fail loop - 0 for refclk, 1 for vcoclk.
-
-25
- ORRS r1,r1,r1
- MOV pc, r14
-
-
- SUBT Sound DMA test
-;
-; This test runs the sound DMA system to prove the operation of VIDC and
-; MEMC's sound DMA control and the operation of the SIRQ sound DMA complete
-; interrupt.
-; To avoid making a noise, set the sound muting bit on.
-;
-; Initialise MEMC sound DMA
-; Initialise VIDC sound channel
-; Initialise timer 0 and timer 1 to guard-band 10mS sound duration
-; Poll IOC until IL1 (SIRQ interrupt) becomes active
-; Check timer 0 has completed and timer 1 has not
-;
-
-ts_SIRQ_period ROUT
-
- ; set up MEMC to point to a buffer near the start of physical RAM,
- ; labelled in r9_fiq by the early memory size tests (not MemSize)
- ; Registers are set as (address / 16)
- ; Register bits are (register * 4) in VIDC address mask
- ; Hence values written to MEMC + register offset + (pointer / 4)
-
-
- [ MEMC_Type = "IOMD"
- MOV r3,#IOMD_Base
- MOV r0,#(IOMD_DMA_C_Bit :OR: IOMD_DMA_E_Bit :OR: 16)
- STR r0,[r3,#IOMD_SD0CR]
- MOV_fiq r0,r9 ; zero the DMA buffer
- ADD r1,r0,#ts_Soundbuf_length
- MOV r2,#0
-02 STR r2,[r0],#4
- CMPS r0,r1
- BNE %BT02
- |
- MOV_fiq r0,r11_fiq
- BIC r0, r0, #MEMC_Son ; ensure sound DMA disabled
-
- STR r0, [r0]
- LDR r1, =(MEMC_SendN :OR: ((ts_Soundbuf + ts_Soundbuf_length) / 4))
- STR r1, [r1]
- LDR r2, =(MEMC_Sstart :OR: (ts_Soundbuf / 4))
- STR r2, [r2]
- LDR r0, =MEMC_Sptr ; initialise Sptr and set up again ..
- STR r0, [r0]
- STR r1, [r1]
- STR r2, [r2]
- ]
-
- ; Set up VIDC for 8 channels, 10uS (/8) per sample
-
- LDR r0, =ts_VIDCPhys
- [ VIDC_Type = "VIDC20"
- LDR r1, =VIDSCR ; VIDC10 mode, 24Mhz clock
- STR r1, [r0]
- LDR r1, =VIDDMAoff
- STR r1, [r0]
- ]
- LDR r1, =(VIDSTIM0 + 1) ; channel 0 at 100% left
- LDR r2, =((VIDSTIM1 - VIDSTIM0) + 1)
- MOV r3, #7
-05 STR r1, [r0] ; .. up to 6 at 100% right
- ADD r1, r1, r2
- SUBS r3, r3, #1
- BNE %05
- SUB r1, r1, #4 ; finally ch7 at centre again
- STR r1, [r0]
-
- LDR r1, =(VIDSFR + 8) ; 10uS/byte
- STR r1, [r0]
-
- ; Set up the timer to limit at 20 us (10uS/sample, 1024-16 bytes => 10.08 mS)
-
- LDR r3, =IOC
- LDR r1, =(20 * 1000 * 2) ; 20 mS upper limit
- STRB r1, [r3, #Timer1LL]
- MOV r0, r1, LSR #8
- STRB r0, [r3, #Timer1LH]
-
- MOV r0, #-1
- STRB r0, [r3, #IOCControl] ; mute sound (on IOC system)
- STRB r0, [r3, #Timer1GO] ; start the timer
-
- [ MEMC_Type = "IOMD"
- MOV r0, #(IOMD_DMA_E_Bit :OR: 16) ; enable the IOMD DMA
- STR r0, [r3,#IOMD_SD0CR]
- MOV_fiq r0,r9 ; set the buffer pointers
- MOV r4,#((ts_Soundbuf_length/2) - 16)
- STR r0,[r3,#IOMD_SD0CURA]
- STR r4,[r3,#IOMD_SD0ENDA]
- LDR r2,[r3,#IOMD_SD0ST]
- ORR r4,r4,#IOMD_DMA_S_Bit
- STR r0,[r3,#IOMD_SD0CURB]
- STR r4,[r3,#IOMD_SD0ENDB]
- |
- MOV_fiq r0, r11_fiq
- ORR r0, r0, #MEMC_Son
- STR r0, [r0] ; enable the MEMC1a DMA
- ]
-
- ; set long timeout, clear the IL1, T0 and T1 bits
-
- LDR r2, =VIDC_SOUNDWAIT ; lastditch timeout loop
- LDR r0, =(timer0_bit :OR: timer1_bit)
- STRB r0, [r3,#IOCIRQCLRA]
-
-
- ; Wait until sound DMA completes (or up to about 100 mS),
- ; then check timers.
-
-10
- [ MEMC_Type = "IOMD"
- LDRB r0,[r3, #IOMD_SD0ST]
- AND r0, r0, #(IOMD_DMA_O_Bit :OR: IOMD_DMA_I_Bit)
- CMPS r0, #(IOMD_DMA_O_Bit :OR: IOMD_DMA_I_Bit)
- BEQ %12
- |
- LDRB r0, [r3,#IOCIRQSTAB]
- ANDS r0, r0, #sound_IRQ_bit
- BNE %12
- ]
- LDR r0, [r3, #IOCIRQSTAA]
- ANDS r0, r0,#timer1_bit ; timeout if timer 1 expires
- BNE %11
-
- SUBS r2, r2, #1 ; or counter reaches zero
- BNE %10
-
-11 ORRS r0, r0, #1 ; Failed : clear 0 flag
- MOV r2, #0 ; return a timeout value of 0
- B %15 ; ... and quit
-
- ; finished in reasonable time : check time remaining in t1
- ; Time for DMA should be 10.24ms (1024 bytes at 10us/byte)
- ; less up to the time to use the final 16-byte transfer, 160us.
-
-12 STRB r0, [r3, #Timer1LR] ; latch the current count
- LDRB r2, [r3, #Timer1CL]
- LDRB r0, [r3, #Timer1CH]
- ADD r2, r2, r0, LSL #8
-
- SUB r2, r1, r2
- MOV r2, r2, LSR #1 ; Sound DMA time in uS
-
- LDR r1, =10030 ; inside limits ?
- SUBS r0, r2, r1
- BLE %F13
-
- LDR r1, =260 ; 10.03 -> 10.29 mS
- CMPS r0, r1
- MOVLT r1,#0 ; inside limits : set Z flag
-
-13 ORRS r1,r1,r1
-
- ; return with zero flag set if time (in r2) was within limits
-
-15
- [ MEMC_Type = "IOMD"
- MOV r0, #IOMD_DMA_C_Bit
- STR r0, [r3,#IOMD_SD0CR]
- |
- BIC r0, r0, #MEMC_Son
- STR r0, [r0]
- ]
- MOV r0, r2 ; return the long time value
- MOV pc, r14
-
-;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-;
-; Data tables: VIDC := mode 0, all palette black
-
-TestVIDCTAB
-
- [ VIDC_Type = "VIDC1a"
-
- & &00000000
- & &04000000
- & &08000000
- & &0C000000
- & &10000000
- & &14000000
- & &18000000
- & &1C000000
- & &20000000
- & &24000000
- & &28000000
- & &2C000000
- & &30000000
- & &34000000
- & &38000000
- & &3C000000
- & &40000000 ; Border -> black
- & &44000000 ; Cursor -> black
- & &48000000
- & &4C000000 ; Palette programmed (avoid messy screen on reset)
-;
-; standard mode 0 setup (except display area disabled)
-;
-
- & &807FC000
- & &8408C000
- & &881B0000
- & &8C1EC000 ; HDSR
- & &906EC000 ; HDER
- & &94770000
- & &9C400000
- & &A04DC000
- & &A4008000
- & &A8050000 ; VBSR
- & &AC098000 ; VDSR
- & &B0000000 ; VDER < VDSR to disable screen DMA B0000000
- & &B44DC000 ; VBER
- & &E00000B2
-;
-; Additional setup : cursor blanked, sound frequency test bit set
-;
- & &C0000100 ; SFR NB. TEST BIT! - also DFlynn requested value
- & &98258000 ; HCSR
- & &B8004000 ; VCSR
- & &BC400000 ; VCER
-; don't mess with the stereo image registers: sound code will set them.
- & &FFFFFFFF ; That's the lot
-
-;
-; Further registers to turn screen DMA on again (border all over)
-; Must have a video start register before video end register to get
-; a vertical flyback interrupt.
-;
- & &B0494000 ; VDER > VDSR to enable screen DMA
- & &FFFFFFFF
- ]
-
- [ VIDC_Type = "VIDC20"
-
-; This differs from the default RISC OS VIDCTAB in running from
-; the 24MHZ video ref clock. H register contents are increased by 50%.
-
-; Program Control Register first, to clear power-down bit
-
- & &E0000402 ; CR: FIFO load 16 words, 1 bpp, ck/1, rclk
- & &E0000402 ;
- & &B1000001 ; SCR: sound disabled (+use 24MHz clock)
-
-; Don't bother programming all 256 palette entries, we'll be here all night
-; Since we're setting up a 1 bit-per-pixel mode, just do colours 0 and 1
-
- & &10000000 ; Palette address register = 0
- & &00000000 ; Colour 0 = black
- & &00000000 ; Colour 1 = black
- & &407f7f7f ; Border colour = grey
- & &50000000 ; Pointer colour 1 = black
- & &60000000 ; Pointer colour 2 = black
- & &70000000 ; Pointer colour 3 = black
-
-; Get a stable display up so we get stable signals
-
- & &800005F8 ; HCR = 114 + 132 + 144 + 960 + 144 + 42
- & &8100006A ; HSWR = 114
- & &820000EA ; HBSR = 114 + 132
- & &83000174 ; HDSR = 114 + 132 + 144
- & &84000534 ; HDER = 114 + 132 + 144 + 960
- & &850005CA ; HBER = 114 + 132 + 144 + 960 + 144
- & &860000F3 ; HCSR = HDSR
-
- & &90000137 ; VCR = 3 + 19 + 16 + 256 + 16 + 2
- & &91000002 ; VSWR = 3
- & &92000015 ; VBSR = 3 + 19
- & &93000025 ; VDSR = 3 + 19 + 16
- & &94000024 ; VDER = VDSR -1 to disable sceeen DMA
- & &95000135 ; VBER = 3 + 19 + 16 + 256 + 16
- & &96000025 ; VCSR = VDSR
- & &97000025 ; VCER = VDSR
-
- & &C00F1003 ; EREG = comp sync, DACs on, ereg output ext lut
- & &D000C385 ; FSYNREG, clk = (3+1)/(5+1) * 24MHz = 16MHz
- & &F0013000 ; DCR: bus D[31:0], Hdisc
- & &FFFFFFFF
-
- & &94000125 ; VDER > VDSR to enable screen DMA
- & &FFFFFFFF
- ; FSIZE is one less than number of rasters in Vflyback
- & &00000037 ; (3 + 19 + 16 + 0 + 16 + 2) - 1
-
- ; Alternate settings for VGA monitor
-
-TestVVIDCTAB
- & &E0000402 ; CR: FIFO load 16 words, 1 bpp, ck/1, rclk
- & &E0000402 ;
- & &B1000001 ; SCR: sound disabled (+use 24MHz clock)
-
- & &10000000 ; Palette address register = 0
- & &00000000 ; Colour 0 = black
- & &00000000 ; Colour 1 = black
- & &407f7f7f ; Border colour = grey
- & &50000000 ; Pointer colour 1 = black
- & &60000000 ; Pointer colour 2 = black
- & &70000000 ; Pointer colour 3 = black
-
- & &80000310 ; HCR = 92 + 45 + 0 + 640 + 0 + 16
- & &81000054 ; HSWR = 92
- & &82000080 ; HBSR = 92 + 45
- & &83000080 ; HDSR = 92 + 45 + 0
- & &84000300 ; HDER = 92 + 45 + 0 + 640
- & &85000300 ; HBER = 92 + 45 + 0 + 640 + 0
- & &86000080 ; HCSR = HDSR
-
- & &9000020B ; VCR = 2 + 32 + 0 + 480 + 0 + 11
- & &91000001 ; VSWR = 2
- & &92000021 ; VBSR = 2 + 32
- & &93000021 ; VDSR = 2 + 32 + 0
- & &94000020 ; VDER = VDSR -1 to disable sceeen DMA
- & &95000201 ; VBER = 2 + 32 + 0 + 480 + 0
- & &96000021 ; VCSR = VDSR
- & &97000021 ; VCER = VDSR
-
- & &C0051003 ; EREG = sep/inv sync, DACs on, ereg output ext lut
- & &F0013000 ; DCR: bus D[31:0], Hdisc
- & &FFFFFFFF
-
- ]
-
- END
-
-
-
diff --git a/TestSrc/ExtIO b/TestSrc/ExtIO
index cab813c2cb33f9ec5b08ad09aa2bf10f12c6acff..2aec7cd51ac37aa36fb0e19ec17e8301f9161ce7 100644
--- a/TestSrc/ExtIO
+++ b/TestSrc/ExtIO
@@ -4,7 +4,7 @@
;
; External interface for RISC OS ROM.
; provides entry points to send byte- and word- and string-sized objects
-; and to receive byte- and word-sized objects
+; and to receive byte- and word-sized objects
;
; A minimal set of opcodes should be used (ideally, only B, LDR and ADDS)
; so that a processor test may be validly included in the internal test
@@ -28,6 +28,7 @@
; running from the 2nd ROM bank, conditioned on
; CanLiveOnROMCard. Needed because 2nd ROM bank
; isn't ghosted on the A23 line like the 1st bank.
+; 04-May-99 KJB Modified to cope with >8M ROMs.
;------------------------------------------------------------------------
@@ -35,7 +36,8 @@
;
; The test adapter senses an access to the ROM with address line A23 high.
-; Current (8M addressing space) ROMs only use address lines A2 to A22,
+;
+; 8M addressing space ROMs only use address lines A2 to A22,
; so if A23 is asserted it will be ignored (the ROMS are aliased
; into 16M of space). With no test adapter, the aliased ROM location will
; be read and may be recognised. The test adapter may selectively disable
@@ -43,16 +45,18 @@
; should be dependent on the previous ROM read operation, and will
; therefore be predictably not equal to the data read when the ROMs are
; aliased.
-; The assumption that A23 is unused may be invalidated by a later issue
-; of the PCB. Machines using larger ROMs than 8Mbytes will require explicit
-; decoding or a new communication scheme.
+;
+; On a system with >8M of ROM, A23 is now meaningful, and there is no
+; aliasing of the ROM image. In this case, we read a fixed location at the
+; end of the ROM that always contains zero - if it reads as non-zero, the
+; test adapter is signalling.
;
;
-; This section determines whether the test interface adapter exists, and
-; what variety is fitted (dumb, display or external)
-; 3 read operations are performed (a WS operation): if all of these
+; This section determines whether the test interface adapter exists, and
+; what variety is fitted (dumb, display or external)
+; 3 read operations are performed (a WS operation): if all of these
; find a ROM alias then no adapter is fitted.
;
; If an adapter responds, then a RD operation is performed - 4 strobes then
@@ -81,8 +85,27 @@ ts_GetCommand ROUT
ROUT
;
-; Load up the registers for the test interface communication -
+; Load up the registers for the test interface communication.
;
+
+; If the ROM is >8M, we will use the fixed zero word in the ROM trailer.
+; If not, we use the old scheme (in case someone is using an old ROM joiner
+; that doesn't write the correct trailer.) Because the ROM is >8M, the
+; trailer will be at an address with A23 set, as desired.
+;
+; KJB - note I haven't kept the purity of the minimal instruction set -
+; I feel that it is unlikely that there ever will be a processor test,
+; and if there is, then this won't be the only place where the purity
+; has been broken...
+
+ ASSERT ts_Alias_bits = 8*1024*1024
+
+ MOV r0,#0
+ LDR r1,[r0, #ts_ROMSIZE] ; size of ROM in bank 0
+ CMP r1,#8*1024*1024
+ SUBHI r2,r1,#20 ; zero word is at end-20
+ BHI %42
+
; Point r2 at a word which contains 0 in 0-8MB physical space.
; Note that this code doesn't cope with the case where it can't find a zero
; word anywhere in the whole ROM. I don't think that this is a problem.
@@ -95,6 +118,7 @@ ts_GetCommand ROUT
BNE %01
ADD r2, r2, #ts_Alias_bits ; point to zero word in ghost
+42
MOV r1, #-1 ; expected below
04
; do an RD operation (four strobes) to ensure interface cleared
@@ -164,7 +188,7 @@ ts_GetCommand ROUT
ADDS r5,r5,r5 ; loop until 5 bits are read
BCC %10
- ADDS r5,r4,r4 ; copy bits 7..3 to r5, bits 5..1
+ ADDS r5,r4,r4 ; copy bits 7..3 to r5, bits 5..1
ADDS r4,r0,r0 ; and read the last 3 bits to r4
11 LDR r3,[r2] ; read a bit of the byte
@@ -179,7 +203,7 @@ ts_GetCommand ROUT
; Pass the option bits (r4) to the function identified by r5.
;
- ADDS r5,r5,r5 ; index * 2 -> index * 4
+ ADDS r5,r5,r5 ; index * 2 -> index * 4
LDR r3,%12 ; pc-relative ptr to command_table
ADD pc,pc,r0
12
@@ -187,14 +211,14 @@ ts_GetCommand ROUT
ADDS r3,pc,r3 ; absolute pointer to command table
ADDS r3,r3,r5
-13 LDR r3,[r3] ; get table entry
+13 LDR r3,[r3] ; get table entry
14 ADD pc,pc,r3 ; (offset from command_table)
& 0 ; necessary padding : pc must point
; to command table when r3 is added.
;
-; This is the table of offsets to all the built-in functions.
+; This is the table of offsets to all the built-in functions.
; The top 5 bits of the command are used to index, so there are
; 32 possible entries, mostly illegal.
; Decoding of the function modifier bits is performed by multiple
@@ -226,7 +250,7 @@ ts_CRindex
DCD (ts_read_cpr15l - ts_command_table)
DCD (ts_read_cpr15h - ts_command_table)
- ; pad the table out to 31 entries
+ ; pad the table out to 31 entries
; (leave space for display vector)
OldOpt SETA {OPT}
@@ -415,17 +439,17 @@ ts_Putdata ROUT
;
; - Send the text (nul-terminated, at r4) to the display
;
-; Interface registers need to be set up : this function is called from test
+; Interface registers need to be set up : this function is called from test
; code rather than external interface code.
;
-; The display is assumed to be a standard 16 character LCD module using
+; The display is assumed to be a standard 16 character LCD module using
; the Hitachi HD44780 display controller.
; The 16-digit module uses a single 44780. This is an abnormal use of the
; controller, and requires it to be set to two-line mode, with the first
; 8 displayed characters on the first 'line', and the second 8 on the
; second 'line'. Characters sent to the second line must be written at
; character position 40 +. In order to permit different modules to be
-; fitted to later adapters, it is suggested that the first 7 characters
+; fitted to later adapters, it is suggested that the first 7 characters
; be treated as a 'title' line, and the second 8 as a 'comment' line.
; A space should always be placed at the end of the title line to
; split the display fields, unless there is no 'comment' line.
@@ -437,7 +461,7 @@ ts_Putdata ROUT
; The bits in a transmitted byte are assigned as :
;
; bit 0 - D4 } 4-bit mode data bus
-; 1 - D5 }
+; 1 - D5 }
; 2 - D6 }
; 3 - D7 }
;
@@ -446,14 +470,14 @@ ts_Putdata ROUT
; 5 - } Unassigned
; 6 - }
;
-; 7 - CPEN Interface control : 0 for enable,
+; 7 - CPEN Interface control : 0 for enable,
; 1 for disable
;
-; For each message sent, the display is first initialised, using the
-; following sequence (each byte is sent as 2 bytes, high nibble first,
+; For each message sent, the display is first initialised, using the
+; following sequence (each byte is sent as 2 bytes, high nibble first,
; with RS clear in bit 4 of each byte)
; After each byte, an RD operation is performed : this is used by the
-; interface hardware to strobe the data into the display.
+; interface hardware to strobe the data into the display.
;
;
; The message addressed by r4 is then sent (data mode : RS set in each byte)
@@ -787,7 +811,7 @@ ts_send_text_byte ROUT
;
; Character is normal text : write it to the LCD.
-; The shift loop is used to generate the inter-byte delay normally
+; The shift loop is used to generate the inter-byte delay normally
; provided by ts_recover_time. Always make sure this is long enough.
;
@@ -887,7 +911,7 @@ ts_send_cbit_upper
LDR r5,%70 ; bitcount mask for 4 data bits
ADD pc,pc,r0 ; and 4 interface control bits
70
- & (((1 :SHL: 4) + 1) :SHL: 24)
+ & (((1 :SHL: 4) + 1) :SHL: 24)
ts_send_text_lower
LDR r3,%71
@@ -993,8 +1017,8 @@ ts_send_cbit_lower
;
; Wait for about 1 seconds worth of LCD operation delays to
-; permit the operator to read the text.
-; Use of the interface's monitor allows this delay to be increased
+; permit the operator to read the text.
+; Use of the interface's monitor allows this delay to be increased
; or decreased externally.
;
@@ -1038,7 +1062,7 @@ ts_SendEnd ROUT
10
& (1 :SHL: 24)
LDR r3,%11
- ADD pc,pc,r0
+ ADD pc,pc,r0
11
& ts_recover_time ; wait before sending data bits
12 ADDS r3,r3,r3 ; for byte timing.
diff --git a/VersionASM b/VersionASM
index ff6ea2ad3aa34147d5820978f399b4c3777158c5..10f67e4cd4b2219495aa9a9049fbd7b90407aa6f 100644
--- a/VersionASM
+++ b/VersionASM
@@ -6,9 +6,9 @@
GBLS Module_MinorVersion
GBLS Module_Date
GBLS Module_FullVersion
-Module_MajorVersion SETS "4.76"
-Module_Version SETA 476
+Module_MajorVersion SETS "4.77"
+Module_Version SETA 477
Module_MinorVersion SETS ""
-Module_Date SETS "30 Apr 1999"
-Module_FullVersion SETS "4.76"
+Module_Date SETS "04 May 1999"
+Module_FullVersion SETS "4.77"
END
diff --git a/VersionNum b/VersionNum
index 68e950b7422512064e0bc346870f7af0c5dc6ece..7bac36ea6e8c47bce1217ea3df2fab3af4be0726 100644
--- a/VersionNum
+++ b/VersionNum
@@ -1,15 +1,15 @@
-/* (4.76)
+/* (4.77)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
-#define Module_MajorVersion_CMHG 4.76
+#define Module_MajorVersion_CMHG 4.77
#define Module_MinorVersion_CMHG
-#define Module_Date_CMHG 30 Apr 1999
+#define Module_Date_CMHG 04 May 1999
-#define Module_MajorVersion "4.76"
-#define Module_Version 476
+#define Module_MajorVersion "4.77"
+#define Module_Version 477
#define Module_MinorVersion ""
-#define Module_Date "30 Apr 1999"
+#define Module_Date "04 May 1999"
-#define Module_FullVersion "4.76"
+#define Module_FullVersion "4.77"