Commit 994013b4 authored by Jeffrey Lee's avatar Jeffrey Lee Committed by ROOL
Browse files

Add extra ops to hdr/Copro15ops

More data & prefetch abort registers
parent de4dfa14
......@@ -34,8 +34,8 @@ ARM_ID_reg CN 0 ;processor ID
ARM_control_reg CN 1 ;control
ARM_tbase_reg CN 2 ;translation base (MMU)
ARM_domain_reg CN 3 ;domain access control (MMU)
ARM_FSR_reg CN 5 ;Fault status reg (MMU, read only on ARM 6/7)
ARM_FAR_reg CN 6 ;Fault address reg (MMU, read only on ARM 6/7)
ARM_FSR_reg CN 5 ;fault status reg (MMU, read only on ARM 6/7)
ARM_FAR_reg CN 6 ;fault address reg (MMU, read only on ARM 6/7)
ARM67_TLBflush_reg CN 5 ;TLB flush, ARMs 6 or 7
ARM67_TLBpurge_reg CN 6 ;TLB purge entry, ARMs 6 or 7
......@@ -103,30 +103,78 @@ C15 CN 15
MCR$cond ARM_config_cp,0,$reg,ARM_control_reg,C0,0
MEND
;read MMU/external fault status
;read MMU/external data fault status
MACRO
ARM_read_FSR $reg,$cond
MRC$cond ARM_config_cp,0,$reg,ARM_FSR_reg,C0,0
MEND
;set MMU/external fault status
;set MMU/external data fault status
MACRO
ARM_write_FSR $reg,$cond
MCR$cond ARM_config_cp,0,$reg,ARM_FSR_reg,C0,0
MEND
;read MMU/external fault address
;read MMU/external data fault address
MACRO
ARM_read_FAR $reg,$cond
MRC$cond ARM_config_cp,0,$reg,ARM_FAR_reg,C0,0
MEND
; set MMU/external fault address
; set MMU/external data fault address
MACRO
ARM_write_FAR $reg,$cond
MCR$cond ARM_config_cp,0,$reg,ARM_FAR_reg,C0,0
MEND
; read ARMv7 auxilliary data fault status
MACRO
ARM_read_ADFSR $reg,$cond
MRC$cond ARM_config_cp,0,$reg,c5,c1,0
MEND
; set ARMv7 auxilliary data fault status
MACRO
ARM_write_ADFSR $reg,$cond
MCR$cond ARM_config_cp,0,$reg,c5,c1,0
MEND
;read MMU/external instruction fault status
MACRO
ARM_read_IFSR $reg,$cond
MRC$cond ARM_config_cp,0,$reg,ARM_FSR_reg,C0,1
MEND
;set MMU/external instruction fault status
MACRO
ARM_write_IFSR $reg,$cond
MCR$cond ARM_config_cp,0,$reg,ARM_FSR_reg,C0,1
MEND
;read MMU/external instruction fault address
MACRO
ARM_read_IFAR $reg,$cond
MRC$cond ARM_config_cp,0,$reg,ARM_FAR_reg,C0,2
MEND
; set MMU/external instruction fault address
MACRO
ARM_write_IFAR $reg,$cond
MCR$cond ARM_config_cp,0,$reg,ARM_FAR_reg,C0,2
MEND
; read ARMv7 auxilliary instruction fault status
MACRO
ARM_read_AIFSR $reg,$cond
MRC$cond ARM_config_cp,0,$reg,c5,c1,1
MEND
; set ARMv7 auxilliary instruction fault status
MACRO
ARM_write_AIFSR $reg,$cond
MCR$cond ARM_config_cp,0,$reg,c5,c1,1
MEND
;read ID register to register $id
;bits 15:12 of returned ID will be 0,7,8,10 for ARM 6,7,8,A
MACRO
......
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