Commit 876079a4 authored by Jeffrey Lee's avatar Jeffrey Lee Committed by ROOL
Browse files

Tidy up data abort handling

There was some redundant code needlessly pushing & popping various
registers to the stack, left behind from when we removed the code that
dealt with 26-bit processor vector reads on StrongARM & processed the
proto-OS_AbortTrap "abort indirection nodes".
parent 2b665896
......@@ -1518,7 +1518,8 @@ SysVars_StickyPointers # (10+1)*4 ;used if ChocolateSysVars is TR
! 0, "SysVars_StickyPtrs at ":CC::STR:(SysVars_StickyPointers)
]
;
Abort32_dumparea # 6*4 ;info for OS_ReadSysInfo 7 - 32-bit PSR, fault address, 32-bit PC (room for two copies)
Abort32_dumparea # 3*4 ;info for OS_ReadSysInfo 7 - 32-bit PC, 32-bit PSR, fault address
# 12 ; Spare
[ :DEF: ShowWS
! 0, "Abort32_dumparea at ":CC::STR:(Abort32_dumparea)
]
......@@ -1601,7 +1602,6 @@ PowerSave * &80 ; Gets set in PortableFlags when we've s
AlignSpace
MOSConvertBuffer # 12 ; Enough romm for 8 hex digits.
AbortIndirection # 4 ; Pointer to list of addresses and trap routines
PreVeneerRegDump # 17*4 ; room for r0-r15, spsr
[ CacheCommonErrors
......
......@@ -36,16 +36,6 @@ PAbPreVeneer ROUT
Pull "r0-r7, pc"
]
; Preliminary layout of abort indirection nodes
^ 0
AI_Link # 4
AI_Low # 4
AI_High # 4
AI_WS # 4
AI_Addr # 4
EXPORT DAbPreVeneer
DAbPreVeneer ROUT
......@@ -111,67 +101,18 @@ DAbPreVeneer ROUT
SUBNES pc, lr_abort, #8 ; and restart aborting instruction
]
MRS r0, SPSR ; r0 = PSR when we aborted
MRS r1, CPSR ; r1 = CPSR
ADD r2, r13_abort, #8*4 ; r2 -> saved register bank for r8 onwards
; Remember the details of this abort, for OS_ReadSysInfo 7
LDR r4, =ZeroPage+Abort32_dumparea+3*4 ;use temp area (avoid overwriting main area for expected aborts)
MRS r1, SPSR ; r0 = PSR when we aborted
LDR r4, =ZeroPage+Abort32_dumparea
ARM_read_FAR r3
STMIA r4, {r0,r3,lr_abort} ; dump 32-bit PSR, fault address, 32-bit PC
MOV r4, lr_abort ; move address of aborting instruction into an unbanked register
BIC r1, r1, #&1F ; knock out current mode bits
ANDS r3, r0, #&1F ; extract old mode bits (and test for USR26_mode (=0))
TEQNE r3, #USR32_mode ; if usr26 or usr32 then use ^ to store registers
[ SASTMhatbroken
STMEQIA r2!,{r8-r12}
STMEQIA r2 ,{r13,r14}^
SUBEQ r2, r2, #5*4
|
STMEQIA r2, {r8-r14}^
]
BEQ %FT05
ORR r3, r3, r1 ; and put in user's
MSR CPSR_c, r3 ; switch to user's mode
STMIA r2, {r8-r14} ; save the banked registers
MRS r5, SPSR ; get the SPSR for the aborter's mode
STR r5, [r2, #8*4] ; and store away in the spare slot on the end
; (this is needed for LDM with PC and ^)
ORR r1, r1, #ABT32_mode
MSR CPSR_c, r1 ; back to abort mode for the rest of this
05
Push "r0" ; save SPSR_abort
[ SASTMhatbroken
SUB sp, sp, #3*4
STMIA sp, {r13,r14}^ ; save USR bank in case STM ^, and also so we can corrupt them
NOP
STMDB sp!, {r8-r12}
|
SUB sp, sp, #8*4 ; make room for r8_usr to r14_usr and PC
STMIA sp, {r8-r15}^ ; save USR bank in case STM ^, and also so we can corrupt them
]
MOV r0, lr
STMIA r4, {r0,r1,r3} ; dump 32-bit PC, 32-bit PSR, fault address
SUB r11, r2, #8*4 ; r11 -> register bank
STR r4, [sp, #7*4] ; store aborter's PC in user register bank
; Call normal exception handler
90
; copy temp area to real area (we believe this is an unexpected data abort now)
LDR r0, =ZeroPage+Abort32_dumparea
LDR r1, [r0,#3*4]
STR r1, [r0]
LDR r1, [r0,#4*4]
STR r1, [r0,#4]
LDR r1, [r0,#5*4]
STR r1, [r0,#2*4]
LDR r0, =ZeroPage ; we're going to call abort handler
[ ZeroPage = 0
STR r0, [r0, #CDASemaphore] ; so allow recovery if we were in CDA
......@@ -181,28 +122,6 @@ DAbPreVeneer ROUT
]
LDR r0, [r0, #DAbHan] ; get address of data abort handler
ADD r2, r11, #8*4 ; point r2 at 2nd half of main register bank
LDMIA sp, {r8-r14}^ ; reload user bank registers
NOP ; don't access banked registers after LDM^
ADD sp, sp, #9*4 ; junk user bank stack frame + saved SPSR
MRS r1, CPSR
MRS r6, SPSR ; get original SPSR, with aborter's original mode
AND r7, r6, #&0F
TEQ r7, #USR26_mode ; also matches USR32
LDMEQIA r2, {r8-r14}^ ; if user mode then just use ^ to reload registers
NOP
BEQ %FT80
ORR r6, r6, #I32_bit ; use aborter's flags and mode but set I
BIC r6, r6, #T32_bit ; and don't set Thumb
MSR CPSR_c, r6 ; switch to aborter's mode
LDMIA r2, {r8-r14} ; reload banked registers
MSR CPSR_c, r1 ; switch back to ABT32
80
STR r0, [r13_abort, #16*4] ; save handler address at top of stack
LDR lr_abort, [r13_abort, #15*4] ; get abort address back in R14
......
......@@ -1606,18 +1606,15 @@ osri6_maxvalue * (.-4-osri6_table) :SHR: 2
; ReadSysInfo(7) - read 32-bit Abort information for last unexpected abort
; (prefetch or data)
;
; On entry: r0 = 6 (reason code)
; On entry: r0 = 7 (reason code)
;
; On exit: r1 = 32-bit PC for last abort
; r2 = 32-bit PSR for last abort
; r3 = fault address for last abort (same as PC for prefetch abort)
;
70
Push "r0"
LDR r0, =ZeroPage+Abort32_dumparea
LDMIA r0, {r2, r3}
LDR r1, [r0,#2*4]
Pull "r0"
LDR r1, =ZeroPage+Abort32_dumparea
LDMIA r1, {r1-r3}
ExitSWIHandler
; ReadSysInfo(8) - Returns summary information on host platform.
......
......@@ -167,8 +167,7 @@ DatCopy
LDR r0, =ZeroPage
STR r2, [r0, #ResetIndirection]
MOV r3, #0 ; zero-initialise abort list, and other key workspace
STR r3, [r0, #AbortIndirection]
MOV r3, #0 ; zero-initialise key bits of workspace
[ CompatibilityPage
STRB r3, [r0, #CompatibilityPageEnabled]
]
......
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