Commit 7d5bfc66 authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Delete pre-HAL and 26bit code

Detail:
  This change gets rid of the following switches from the source (picking appropriate code paths for a 32bit HAL build):
  * HAL
  * HAL26
  * HAL32
  * No26bitCode
  * No32bitCode
  * IncludeTestSrc
  * FixR9CorruptionInExtensionSWI
  Various old files have also been removed (POST code, Arc/STB keyboard drivers, etc.)
Admin:
  Identical binary to previous revision for IOMD & Raspberry Pi builds


Version 5.49. Tagged as 'Kernel-5_49'
parent bafe3084
;
; A600tlb
;
; POST procedure for checking the TLB in A600 MMU.
;
; for each of level 1, level 2 small-page, level 2 large-page
; construct page table
; flush cache
; start timer
; for 32 addresses (with different mappings)
; check address mapping
; save timer
; for same 32 addresses
; check address mapping
; compare test times (did 2nd test require table walk ?)
Use a list of addresses that cover a good mixture of virtual addresses
Build a page table that maps these to physical RAM addresses in various ways
Access the addresses in such an order that the cache rotates, scrapping
one entry each time through the list, and loading another. So each cache
entry gets used 31 times, then is lost.
Choice of physical mapping should ensure that the cache entries contain
lots of different values of page and section base addresses.
Choice of virtual test address should ensure that cache tag varies as
widely as posible, too. PRBS ?
Very widely varying values of cache tag require that a large number
of mappings exist .. if these are 2-level mappings, that requires
a lot of RAM. Page tables should be multiply-mapped.
RISC OS puts lots of stuff below the 4M mark. Limits App space to 16M
for backwards compatibility. Probably worth testing outside these
limits to ensure Gold doesn't fall over, but failure rates would be
very low.
;
; POST procedure for checking access faults (was PPL test)
;
; for each of level 1, level 2 small-page, level 2 large-page
; construct page table
; for user, supervisor mode
; check address alignment fault
; check section translation fault
; check
; check page translation fault
; for 3 domain types
; for 16 domains
; check access permissions
;
;
; POST procedure for checking IDC
;
;
; > TestSrc.ARM3
TTL RISC OS 2+ POST ARM version determination
;
; Reads ARM3 version register, returns 0 if ARM 2 fitted.
;
;------------------------------------------------------------------------
; History
;
; Date Name Comment
; ---- ---- -------
; 20-Apr-89 ArtG Initial version
;
;
;------------------------------------------------------------------------
A3Cid CN 0
A3Cfls CN 1
A3Cmod CN 2
A3Ccac CN 3
A3Cupd CN 4
A3Cdis CN 5
A3CON CP 15
ts_ARM_type
MOV r13,lr
;
; First, set up an undefined instruction vector to catch an ARM 2
; (or a faulty ARM 3 ??) when the copro instruction is run.
; Only applies on systems where ROM isn't mapped at zero.
[ CPU_Type = "ARM2" :LOR: CPU_Type = "ARM3"
MOV r0,#0 ; set a page at logical 0
MOV r1,r0
BL ts_set_cam
ADR r0,ts_ARM_undefined
LDMIA r0,{r2,r3}
MOV r1,#4
STMIA r1,{r2,r3} ; set the undefined instruction trap
]
;
; Read ARM3C0 version I.D.
;
MOV r0, #(-1) ; should always be altered
MRC A3CON,0,r0,A3Cid,A3Cid ; Read control register 0
MOV r12, r0
[ CPU_Type = "ARM2" :LOR: CPU_Type = "ARM3"
MOV r1,#0
BL ts_set_cam_idle ; remove the vector page again
]
MOVS r0, r12 ; return the ID (0 for ARM 2)
MOV pc,r13
;
; Trap to be taken when ARM 2 is fitted
;
ts_ARM_undefined
MOV r0,#0
MOVS pc,r14_svc
10
ASSERT ((%10 - ts_ARM_undefined) / 4 = 2)
END
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; > TestSrc.Cmos
TTL RISC OS 2+ POST battery-backed RAM access
;
; A function to read bytes from CMOS, for use in verifying the checksum
; and reading memory test flag & video modes.
;------------------------------------------------------------------------
; History
;
; Date Name Comment
; ---- ---- -------
; 05-Apr-91 ArtG Initial version, based on IICMod.
;
;
;------------------------------------------------------------------------
;
; in:
; R0 = device address (bit 8 - 15 register address )
; R1 = length of block to read
; R2 = initial sum value
;
; out: R0 = sum of all bytes in block
; R1 - R13 trashed
;
ts_CMOSread ROUT
MOV R13,R14
MOV R8,R2 ; initialise accumulator
MOV R7,R1 ; initialise byte counter
MOV R6,R0 ; stash register address
MOV R2, #IOC
MOV R0, #-1 ; ensure timer is ticking
STRB R0, [R2, #Timer0LL] ; (nonzero in input latch)
STRB R0, [R2, #Timer0LH]
STRB R0, [R2, #Timer0GO] ; load the count registers
BL ts_Start
BEQ %FT30 ; check clock line toggles OK
AND R0, R6, #&FE
BL ts_TXCheckAck ; transmit device address (write)
BVS %FT30
MOV R0, R6, LSR #8
BL ts_TXCheckAck ; write register address
BVS %FT30
BL ts_Start ; Extra START bit to switch modes
AND R0, R6, #&FE
ORR R0, R0, #1
BL ts_TXCheckAck ; transmit device address (read)
BVS %FT30
20
BL ts_RXByte ; read byte from bus
ADD R8, R8, R0 ; accumulate total
SUBS R7, R7, #1 ; is it last byte ?
MOVNE R0, #0 ; no, then acknowledge with 0 bit
MOVEQ R0, #1 ; yes, then don't acknowledge
BL ts_ClockData ; but always send ack clock pulse
TEQ R7, #0 ; loop, until last byte
BNE %BT20
30
MOVVS R7, #-1 ; pass error indicator to caller
BL ts_Stop
MOV R0, R8
TEQ R7, #0 ; return zero flag if read OK
MOV PC,R13
; *****************************************************************************
;
; TXCheckACK - transmit a byte and wait for slave to ACK
;
; out: Trashes r0,r1,r2,r3,r4,r5,r9,r10,r11,r12
; V bit set on error.
;
ts_TXCheckAck ROUT
MOV R12,R14
BL ts_TXByte
BL ts_Acknowledge
MOV PC, R12
; *****************************************************************************
;
; SetC1C0 - Set clock and data lines to values in R1 and R0 respectively
;
; out: Trashes r0,r1,r2,r11
;
ts_SetC1C0 ROUT
MOVS R11, R14 ; NE: indicate not checking clock
ts_SetOrCheck
MRS R14, CPSR
ORR R14, R14, #I32_bit ; disable interrupts
MSR CPSR_c, R14
ADD R0, R0, R1, LSL #1 ; R0 := C0 + C1*2
ORR R0, R0, #&C0 ; make sure two test bits are
; always set to 1 !
MOV R2, #IOC
STRB R0, [R2, #IOCControl]
10
LDREQB R1, [R2, #IOCControl] ; wait for clock
TSTEQ R1, #i2c_clock_bit ; to read high
BEQ %BT10
MOV R0, #10 ; delay for >= 10/2 microsecs
;
; in-line do-micro-delay to save a stack level
;
STRB R0, [R2, #Timer0LR] ; copy counter into output latch
LDRB R1, [R2, #Timer0CL] ; R1 := low output latch
20
STRB R0, [R2, #Timer0LR] ; copy counter into output latch
LDRB R14, [R2, #Timer0CL] ; R14 := low output latch
TEQ R14, R1 ; unchanged ?
MOVNE R1, R14 ; copy anyway
BEQ %BT20 ; then loop
SUBS R0, R0, #1 ; decrement count
BNE %BT20 ; loop if not finished
;
; end do-micro-delay
;
MOV PC, R11
; Set clock and data lines to R1 and R0 and then wait for clock to be high
ts_SetC1C0CheckClock ROUT
MOV R11, R14
CMP R0, R0 ; EQ: indicate checking clock
B ts_SetOrCheck
; *****************************************************************************
;
; ClockData - Clock a bit of data down the IIC bus
;
; in: R0 = data bit
;
; out: Trashes r0,r1,r2,r3,r10,r11
;
ts_ClockData ROUT
MOV R10,R14
MOV R3, R0 ; save data
MOV R1, #0 ; clock LO
BL ts_SetC1C0
MOV R1, #1 ; clock HI
MOV R0, R3
BL ts_SetC1C0CheckClock
; Delay here must be >= 4.0 microsecs
MOV R1, #0 ; clock LO
MOV R0, R3
BL ts_SetC1C0
MOV PC,R10
; *****************************************************************************
;
; Start - Send the Start signal
;
; out: Trashes r0,r1,r2,r9,r11
; R0 (and Z flag) indicates state of clock .. should be NZ.
;
ts_Start ROUT
MOV R9,R14
MOV R0, #1 ; clock HI, data HI
MOV R1, #1
BL ts_SetC1C0
; Delay here must be >= 4.0 microsecs
MOV R0, #0 ; clock HI, data LO
MOV R1, #1
BL ts_SetC1C0
; Make sure clock really is high (and not shorted to gnd)
LDRB R3, [R2, #IOCControl]
; Delay here must be >= 4.7 microsecs
MOV R0, #0 ; clock LO, data LO
MOV R1, #0
BL ts_SetC1C0
ANDS R0, R3, #i2c_clock_bit
MOV PC,R9
; *****************************************************************************
;
; Acknowledge - Check acknowledge after transmitting a byte
;
; out: Trashes r0,r1,r2,r3,r9,r11
; V=0 => acknowledge received
; V=1 => no acknowledge received
;
ts_Acknowledge ROUT
MOV R9,R14
MOV R0, #1 ; clock LO, data HI
MOV R1, #0
BL ts_SetC1C0
MOV R0, #1 ; clock HI, data HI
MOV R1, #1
BL ts_SetC1C0CheckClock
; Delay here must be >= 4.0 microsecs
MOV R2, #IOC
LDRB R3, [R2, #IOCControl] ; get the data from IOC
MOV R0, #1 ; clock LO, data HI
MOV R1, #0
BL ts_SetC1C0
TST R3, #1 ; should be LO for correct acknowledge
MRS R3, CPSR
BICEQ R3, R3, #V_bit ; clear V if correct acknowledge
ORRNE R3, R3, #V_bit ; set V if no acknowledge
MSR CPSR_f, R3
MOV PC,R9
; *****************************************************************************
;
; Stop - Send the Stop signal
;
; out: Trashes r0,r1,r2,r9,r11
;
ts_Stop ROUT
MOV R9,R14
MOV R0, #0 ; clock HI, data LO
MOV R1, #1
BL ts_SetC1C0
; Delay here must be >= 4.0 microsecs
MOV R0, #1 ; clock HI, data HI
MOV R1, #1
BL ts_SetC1C0
MOV PC,R9
; *****************************************************************************
;
; TXByte - Transmit a byte
;
; in: R0 = byte to be transmitted
;
; out: Trashes r0,r1,r2,r3,r4,r5,r9,r10,r11
;
ts_TXByte ROUT
MOV R9, R14
MOV R4, R0 ; byte goes into R4
MOV R5, #&80 ; 2^7 the bit mask
10
ANDS R0, R4, R5 ; zero if bit is zero
MOVNE R0, #1
BL ts_ClockData ; send the bit
MOVS R5, R5, LSR #1
BNE %BT10
MOV PC, R9
; *****************************************************************************
;
; RXByte - Receive a byte
;
; out: R0 = byte received
; Trashes r1,r2,r3,r4,r9,r11
;
ts_RXByte ROUT
MOV R9, R14
MOV R3, #0 ; byte:=0
MOV R2, #IOC
MOV R4, #7
MOV R0, #1 ; clock LO, data HI
MOV R1, #0
BL ts_SetC1C0
10
MOV R0, #1 ; pulse clock HI
MOV R1, #1
BL ts_SetC1C0CheckClock
LDRB R1, [R2, #IOCControl] ; get the data from IOC
AND R1, R1, #1
ADD R3, R1, R3, LSL #1 ; byte:=byte*2+(IOC?0)AND1
MOV R0, #1 ; return clock LO
MOV R1, #0
BL ts_SetC1C0
SUBS R4, R4, #1
BCS %BT10
MOV R0, R3 ; return the result in R0
MOV PC, R9
LTORG
END
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; > InitModule
; Source for Pre_InitModule, PostInitModule im_InitModules & im_Pre_InitPodMod functions
;
; ***********************************
; *** C h a n g e L i s t ***
; ***********************************
;
; Date Who Version Description
; ---- --- ------- -----------
; 13-Jun-96 BAR 0.01 Started
; 27-Jun-96 BAR 0.02 Added code to check the type of reset we
; just had. If power-on then we can display
; messages, else exit back.
;
;
; Provides functions to display messages for when we initiliseing the
; modules. Messages are only sent to the display adapator, if the Reset Type
; is Power On Reset. The code uses the constant ResetType, defined in
; kernel.hdr.KernelWS. This is the address of a memory location, where the
; type of reset is stored. ResetType is a sigle bit flag, in bit 0 of the
; memory location. The constant PowerOnReset is used, which is defined in
; Kernel.s.newReset. This defines the value that a power-on reset should be.
; The value of PowerOnReset should always be 1. (This corresponds to the
; value of the bit 4 of IOMD's IRQA Status register, where the Power-on
; reset status is initially stored.) The value of ResetType can vary between
; different versions of the operating system.
;
;
; im_Pre_InitModule is called before a module is started
; im_Post_InitModule is called after a module is started, only if there was
; an error
; im_InitModules is called at the start of initiliseing the modules.
; im_Pre_InitPodMod is called when we start the podule manager.
;
; All the functions will push registers r0-r12 to the stack, check the
; poweron reset status, if power on reset, then send a message to the
; display adaptor and then pull them off at the end.
;
;
im_Pre_InitModule ROUT
Push "r0-r12" ; Put r0->r12 on to stack
; Get the type of reset we had, if power-on - can use display adaptor
LDR r1,=ResetType ; Load r1 with address of ResetType
LDR r0,[r1] ; Get contents of ResetType = what type of reset
CMPS r0,#PowerOnReset ; Compare with PowerOnReset (1)
;if equel send message
LDREQ r4,[r11,#ROMModule_Name] ; Put ptr to mod name in r4
BLEQ ts_SendText ; Send the txt to disp adaptor
;restore the reg's.
Pull "r0-r12" ; Get r0->r12 from the stack
MOV pc,r14 ; Return to caller
im_Post_InitModule ROUT
1
= "Module Bad",0
Push "r0-r12" ; Put r0->r12 on to stack
; Get the type of reset we had, if power-on - can use display adaptor
LDR r1,=ResetType ; Load r1 with address of ResetType
LDR r0,[r1] ; Get contents of ResetType = what type of reset
CMPS r0,#PowerOnReset ; Compare with PowerOnReset (1)
BNE %FT2 ; IF not equal jump to 2 AKA don't send msg.
Push "r0" ; Put r0 in stack again
ADR r4, %BT1 ; r4 = bad module msg
BL ts_SendText ; Send the txt to disp adaptor
Pull "r0" ; Get r0 from the stack
ADDVC r4,r0,#4 ; If V Clr add 4 to r0 - point to err txt
BLVC ts_SendText ; Send the txt to disp adaptor
2
Pull "r0-r12" ; Get r0->r12 from the stack
MOV pc,r14 ; Return to caller
im_InitModules ROUT
1
= "Init Modules :",0
Push "r0-r12" ; Put r0->r12 on to stack
; Get the type of reset we had, if power-on - can use display adaptor
LDR r1,=ResetType ; Load r1 with address of ResetType
LDR r0,[r1] ; Get contents of ResetType = what type of reset
CMPS r0,#PowerOnReset ; Compare with PowerOnReset (1)
;if equel send message
ADREQ r4, %BT1 ; r4 = init msg
BLEQ ts_SendText ; Send the txt to disp adaptor
;restore the reg's.
Pull "r0-r12" ; Get r0->r12 from the stack
MOV pc,r14 ; Return to caller
im_Pre_InitPodMod ROUT
1
= "Podule",0
Push "r0-r12" ; Put r0->r12 on to stack
; Get the type of reset we had, if power-on - can use display adaptor
LDR r1,=ResetType ; Load r1 with address of ResetType
LDR r0,[r1] ; Get contents of ResetType = what type of reset
CMPS r0,#PowerOnReset ; Compare with PowerOnReset (1)
;if equel send message
ADREQ r4, %BT1 ; r4 = init msg
BLEQ ts_SendText ; Send the txt to disp adaptor
;restore the reg's.
Pull "r0-r12" ; Get r0->r12 from the stack
MOV pc,r14 ; Return to caller
END
; > TestSrc.IOC
TTL RISC OS 2+ POST IO controller
;
; This initial IOC test simply reports the content of the IRQ and FIRQ
; registers, to show any unexpected pending IRQs.
; Certain of these should really be cleared, and the effect of an
; interrupt tested.
;
;------------------------------------------------------------------------
; History
;
; Date Name Comment
; ---- ---- -------
; 18-Dec-89 ArtG Initial version
; 29-Nov-91 ArtG Added IOC bus test using mask registers
; 20-Jun-93 ArtG Modified for 29-bit IOMD test
; 18-Nov-94 RCM Morris changes
; 15-May-96 BAR Changes for 7500FE - new IOMD ID code.
; Now list 3 ID codes.
; 17-Jun-96 BAR Change ts_IOMD_IDn definitions to point to
; definitions in IOMDL
; 09-Jul-96 BAR Improve IOMD ID code.
;
;
;------------------------------------------------------------------------
[ IO_Type = "IOMD"
ts_IObase * IOMD_Base
ts_IOmask * &00fffff0 ;&1fffffff
ts_IOreg1 * IOMD_VIDEND ;IOMD_VIDCUR
ts_IOreg2 * IOMD_VIDSTART
ts_IObswap * 32
ts_IOMD_ID1 * IOMD_Original
ts_IOMD_ID2 * IOMD_7500
ts_IOMD_ID3 * IOMD_7500FE
|
ts_IObase * IOC
ts_IOmask * &ff0000
ts_IOreg1 * IOCIRQMSKA
ts_IOreg2 * IOCIRQMSKB
ts_IObswap * 16
]
ts_IOCreg
MOV r0,#0 ; zero error accumulator
LDR r3, =ts_IObase
MOV r1,#(1 :SHL: 31) ; initialise bit-set test mask
0
MVN r2,r1 ; make bit-clear test mask
LDR r4, =ts_IOmask
ANDS r4,r1,r4
BEQ %FT1 ; skip if this bit isn't tested
STR r1,[r3,#ts_IOreg1]
STR r2,[r3,#ts_IOreg2]
LDR r4,[r3,#ts_IOreg1]
; EOR r4, r4, r1, LSR #ts_IObswap ; check bit-set test was OK
EOR r4, r4, r1 ; check bit-set test was OK
ORR r0, r0, r4 ; accumulate errors in r0
LDR r4,[r3,#ts_IOreg2]
; EOR r4, r4, r2, LSR #ts_IObswap ; check bit-clear test was OK
EOR r4, r4, r2 ; check bit-clear test was OK
ORR r0, r0, r4 ; accumulate errors in r0
1
MOV r1, r1, LSR #1 ; shift mask downwards
TEQ r1,#0
BNE %BT0 ; and loop until all bits tested
LDR r8, =ts_IOmask
ANDS r8, r0, r8
MOV pc,r14 ; return error if any bit failed
ts_IOCstat
LDR r3, =ts_IObase ; r3 points to IO Chip base address
MOV r0,#0 ; clear r0
[ IO_Type = "IOMD"
; Check IOMD chip variants
LDRB r1,[r3,#IOMD_ID1] ; load r1 with IOMD ID high byte
LDRB r0,[r3,#IOMD_ID0] ; load r1 with IOMD ID low byte
ORR r0,r0,r1, LSL #8 ; Or r0 and r1 - shifted left 8, put in r0
LDR r1,=ts_IOMD_ID1 ; get Ref IOMD ID code #1
CMPS r0,r1 ; check =to IOMD ID Code #1
LDRNE r1,=ts_IOMD_ID2 ; If not ID1, get Ref IOMD ID code #2