Commit 79bc3343 authored by Jeffrey Lee's avatar Jeffrey Lee Committed by ROOL
Browse files

Remove CAM size limit

Previously the CAM sat inside a fixed 16MB window, restricting it to
storing the details of 1 million pages, i.e. 4GB of RAM. Shuffle things
around a bit to allow this restriction to be removed: the CAM is now
located just above the IO region, and the CAM start address /
IO top will calculated appropriately during kernel init. This change
paves the way for us to support machines with over 4GB of RAM.

FixedAreasTable has also been removed, since it's no longer really
necessary (DAs can only be created between the top of application space
and the bottom of the used IO space, and it's been a long time since
we've had any fixed bits in the middle of there)
parent b51b5540
...@@ -286,9 +286,9 @@ $label # $size ...@@ -286,9 +286,9 @@ $label # $size
MEND MEND
^ &B9000000 ^ &B9000000
IOLimit ASpace &40000000 ; initial lower limit on room for IO space (DA creation may move limit up) IOLimit ASpace &41000000 ; initial lower limit on room for IO space (DA creation may move limit up)
IO ASpace &00000000 ; works downwards ; IO start will be placed just before CAM (calculated at runtime)
PhysicalAccess ASpace &01000000, &01000000 ; 16MB allocation to permit supersection mapping CAMTop ASpace &00000000 ; top of CAM, will be allocated down from here
HALWorkspaceSize * &00100000 HALWorkspaceSize * &00100000
HALWorkspace ASpace HALWorkspaceSize HALWorkspace ASpace HALWorkspaceSize
IRQStackAddress ASpace IRQStackSize, &100000 IRQStackAddress ASpace IRQStackSize, &100000
...@@ -311,8 +311,7 @@ L1PT ASpace &00004000 ...@@ -311,8 +311,7 @@ L1PT ASpace &00004000
CursorChunkAddress ASpace &00008000 CursorChunkAddress ASpace &00008000
DuffEntry ASpace &00001000 ; No page ever mapped in here (L2PT entry always 0), also, all non mapped pages DuffEntry ASpace &00001000 ; No page ever mapped in here (L2PT entry always 0), also, all non mapped pages
Nowhere * DuffEntry ; use this as their CAM entry. There is only one 'Nowhere' (synonym). Nowhere * DuffEntry ; use this as their CAM entry. There is only one 'Nowhere' (synonym).
CAMspace * CAM_EntrySize*1024*1024 ; 1M entries = enough for 4GB of RAM PhysicalAccess ASpace &01000000, &01000000 ; 16MB allocation to permit supersection mapping
CAM ASpace CAMspace
WorkspaceLimit # 0 WorkspaceLimit # 0
GBLL ROMatTop GBLL ROMatTop
...@@ -1245,6 +1244,7 @@ Cache_HALDevice # 4 ; Pointer to any HAL cache dev ...@@ -1245,6 +1244,7 @@ Cache_HALDevice # 4 ; Pointer to any HAL cache dev
IOAllocPtr # 4 ; current lowpoint of mapped I/O space (also upper limit on DAs) IOAllocPtr # 4 ; current lowpoint of mapped I/O space (also upper limit on DAs)
IOAllocLimit # 4 ; current lowest allowed I/O space (DA creation may move this up) IOAllocLimit # 4 ; current lowest allowed I/O space (DA creation may move this up)
IOAllocTop # 4 ; high end of I/O space
PhysIllegalMask # 4 ; mask of invalid bits in upper word of physical addresses PhysIllegalMask # 4 ; mask of invalid bits in upper word of physical addresses
...@@ -1340,8 +1340,6 @@ CamMapCorruptDebugBlock # &40 ; somewhere to dump registers in case of ...@@ -1340,8 +1340,6 @@ CamMapCorruptDebugBlock # &40 ; somewhere to dump registers in case of
# (JordanWS+256*4-@) ; pad out to original size # (JordanWS+256*4-@) ; pad out to original size
CamEntriesPointer # 4 ; points to where CAM soft copy is CamEntriesPointer # 4 ; points to where CAM soft copy is
; (CamEntries for machines up to 8MBytes,
; CamEntriesForBigMachines for larger machines)
MaxCamEntry # 4 ; maximum index into the cam map, ie MaxCamEntry # 4 ; maximum index into the cam map, ie
; 511 for 16MByte machines, 383 for 12MBytes ; 511 for 16MByte machines, 383 for 12MBytes
......
...@@ -4074,21 +4074,11 @@ CheckForOverlappingAreas Entry "r0-r5" ...@@ -4074,21 +4074,11 @@ CheckForOverlappingAreas Entry "r0-r5"
CMP r5, r0 ; end must be below I/O space (allocated down from high memory) CMP r5, r0 ; end must be below I/O space (allocated down from high memory)
BHI %FT20 BHI %FT20
; check against list of fixed areas ; check against application space
LDR r1, =ZeroPage
ADR lr, FixedAreasTable LDR r1, [r1, #SoftAplWorkMaxSize]
10 CMP r3, r1
LDMIA lr!, {r0, r1} ; r0 = start addr, r1 = size BHS %FT30 ; start is beyond aplspace limit
CMP r0, #-1 ; if at end of list
BEQ %FT30 ; then OK wrt fixed areas
CMP r1, #-1 ; appspace?
LDREQ r1, =ZeroPage
LDREQ r1, [r1, #SoftAplWorkMaxSize]
ADD r1, r1, r0 ; r1 = end addr+1
CMP r5, r0 ; if end of our area is <= start of fixed, then OK wrt fixed areas
BLS %FT30
CMP r3, r1 ; if start of our area is >= end of fixed, then go onto next area
BCS %BT10
20 20
ADRL r0, ErrorBlock_OverlappingAreas ADRL r0, ErrorBlock_OverlappingAreas
...@@ -4126,22 +4116,6 @@ CheckForOverlappingAreas Entry "r0-r5" ...@@ -4126,22 +4116,6 @@ CheckForOverlappingAreas Entry "r0-r5"
CLRV ; OK exit CLRV ; OK exit
EXIT EXIT
FixedAreasTable ; table of fixed areas (address, size)
& 0, -1 ; application space (size looked up later)
[ CursorChunkAddress < IO
& CursorChunkAddress, 64*1024 ; 32K for cursor, 32K for "nowhere"
]
[ ROM < IO
[ OSROM_ImageSize > 8192
& &03800000, OSROM_ImageSize*1024 ; ROM
|
& &03800000, 8*1024*1024 ; ROM
]
]
& IO, &FFFFFFFF-IO ; Kernel workspace (code will also check dynamic value IOAllocPtr)
& -1, 0 ; termination
;************************************************************************** ;**************************************************************************
; ;
; AllocateAreaAddress - Find an area of logical space to use for this area ; AllocateAreaAddress - Find an area of logical space to use for this area
...@@ -4167,9 +4141,12 @@ AllocateAreaAddress Entry "r0-r2,r4-r7" ...@@ -4167,9 +4141,12 @@ AllocateAreaAddress Entry "r0-r2,r4-r7"
MOVS r5, r5, LSL #1 ; double size MOVS r5, r5, LSL #1 ; double size
BCS %FT90 ; if that wrapped then that's bad BCS %FT90 ; if that wrapped then that's bad
05 05
LDR r3, =DynArea_NewAreasBase ; r3 is our current attempt LDR r3, =DynArea_NewAreasBase
ADR r0, FixedAreasTable ; r0 is ptr into fixed areas table LDR r1, =ZeroPage
LDR r1, =ZeroPage+DAList ; r1 is ptr into dyn areas list LDR r1, [r1, #SoftAplWorkMaxSize]
CMP r1, r3
MOVHI r3, r1 ; r3 is our current attempt
LDR r1, =ZeroPage+DAList ; r1 is ptr into dyn areas list
10 10
ADDS r7, r3, r5 ; r7 is our end+1 ADDS r7, r3, r5 ; r7 is our end+1
BHI %FT90 ; if we wrapped (but not end+1=0) then we failed BHI %FT90 ; if we wrapped (but not end+1=0) then we failed
...@@ -4178,7 +4155,7 @@ AllocateAreaAddress Entry "r0-r2,r4-r7" ...@@ -4178,7 +4155,7 @@ AllocateAreaAddress Entry "r0-r2,r4-r7"
CMP r7, r2 CMP r7, r2
BHI %FT90 ; if we walked into IOspace (assumed higher than any DA space) then we failed BHI %FT90 ; if we walked into IOspace (assumed higher than any DA space) then we failed
15 15
BL GetNextRange ; get next range from either list (r2=start, r6=end+1) BL GetNextRange ; get next range from DA list (r2=start, r6=end+1)
CMP r7, r2 ; if end(ours) <= start(next) then this is OK CMP r7, r2 ; if end(ours) <= start(next) then this is OK
BLS %FT80 ; (note this also works when r2=-1) BLS %FT80 ; (note this also works when r2=-1)
CMP r3, r6 ; else if start(ours) >= end(next) CMP r3, r6 ; else if start(ours) >= end(next)
...@@ -4213,42 +4190,28 @@ AllocateAreaAddress Entry "r0-r2,r4-r7" ...@@ -4213,42 +4190,28 @@ AllocateAreaAddress Entry "r0-r2,r4-r7"
; ;
; Internal routine called by AllocateAreaAddress ; Internal routine called by AllocateAreaAddress
; ;
; in: r0 -> next entry in fixed list ; in: r1!0 -> next entry in dyn list
; r1!0 -> next entry in dyn list
; ;
; out: r2 = next lowest area base (-1 if none) ; out: r2 = next lowest area base (-1 if none)
; r6 = end of that range (undefined if none) ; r6 = end of that range (undefined if none)
; Either r0 or r1 updated to next one (except when r2=-1 on exit) ; r1 updated to next one (except when r2=-1 on exit)
; ;
GetNextRange Entry "r7,r8" GetNextRange Entry "r7,r8"
LDMIA r0, {r2, r6} ; load start, size from fixed list
CMP r6, #-1 ; appspace?
LDREQ r6, =ZeroPage
LDREQ r6, [r6, #SoftAplWorkMaxSize]
ADD r6, r6, r2 ; r6 = end+1
ASSERT DANode_Link = 0 ASSERT DANode_Link = 0
LDR r7, [r1, #DANode_Link] ; get next from dyn LDR r7, [r1, #DANode_Link] ; get next from dyn
TEQ r7, #0 ; if none TEQ r7, #0 ; if none
MOVEQ r8, #-1 ; then use addr -1 MOVEQ r2, #-1 ; then use addr -1
BEQ %FT10 EXIT EQ
LDR r8, [r7, #DANode_Flags] ; more double trouble LDR r8, [r7, #DANode_Flags] ; more double trouble
TST r8, #DynAreaFlags_DoublyMapped TST r8, #DynAreaFlags_DoublyMapped
LDR r8, [r7, #DANode_Base] LDR r2, [r7, #DANode_Base]
LDR lr, [r7, #DANode_MaxSize] LDR lr, [r7, #DANode_MaxSize]
SUBNE r8, r8, lr SUBNE r2, r2, lr
MOVNE lr, lr, LSL #1 MOVNE lr, lr, LSL #1
ADD lr, lr, r8 ; now r8 = start addr, lr = end+1 ADD r6, lr, r2 ; now r2 = start addr, r6 = end+1
10 MOV r1, r7
CMP r8, r2 ; if dyn one is earlier
MOVCC r2, r8 ; then use dyn start
MOVCC r6, lr ; and end
MOVCC r1, r7 ; and advance dyn ptr
EXIT CC ; then exit
CMP r2, #-1 ; else if not at end of fixed
ADDNE r0, r0, #8 ; then advance fixed ptr
EXIT EXIT
;************************************************************************** ;**************************************************************************
......
...@@ -1142,8 +1142,16 @@ MMUon_nol1ptoverlap ...@@ -1142,8 +1142,16 @@ MMUon_nol1ptoverlap
LDR a2, =ZeroPage LDR a2, =ZeroPage
LDR a1, =IOLimit LDR a1, =IOLimit
STR a1, [a2, #IOAllocLimit] STR a1, [a2, #IOAllocLimit]
LDR a1, =IO LDR a1, [a2, #SoftCamMapSize]
RSB a1, a1, #CAMTop ; Start of CAM
[ LongDesc
BFC a1, #0, #21 ; Round down to 2MB for IO start
|
MOV a1, a1, LSR #20 ; Round down to 1MB for IO start
MOV a1, a1, LSL #20
]
STR a1, [a2, #IOAllocPtr] STR a1, [a2, #IOAllocPtr]
STR a1, [a2, #IOAllocTop]
BL SetUpHALEntryTable BL SetUpHALEntryTable
...@@ -1381,7 +1389,8 @@ ROMDecompAlign * 20 ...@@ -1381,7 +1389,8 @@ ROMDecompAlign * 20
; Allocate the CAM ; Allocate the CAM
LDR a3, [v8, #SoftCamMapSize] LDR a3, [v8, #SoftCamMapSize]
LDR a2, =AreaFlags_CAM LDR a2, =AreaFlags_CAM
LDR a1, =CAM RSB a1, a3, #CAMTop
STR a1, [v8, #CamEntriesPointer]
BL Init_MapInRAM BL Init_MapInRAM
; Allocate the supervisor stack ; Allocate the supervisor stack
...@@ -1491,9 +1500,6 @@ ROMDecompAlign * 20 ...@@ -1491,9 +1500,6 @@ ROMDecompAlign * 20
MSR CPSR_c, #F32_bit+SVC2632 MSR CPSR_c, #F32_bit+SVC2632
LDR sp, =SVCSTK LDR sp, =SVCSTK
LDR ip, =CAM
STR ip, [v8, #CamEntriesPointer]
BL ConstructCAMfromPageTables BL ConstructCAMfromPageTables
MOV a1, #4096 MOV a1, #4096
...@@ -1582,7 +1588,7 @@ HAL_InvalidateCache_ARMvF ...@@ -1582,7 +1588,7 @@ HAL_InvalidateCache_ARMvF
CountPageTablePages ROUT CountPageTablePages ROUT
Entry Entry
LDR a1, =ZeroPage LDR a1, =ZeroPage
LDR a2, =CAM LDR a2, [a1, #CamEntriesPointer]
LDR a3, [a1, #MaxCamEntry] LDR a3, [a1, #MaxCamEntry]
[ ZeroPage <> 0 [ ZeroPage <> 0
MOV a1, #0 MOV a1, #0
...@@ -1644,7 +1650,7 @@ ConstructCAMfromPageTables ...@@ -1644,7 +1650,7 @@ ConstructCAMfromPageTables
Push "v1-v8, lr" Push "v1-v8, lr"
LDR a1, =ZeroPage LDR a1, =ZeroPage
LDR a2, [a1, #MaxCamEntry] LDR a2, [a1, #MaxCamEntry]
LDR v1, =CAM ; v1 -> CAM (for whole routine) LDR v1, [a1, #CamEntriesPointer] ; v1 -> CAM (for whole routine)
ADD a2, a2, #1 ADD a2, a2, #1
ADD a2, v1, a2, LSL #CAM_EntrySizeLog2 ADD a2, v1, a2, LSL #CAM_EntrySizeLog2
...@@ -2442,13 +2448,13 @@ RamSkipTable ...@@ -2442,13 +2448,13 @@ RamSkipTable
ClearFreePoolSection ROUT ClearFreePoolSection ROUT
Push "r1-r3, lr" Push "r1-r3, lr"
LDR r1, =ZeroPage LDR r3, =ZeroPage
LDR r1, [r1, #MaxCamEntry] LDR r1, [r3, #MaxCamEntry]
LDR r2, =ZeroPage+FreePoolDANode LDR r2, =ZeroPage+FreePoolDANode
CMP r0, r1 CMP r0, r1
BHI %FT30 BHI %FT30
LDR r3, =CAM LDR r3, [r3, #CamEntriesPointer]
ADD r1, r3, r1, LSL #CAM_EntrySizeLog2 ; top entry (inc) ADD r1, r3, r1, LSL #CAM_EntrySizeLog2 ; top entry (inc)
ADD r3, r3, r0, LSL #CAM_EntrySizeLog2 ; starting entry ADD r3, r3, r0, LSL #CAM_EntrySizeLog2 ; starting entry
10 10
...@@ -2544,7 +2550,8 @@ ClearFreePoolSection ROUT ...@@ -2544,7 +2550,8 @@ ClearFreePoolSection ROUT
MOV r5, r8, LSR #20 MOV r5, r8, LSR #20
ORR r5, r5, r9, LSL #12 ORR r5, r5, r9, LSL #12
TEQ r10, r5 ; same MB as previous? TEQ r10, r5 ; same MB as previous?
LDRNE r14, =CAM LDRNE r14, =ZeroPage
LDRNE r14, [r14, #CamEntriesPointer]
SUBNE r14, r11, r14 SUBNE r14, r11, r14
MOVNE r14, r14, LSR #CAM_EntrySizeLog2 ; no, so compute continuation point MOVNE r14, r14, LSR #CAM_EntrySizeLog2 ; no, so compute continuation point
SUBEQ r0, r0, #4 ; wind back to make sure we stay in the correct megabyte of PhysicalAccess SUBEQ r0, r0, #4 ; wind back to make sure we stay in the correct megabyte of PhysicalAccess
...@@ -2694,7 +2701,8 @@ RISCOS_MapInIO_PTE ; a1 bits 0-19 = L1 section entry flags, bits 20+ = our extra ...@@ -2694,7 +2701,8 @@ RISCOS_MapInIO_PTE ; a1 bits 0-19 = L1 section entry flags, bits 20+ = our extra
LDR v7, [ip, #IOAllocPtr] LDR v7, [ip, #IOAllocPtr]
MOV v7, v7, LSR #18 ; v7 = logical 2MB*8 that we're checking for a match MOV v7, v7, LSR #18 ; v7 = logical 2MB*8 that we're checking for a match
LDR v1, =LL2PT LDR v1, =LL2PT
LDR v2, =IO :SHR: 18 ; v2 = last logical 2MB*8 to check (exclusive) LDR v2, [ip, #IOAllocTop]
MOV v2, v2, LSR #18 ; v2 = last logical 2MB*8 to check (exclusive)
10 10
ADD ip, v7, v8, LSL #3 ; logical 2MB*8 of base mapping or second mapping if there is one ADD ip, v7, v8, LSL #3 ; logical 2MB*8 of base mapping or second mapping if there is one
CMP ip, v2 CMP ip, v2
...@@ -2795,7 +2803,8 @@ RISCOS_MapInIO_PTE ; a1 bits 0-19 = L1 section entry flags, bits 20+ = our extra ...@@ -2795,7 +2803,8 @@ RISCOS_MapInIO_PTE ; a1 bits 0-19 = L1 section entry flags, bits 20+ = our extra
ConstructIOPTE a4, v4, a1, lr ; a4 = first PT entry to match ConstructIOPTE a4, v4, a1, lr ; a4 = first PT entry to match
ADD v3, v3, #1 ; v3 = number of MB to step between sections or supersections ADD v3, v3, #1 ; v3 = number of MB to step between sections or supersections
LDR v1, =L1PT LDR v1, =L1PT
LDR v2, =IO :SHR: 20 ; v2 = last logical MB to check (exclusive) LDR v2, [ip, #IOAllocTop]
MOV v2, v2, LSR #20 ; v2 = last logical MB to check (exclusive)
SUB a3, a3, v3 ; no increment on first iteration SUB a3, a3, v3 ; no increment on first iteration
10 10
ADD a3, a3, v3 ; next logical MB to check ADD a3, a3, v3 ; next logical MB to check
......
...@@ -725,8 +725,8 @@ MemoryAmounts ROUT ...@@ -725,8 +725,8 @@ MemoryAmounts ROUT
B %FT97 B %FT97
40 40
LDR r1, =ZeroPage LDR r1, =ZeroPage
LDR r3, [r1, #IOAllocTop]
LDR r1, [r1, #IOAllocLimit] LDR r1, [r1, #IOAllocLimit]
LDR r3, =IO
SUB r1, r3, r1 ; IO = IO ceiling - IO floor SUB r1, r3, r1 ; IO = IO ceiling - IO floor
B %FT97 B %FT97
50 50
...@@ -1167,8 +1167,8 @@ MAI_UNDStk ...@@ -1167,8 +1167,8 @@ MAI_UNDStk
MAI_SoftCAM MAI_SoftCAM
LDR r0, =ZeroPage LDR r0, =ZeroPage
LDR r1, [r0, #CamEntriesPointer] LDR r1, [r0, #CamEntriesPointer]
LDR r2, =CAMspace LDR r2, [r0, #SoftCamMapSize]
LDR r3, [r0, #SoftCamMapSize] MOV r3, r2
EXIT EXIT
MAI_L1PT MAI_L1PT
...@@ -2117,7 +2117,8 @@ CheckMemoryAccess ROUT ...@@ -2117,7 +2117,8 @@ CheckMemoryAccess ROUT
; Hit the end of the list ; Hit the end of the list
30 30
; IO memory ; IO memory
CMP r1, #IO LDR r9, [r10, #IOAllocTop]
CMP r1, r9
BHS %FT40 BHS %FT40
MOV r3, r1, LSR #20 MOV r3, r1, LSR #20
LDR r4, [r10, #IOAllocPtr] LDR r4, [r10, #IOAllocPtr]
...@@ -2135,29 +2136,17 @@ CheckMemoryAccess ROUT ...@@ -2135,29 +2136,17 @@ CheckMemoryAccess ROUT
ADD r4, r3, #1<<20 ADD r4, r3, #1<<20
ORR r5, r5, #CMA_Partially_Phys ORR r5, r5, #CMA_Partially_Phys
BL CMA_AddRange2 BL CMA_AddRange2
CMP r4, #IO CMP r4, r9
MOV r3, r4 MOV r3, r4
BNE %BT31 BNE %BT31
40 40
; Everything else! ; Everything else!
ASSERT PhysicalAccess >= IO ASSERT CAMTop <= HALWorkspace
CMP r1, #HALWorkspace LDR r3, [r10, #CamEntriesPointer]
BHS %FT50 LDR r4, [r10, #SoftCamMapSize]
Push "r0-r2" LDR r5, =CMA_CAM
LDR r0, =PhysicalAccess BL CMA_AddRange
BL LoadAndDecodeL1Entry ASSERT HALWorkspace >= CAMTop
CMP r2, #-2
AND lr, r2, #DynAreaFlags_APBits
Pull "r0-r2"
BHS %FT50
ADD r4, r3, #PhysicalAccess
LDR r5, [r10, #MMU_PPLAccess]
LDR r3, =PhysicalAccess
LDR r5, [r5, lr, LSL #2]
ORR r5, r5, #CMA_Partially_Phys
BL CMA_AddRange2
50
ASSERT HALWorkspace > PhysicalAccess
LDR r3, =HALWorkspace LDR r3, =HALWorkspace
LDR r4, [r10, #HAL_WsSize] LDR r4, [r10, #HAL_WsSize]
LDR r5, =CMA_HALWorkspace LDR r5, =CMA_HALWorkspace
...@@ -2245,12 +2234,26 @@ CheckMemoryAccess ROUT ...@@ -2245,12 +2234,26 @@ CheckMemoryAccess ROUT
MOV r4, #32*1024 MOV r4, #32*1024
LDR r5, =CMA_CursorChunk LDR r5, =CMA_CursorChunk
BL CMA_AddRange BL CMA_AddRange
ASSERT CAM > CursorChunkAddress
LDR r3, =CAM ASSERT PhysicalAccess > CursorChunkAddress
LDR r4, [r10, #SoftCamMapSize] CMP r1, #ROM
LDR r5, =CMA_CAM BHS %FT80
BL CMA_AddRange Push "r0-r2"
ASSERT ROM > CAM LDR r0, =PhysicalAccess
BL LoadAndDecodeL1Entry
CMP r2, #-2
AND lr, r2, #DynAreaFlags_APBits
Pull "r0-r2"
BHS %FT80
ADD r4, r3, #PhysicalAccess
! 0, "LongDescTODO 1MB bodge in LoadAndDecodeL1Entry will make this wrong"
LDR r5, [r10, #MMU_PPLAccess]
LDR r3, =PhysicalAccess
LDR r5, [r5, lr, LSL #2]
ORR r5, r5, #CMA_Partially_Phys
BL CMA_AddRange2
80
ASSERT ROM > PhysicalAccess
LDR r3, =ROM LDR r3, =ROM
LDR r4, =OSROM_ImageSize*1024 LDR r4, =OSROM_ImageSize*1024
LDR r5, =CMA_ROM LDR r5, =CMA_ROM
......
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