Commit 4fd2dd01 authored by Jeffrey Lee's avatar Jeffrey Lee Committed by ROOL
Browse files

Prepare logical_to_physical for 64bit phys addrs

ppn_to_physical, logical_to_physical, physical_to_ppn & ppn_to_physical
have now all been changed to accept/receive 64bit physical addresses in
R8,R9 instead of a 32bit address in R5. However, where a phys addr is
being provided as an input, they may currently only pay attention to the
bottom 32 bits of the address.
parent fd66eeef
......@@ -3029,7 +3029,6 @@ DynArea_PMP_LogOp ROUT
BNE %FT91
LDR r11, [r10, #DANode_MaxSize]
LDR r12, [r10, #DANode_Base]
LDR r8, =L2PT
; Usage in main loop:
; r0 = number of cacheable pages being umapped
; r1 = offset in temp page list
......@@ -3039,7 +3038,7 @@ DynArea_PMP_LogOp ROUT
; r5 = current entry PMP page index
; r6 = current entry page flags
; r7 -> PMP
; r8 -> L2PT
; r8 spare
; r9 -> PMPMaxSize
; r10 -> DANode
; r11 -> DA max size
......@@ -3711,7 +3710,6 @@ DynArea_PMP_GetPages ROUT
LDR r11, =ZeroPage
LDR r5, [r10, #DANode_Base]
LDR r7, [r11, #MaxCamEntry]
LDR r8, =L2PT
LDR r11, [r11, #CamEntriesPointer]
LDR r12, =DynAreaFlags_PMPLogOpAccessMask
; Usage in main loop:
......@@ -3720,7 +3718,6 @@ DynArea_PMP_GetPages ROUT
; r5 -> DA base
; r6 -> PMP
; r7 = MaxCamEntry
; r8 -> L2PT
; r9 = PMP size
; r10 -> DANode
; r11 -> CAM
......@@ -5997,11 +5994,11 @@ DoTheGrowPagesSpecified ROUT
TST r1, #PageFlags_Required ; if this page is required for the operation
BNE %BT64 ; then try next page
Push "r3,r5,r9"
Push "r3,r5,r8,r9"
MOV r3, r6
BL ppn_to_physical
MOV r10, r5
Pull "r3,r5,r9"
MOV r10, r8
Pull "r3,r5,r8,r9"
; DREG r6, "Using page number "
68
......
......@@ -2138,7 +2138,7 @@ ClearFreePoolSection ROUT
LDR r14, [r3, #CAM_PMPIndex] ; list index
LDR r9, [r2, #DANode_PMP] ; PMP list base
LDR r3, [r9, r14, LSL #2] ; ppn
BL ppn_to_physical ; => r5 = PA
BL ppn_to_physical ; => r8,r9 = PA
[ MEMM_Type = "ARM600"
; Map in this section, cacheable + bufferable to ensure burst writes
......@@ -2150,17 +2150,20 @@ ClearFreePoolSection ROUT
; PL310 L2 cache)
LDR a1, =OSAP_None + DynAreaFlags_NotCacheable
]
MOV a2, r5
MOV a3, #0
MOV a2, r8
MOV a3, r9
MOV a4, #0
BL RISCOS_AccessPhysicalAddressUnchecked
MOV r5, r8, LSR #20
ORR r5, r5, r9, LSL #12 ; r5 = physical MB
MOV r4, #0 ; clear to this value
MOV r6, r4
MOV r7, r4
MOV r8, r4
MOV r12, r4
45
MOV r8, r4
MOV r9, r4
MOV r10, r4
MOV r11, r4
......@@ -2173,6 +2176,8 @@ ClearFreePoolSection ROUT
TEQ r0, r2
BNE %BT50
MOV r10, r5 ; previous phys MB
; Step the CAM until there are no more pages in that section
LDR r1, [sp, #1*4]
LDR r2, [sp, #2*4]
......@@ -2194,22 +2199,27 @@ ClearFreePoolSection ROUT
MOV r14, #-1 ; CAM top, no more
B %FT80
70
MOV r10, r5 ; previous PA
; Next PMP entry in the free pool
LDR r14, [r11, #CAM_PMPIndex] ; list index
LDR r9, [r2, #DANode_PMP] ; PMP list base
LDR r3, [r9, r14, LSL #2] ; ppn
BL ppn_to_physical ; => r5 = PA
BL ppn_to_physical ; => r8,r9 = PA
MOV r14, r10, LSR #20
TEQ r14, r5, LSR #20 ; same MB as previous?
MOV r5, r8, LSR #20
ORR r5, r5, r9, LSL #12
TEQ r10, r5 ; same MB as previous?
LDRNE r14, =CAM
SUBNE r14, r11, r14
MOVNE r14, r14, LSR #CAM_EntrySizeLog2 ; no, so compute continuation point
LDREQ r0, =PhysicalAccess
MOVEQ r14, r5, LSL #12
ORREQ r0, r0, r14, LSR #12
SUBEQ r0, r0, #4 ; wind back to make sure we stay in the correct megabyte of PhysicalAccess
[ NoARMT2
MOVEQ r0, r0, LSR #20
ORREQ r0, r0, r8, LSL #12
MOVEQ r0, r0, ROR #12
|
BFIEQ r0, r8, #0, #20
]
STREQ r11, [sp, #3*4]
BEQ %BT45 ; yes, so clear it
80
......@@ -2220,8 +2230,8 @@ ClearFreePoolSection ROUT
MOV r4, r0
MOV r0, #L1_B
MOV r1, r10
MOV r2, #0
MOV r1, r10, LSL #20
MOV r2, r10, LSR #12
MOV r3, #0
BL RISCOS_AccessPhysicalAddress
......@@ -2436,10 +2446,9 @@ RISCOS_AddDevice
RISCOS_LogToPhys ROUT
Push "r4,r5,r8,r9,lr"
MOV r4, a1
LDR r8, =L2PT
BL logical_to_physical
MOVCC a2, #0 ; assume L2 page tables only used for bottom 4GB for now
MOVCC a1, r5
MOVCC a1, r8
MOVCC a2, r9
BCC %FT10
; Try checking L1PT for any section mappings (logical_to_physical only
; deals with regular 4K page mappings)
......
......@@ -164,12 +164,12 @@ MemoryConvertNoFIQCheck ROUT
LDR r6, =ZeroPage
LDR r7, [r6, #MaxCamEntry]
LDR r6, [r6, #CamEntriesPointer]
LDR r8, =L2PT
10
SUBS r2, r2, #1
BCC %FT70
LDMIA r1!, {r3-r5} ; Get next three word entry (PN,LA,PA) and move on pointer.
LDMIA r1!, {r3-r4,r8} ; Get next three word entry (PN,LA,PA) and move on pointer.
MOV r9, #0 ; Top half of PA is zero
[ AMB_LazyMapIn
BL handle_AMBHonesty ; may need to make page honest (as if not lazily mapped)
......@@ -186,7 +186,7 @@ MemoryConvertNoFIQCheck ROUT
BCS %FT80
TST r0, #logical,wanted
STRNE r4, [r1, #-8] ; Store back LA if wanted.
STR r5, [r1, #-4] ; Store back PA.
STR r8, [r1, #-4] ; Store back PA.
20
TST r0, #alter_cacheable ; If altering cacheability
EORNE lr, r0, #ppn,given ; and PN not given
......@@ -241,6 +241,7 @@ MemoryConvertNoFIQCheck ROUT
BNE %BT10 ; Do next entry if we don't have to change L2.
MOV r4, r4, LSR #12
LDR r8, =L2PT
LDR r3, =ZeroPage
ADD r4, r8, r4, LSL #2 ; Address of L2 entry for logical address.
[ MEMM_Type = "VMSAv6"
......@@ -334,11 +335,11 @@ MemoryConvertNoFIQCheck ROUT
[ AMB_LazyMapIn
;
; entry: r3,r4,r5 = provided PN,LA,PA triple for entry to make honest (at least one given)
; entry: r3,r4,r8,r9 = provided PN,LA,PA triple for entry to make honest (at least one given)
; r0 bits flag which of PN,LA,PA are given
; exit: mapping made honest (as if not lazily mapped) if necessary
handle_AMBHonesty ROUT
Push "r0, r3-r5, lr"
Push "r0, r3-r4, lr"
TST r0, #logical,given
BEQ %FT10
MOV r0, r4
......@@ -354,14 +355,14 @@ handle_AMBHonesty ROUT
20
TST r0, #physical,given
BEQ %FT90
Push "r7, r9-r11"
Push "r5, r7, r10-r11"
LDR r14, =ZeroPage
LDR r7, [r14, #MaxCamEntry]
BL physical_to_ppn
Pull "r7, r9-r11"
Pull "r5, r7, r10-r11"
BCC %BT15
90
Pull "r0, r3-r5, pc"
Pull "r0, r3-r4, pc"
] ;AMB_LazyMapIn
......@@ -370,11 +371,11 @@ handle_AMBHonesty ROUT
; ppn_to_logical
;
; In: r3 = page number
; r5 = physical address if given
; r8,r9 = physical address if given
; r6 = CamEntriesPointer
; r7 = MaxCamEntry
;
; Out: r9 corrupted
; Out: r5 corrupted
; CC => r4 = logical address
; CS => invalid page number
;
......@@ -387,9 +388,13 @@ ppn_to_logical
ASSERT CAM_LogAddr=0
LDR r4, [r6, r3, LSL #CAM_EntrySizeLog2] ; If valid then lookup logical address.
TST r0, #physical,given ; If physical address was given then
LDRNE r9, =&FFF
ANDNE r9, r5, r9 ; mask off page offset
ORRNE r4, r4, r9 ; and combine with logical address.
[ NoARMT2
LDRNE r5, =&FFF
ANDNE r5, r8, r5 ; mask off page offset
ORRNE r4, r4, r5 ; and combine with logical address.
|
BFINE r4, r8, #0, #12 ; apply page offset
]
CLC
MOV pc, lr
......@@ -398,19 +403,19 @@ ppn_to_logical
; logical_to_physical
;
; In: r4 = logical address
; r8 = L2PT
;
; Out: r9 corrupted
; CC => r5 = physical address
; CS => invalid logical address, r5 corrupted
; Out: r5 corrupt
; CC => r8,r9 = physical address
; CS => invalid logical address, r8,r9 corrupted
;
; Convert logical address to physical address.
;
logical_to_physical
LDR r5, =L2PT
MOV r9, r4, LSR #12 ; r9 = logical page number
ADD r9, r8, r9, LSL #2 ; r9 -> L2PT entry for logical address
MOV r5, r9, LSR #12 ; r5 = page offset to L2PT entry for logical address
LDR r5, [r8, r5, LSL #2] ; r5 = L2PT entry for L2PT entry for logical address
ADD r9, r5, r9, LSL #2 ; r9 -> L2PT entry for logical address
MOV r8, r9, LSR #12 ; r8 = page offset to L2PT entry for logical address
LDR r8, [r5, r8, LSL #2] ; r8 = L2PT entry for L2PT entry for logical address
[ MEMM_Type = "ARM600"
ASSERT ((L2_SmallPage :OR: L2_ExtPage) :AND: 2) <> 0
ASSERT (L2_LargePage :AND: 2) = 0
......@@ -418,22 +423,27 @@ logical_to_physical
ASSERT L2_SmallPage = 2
ASSERT L2_XN = 1 ; Because XN is bit 0, bit 1 is the only bit we can check when looking for small pages
]
TST r5, #2 ; Check for valid (4K) page.
TST r8, #2 ; Check for valid (4K) page.
BEQ meminfo_returncs
LDR r5, [r9] ; r5 = L2PT entry for logical address
TST r5, #2 ; Check for valid (4K) page.
LDR r8, [r9] ; r8 = L2PT entry for logical address
TST r8, #2 ; Check for valid (4K) page.
BEQ meminfo_returncs
[ NoARMT2
LDR r9, =&FFF ; Valid so
BIC r5, r5, r9 ; mask off bits 0-11,
BIC r8, r8, r9 ; mask off bits 0-11,
AND r9, r4, r9 ; get page offset from logical page
ORR r5, r5, r9 ; combine with physical page address.
ORR r8, r8, r9 ; combine with physical page address.
|
BFI r8, r4, #0, #12 ; Valid, so apply offset within the page
]
MOV r9, #0 ; 4K pages are always in the low 4GB
CLC
MOV pc, lr
meminfo_returncs_pullr5
Pull "r5"
meminfo_returncs_pullr8
Pull "r8"
meminfo_returncs
SEC
MOV pc, lr
......@@ -441,31 +451,31 @@ meminfo_returncs
;----------------------------------------------------------------------------------------
; physical_to_ppn
;
; In: r5 = physical address
; In: r8,r9 = physical address
; r7 = MaxCamEntry
;
; Out: r9-r11 corrupted
; Out: r5,r10-r11 corrupted
; CC => r3 = page number
; CS => invalid physical address, r3 corrupted
;
; Convert physical address to physical page number.
;
physical_to_ppn ROUT
Push "r5"
LDR r9, =ZeroPage+PhysRamTable
Push "r8"
LDR r5, =ZeroPage+PhysRamTable
MOV r3, #0 ; Start at page 0.
MOV r5, r5, LSR #12
MOV r8, r8, LSR #12
10
CMP r7, r3 ; Stop if we run out of pages
BCC meminfo_returncs_pullr5
BCC meminfo_returncs_pullr8
LDMIA r9!, {r10,r11} ; Get start address and size of next block.
SUB r10, r5, r10, LSR #12 ; Determine if given address is in this block.
LDMIA r5!, {r10,r11} ; Get start address and size of next block.
SUB r10, r8, r10, LSR #12 ; Determine if given address is in this block.
CMP r10, r11, LSR #12
ADDCS r3, r3, r11, LSR #12 ; Move on to next block.
BCS %BT10
Pull "r5"
Pull "r8"
ADD r3, r3, r10
CLC
......@@ -476,24 +486,25 @@ physical_to_ppn ROUT
;
; In: r3 = page number
;
; Out: r9 corrupted
; CC => r5 = physical address
; CS => invalid page number, r5 corrupted
; Out: r5 corrupted
; CC => r8,r9 = physical address
; CS => invalid page number, r8,r9 corrupted
;
; Convert physical page number to physical address.
;
ppn_to_physical ROUT
Push "r3,lr"
LDR r9, =ZeroPage+PhysRamTable
LDR r5, =ZeroPage+PhysRamTable
10
LDMIA r9!, {r5,lr} ; Get start address and size of next block.
LDMIA r5!, {r8,lr} ; Get start address and size of next block.
MOVS lr, lr, LSR #12
BEQ %FT20
CMP r3, lr
SUBHS r3, r3, lr
BHS %BT10
ADD r5, r5, r3, LSL #12
ADD r8, r8, r3, LSL #12
MOV r9, #0
Pull "r3,pc"
20
SEC
......@@ -1459,7 +1470,6 @@ DMAPrep ROUT
; Get the params needed for address translation
LDR r6, [r10, #CamEntriesPointer]
LDR r7, [r10, #MaxCamEntry]
LDR r8, =L2PT
; Init workspace
STR r6, [sp, #DMAPrepW_CamEntriesPointer]
; Get the cache line mask value
......@@ -1639,9 +1649,8 @@ DMAPrep_CallInputFunc
; Translate the start of InChunk into a block
; In: r4 = Address to translate
; r7 = MaxCamEntry
; r8 -> L2PT
; Out: r4, r5, r6 = block
; r1, r3, r9-r12 corrupt
; r1, r3, r8-r12 corrupt
DMAPrep_Translate
MOV r1, lr
LDR r12, [sp, #DMAPrepW_InChunk+8]
......@@ -1656,39 +1665,45 @@ DMAPrep_Translate
BL AMB_MakeHonestLA
MOV r0, r9
]
BL logical_to_physical ; r4, r8 -> r5
BLCC physical_to_ppn ; r5, r7 -> r3
BL logical_to_physical ; r4 -> r8, r9
BLCC physical_to_ppn ; r7, r8, r9 -> r3
BCS %BT95
; r9-r11 corrupt
; r5,r10-r11 corrupt
; Grab page flags
ADD lr, r6, r3, LSL #CAM_EntrySizeLog2
LDR lr, [lr, #CAM_PageFlags]
B %FT30
20
MOV r5, r4
BL physical_to_ppn ; r5, r7 -> r3
MOV r8, r4
MOV r9, #0
BL physical_to_ppn ; r7, r8, r9 -> r3
BCS %BT95
; r9-r11 corrupt
; r5, r10-r11 corrupt
; Manual ppn -> logical so we can get the page flags at the same time
; TODO this won't deal with mapped out pages in a sensible manner (will output them all individually)
[ AMB_LazyMapIn
MOV r9, r0
MOV r10, r0
MOV r0, r3
BL AMB_MakeHonestPN
MOV r0, r9
MOV r0, r10
]
ADD lr, r6, r3, LSL #CAM_EntrySizeLog2
ASSERT CAM_LogAddr=0
ASSERT CAM_PageFlags=4
LDMIA lr, {r3, lr}
; Merge in the offset within the page
[ NoARMT2
MOV r3, r3, LSR #12
ORR r4, r3, r4, LSL #20
MOV r4, r4, ROR #20
|
BFI r3, r4, #0, #12
MOV r4, r3
]
30
LDR r3, [sp, #DMAPrepW_InChunk+4]
; Combine the cacheability + phys offset into r5
SUB r5, r5, r4
SUB r5, r8, r4 ; r5 = phys-log
TST lr, #DynAreaFlags_NotCacheable
ORR r5, r3, r5, LSR #12
ORRNE r5, r5, #DMAPrep_NonCacheable
......@@ -1783,7 +1798,7 @@ ChangeCompatibility ROUT
MOV r4, #0
BL logical_to_physical
BL physical_to_ppn
; r9-r11 corrupt, r3 = page number, r5 = phys addr
; r5, r10-r11 corrupt, r3 = page number, r8,r9 = phys addr
MOV r0, #OSMemReason_FindAccessPrivilege
MOV r1, #2_100100
MOV r2, #2_100100
......@@ -2259,7 +2274,6 @@ CMA_Done
BICHS r2, r2, lr
MOVLO r2, r4
; r2 is now page aligned min(r2+1,r4)
LDR r8, =L2PT
TST r5, #CMA_DecodeAP
BIC r4, r1, lr
BNE %FT35
......@@ -2289,6 +2303,7 @@ CMA_Done
BCS %FT45
; Get the L2PT entry and decode the flags
Push "r0-r3"
LDR r8, =L2PT
LDR r0, [r8, r4, LSR #10]
BL DecodeL2Entry ; TODO bit wasteful. We only care about access privileges, but this call gives us cache info too. Also, if we know the L2PT backing exists (it should do) we could skip the logical_to_physical call
; r2 = DA flags
......
......@@ -515,9 +515,8 @@ MakePageTablesCacheable ROUT
BL AdjustMemoryPageFlags
; Update the TTBR
LDR r4, =L1PT
LDR r8, =L2PT
BL logical_to_physical
MOV r0, r5
MOV r0, r8 ; Assume only 32bit address
LDR r1, =ZeroPage
BL SetTTBR
; Perform a full TLB flush to make sure the new mappings are visible
......@@ -540,9 +539,8 @@ MakePageTablesNonCacheable ROUT
LDR r0, =AreaFlags_PageTablesAccess :OR: DynAreaFlags_NotCacheable :OR: DynAreaFlags_NotBufferable
STR r0, [r4, #PageTable_PageFlags]
LDR r4, =L1PT
LDR r8, =L2PT
BL logical_to_physical
MOV r0, r5
MOV r0, r8 ; Assume only 32bit address
LDR r1, =ZeroPage
BL SetTTBR
; Perform a full TLB flush just in case
......@@ -559,19 +557,18 @@ MakePageTablesNonCacheable ROUT
; In:
; R0 = new page flags
; R1 = base of area
; R1 = base of area (page aligned)
; R2 = size of area
AdjustMemoryPageFlags ROUT
Entry "r0-r12"
LDR r8, =L2PT
LDR r12, =ZeroPage
LDR r7, [r12, #MaxCamEntry]
MOV r4, r1
10
BL logical_to_physical ; CC if page exists, r5 = phys addr
BL logical_to_physical ; CC if page exists, r8,r9 = phys addr
BLCC physical_to_ppn
BCS %FT90
; r9-r11 corrupt, r3 = page number, r5 = phys addr
; r5,r10-r11 corrupt, r3 = page number, r8,r9 = phys addr
Push "r0,r2,r4"
MOV r2, r3
MOV r3, r4
......@@ -596,7 +593,8 @@ AdjustMemoryPageFlags ROUT
; be performing cacheable accesses, so the maintenance performed by
; BangCamUpdate won't have done anything useful.
; So start by flushing the L2PT word from the cache.
ADD r0, r8, r3, LSR #10 ; -> L2PT entry we modified
LDR r0, =L2PT
ADD r0, r0, r3, LSR #10 ; -> L2PT entry we modified
LDRB r2, [r12, #DCache_LineLen]
SUB r2, r2, #1
BIC r0, r0, r2
......
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