Commit 46081bca authored by Jeffrey Lee's avatar Jeffrey Lee Committed by ROOL
Browse files

Log -> phys conversion improvements

* RISCOS_LogToPhys upgraded to allow it to cope with all page types
(added support for 64KB "large" pages and lazily-mapped pages)

* Added OS_Memory 65, which calls through to RISCOS_LogToPhys, to allow
regular software to do logical-to-physical conversions for all page
types (other calls, like OS_Memory 0/64, typically only work with 4KB
pages)

* LoadAndDecodeL2Entry updated to always return a page/entry size, like
LoadAndDecodeL1Entry

Version 6.56. Tagged as 'Kernel-6_56'
parent ba993cb5
......@@ -9,12 +9,12 @@
GBLS Module_ApplicationDate
GBLS Module_HelpVersion
GBLS Module_ComponentName
Module_MajorVersion SETS "6.55"
Module_Version SETA 655
Module_MajorVersion SETS "6.56"
Module_Version SETA 656
Module_MinorVersion SETS ""
Module_Date SETS "20 Mar 2021"
Module_ApplicationDate SETS "20-Mar-21"
Module_Date SETS "28 Apr 2021"
Module_ApplicationDate SETS "28-Apr-21"
Module_ComponentName SETS "Kernel"
Module_FullVersion SETS "6.55"
Module_HelpVersion SETS "6.55 (20 Mar 2021)"
Module_FullVersion SETS "6.56"
Module_HelpVersion SETS "6.56 (28 Apr 2021)"
END
/* (6.55)
/* (6.56)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
#define Module_MajorVersion_CMHG 6.55
#define Module_MajorVersion_CMHG 6.56
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 20 Mar 2021
#define Module_Date_CMHG 28 Apr 2021
#define Module_MajorVersion "6.55"
#define Module_Version 655
#define Module_MajorVersion "6.56"
#define Module_Version 656
#define Module_MinorVersion ""
#define Module_Date "20 Mar 2021"
#define Module_Date "28 Apr 2021"
#define Module_ApplicationDate "20-Mar-21"
#define Module_ApplicationDate "28-Apr-21"
#define Module_ComponentName "Kernel"
#define Module_FullVersion "6.55"
#define Module_HelpVersion "6.55 (20 Mar 2021)"
#define Module_LibraryVersionInfo "6:55"
#define Module_FullVersion "6.56"
#define Module_HelpVersion "6.56 (28 Apr 2021)"
#define Module_LibraryVersionInfo "6:56"
......@@ -149,6 +149,7 @@ OSMemReason_AccessPhysAddr64 * 22 ; Temporarily map in 64-bit phys addr
OSMemReason_ReservePages * 23 ; Reserve (or un-reserve) pages
OSMemReason_CheckMemoryAccess * 24 ; Return attributes/permissions for a logical address range
OSMemReason_Convert64 * 64 ; Convert PA <-> LA <-> PN, alter cacheability, with 64bit addresses
OSMemReason_LogToPhys * 65 ; Convert LA -> PA, supporting all page types
; OS_Memory 17/18 permission flags
MemPermission_UserX * 1<<0 ; Executable in user mode
......
......@@ -412,12 +412,13 @@ Get1MPTE_ShortDesc
; r0,r1 = phys addr
; r2 = page flags
; or -1 if fault
; r3 = page size (bytes)
; r3 = entry size/alignment (bytes)
LoadAndDecodeL2Entry_ShortDesc ROUT
LDR r1, =L2PT
LDR r0, [r1, r0, LSR #10]
ANDS r3, r0, #3
MOVEQ r2, #-1
MOVEQ r3, #4096
MOVEQ pc, lr
Entry "r4-r6"
; Get AP bits in low bits
......
......@@ -2694,28 +2694,35 @@ RISCOS_AddDevice
B HardwareDeviceAdd_Common
; uint64_t RISCOS_LogToPhys(const void *log)
; Returns -1 for invalid addresses
; Also returns mapping size/alignment in r3 (for OS_Memory 65)
RISCOS_LogToPhys ROUT
Push "r4,r5,r8,r9,lr"
MOV r4, a1
PTOp logical_to_physical
MOVCC a1, r8
MOVCC a2, r9
BCC %FT10
; Try checking L1PT for any section mappings (logical_to_physical only
; deals with regular 4K page mappings)
; TODO - Add large page support
Push "lr"
MOV r12, a1
MOV r0, a1, LSR #20
MOV r0, r0, LSL #20
PTOp LoadAndDecodeL1Entry
CMP r2, #-2
BHS %FT10
MOVHS a1, #-1 ; No L1 page
MOVHS a2, #-1
SUBLO r3, r3, #1 ; Valid L1 page, apply sub-page offset
ANDLO r4, r4, r3
ADDLO a1, r0, r4
10
Pull "r4,r5,r8,r9,pc"
BNE %FT50
; L2 page table pointer. Because we've already checked L1PT, there
; shouldn't be any need for us to check if the relevant logical mapping
; of L2PT exists (like logical_to_physical does).
MOV r0, r12, LSR #12
MOV r0, r0, LSL #12
[ AMB_LazyMapIn
BL AMB_MakeHonestLA
]
PTOp LoadAndDecodeL2Entry
CMP r2, #-2
50
MOVHI r0, #-1 ; Translation fault
MOVHI r1, #-1
Pull "pc",HI
; Valid mapping, add in the low address bits
SUB r2, r3, #1
AND r12, r12, r2
ORR r0, r0, r12
Pull "pc"
; int RISCOS_IICOpV(IICDesc *descs, uint32_t ndesc_and_bus)
RISCOS_IICOpV ROUT
......
......@@ -93,6 +93,7 @@ MemReturn
80
B MemoryConvert64 ; 64
B MemoryLogToPhys ; 65
90 ; End of list
......@@ -2629,6 +2630,41 @@ CMA_Done
Pull "r2,r4,r5,r8,r9,r10,lr"
B %BT05
;----------------------------------------------------------------------------------------
;
; In: r0 = flags
; bit meaning
; 0-7 65 (reason code)
; 8-31 reserved (set to 0)
; r1 = logical address
;
; Out: r0,r1 = physical address
; r2 = size/alignment of mapping
; For invalid addresses:
; r0 = "Address not recognised" error
; r1 corrupt
; r2 = size/alignment of mapping (so caller knows how much
; to skip)
;
; Convert a logical address to a physical address. Supports all page types
; (unlike other logical -> physical SWIs, which only cope with regular
; 4KB RAM pages).
;
MemoryLogToPhys ROUT
CMP r0, #OSMemReason_LogToPhys
BNE %FT99
Entry "r3"
MOV r0, r1
BL RISCOS_LogToPhys
MOV r2, r3
CMP r0, #-1
CMPEQ r1, #-1
ADREQL r0, ErrorBlock_BadAddress
SETV EQ
EXIT
99
B MemoryBadParameters
LTORG
END
......@@ -377,16 +377,16 @@ Get2MPTE_LongDesc
; r0,r1 = phys addr
; r2 = page flags
; or -1 if fault
; r3 = page size (bytes)
; r3 = entry size/alignment (bytes)
LoadAndDecodeL2Entry_LongDesc ROUT
LDR r1, =LL3PT
ADD r0, r1, r0, LSR #9
LDRD r0, [r0]
ASSERT LL_Fault = 0
TST r0, #LL_TypeMask
MOV r3, #4096
MOVEQ r2, #-1
MOVEQ pc, lr
MOV r3, #4096
05 ; Arrive here from LoadAndDecodeL1Entry
Entry "r4-r5"
LDR lr, =ZeroPage
......
......@@ -341,12 +341,13 @@ Get1MPTE_ShortDesc
; r0,r1 = phys addr
; r2 = page flags
; or -1 if fault
; r3 = page size (bytes)
; r3 = entry size/alignment (bytes)
LoadAndDecodeL2Entry_ShortDesc ROUT
LDR r1, =L2PT
LDR r0, [r1, r0, LSR #10]
TST r0, #3
MOVEQ r2, #-1
MOVEQ r3, #4096
MOVEQ pc, lr
Entry "r4-r6"
; Find entry in PPL table
......
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