Commits (5)
  • Jeffrey Lee's avatar
    Use official error block. Disallow instantiation. Warn clients before finalising. · b881f3cf
    Jeffrey Lee authored
    Detail:
      Resources/UK/Messages, s/Errors, hdr/VFPSupport - Errors now declared in public header. New/updated error messages and symbols.
      s/GetAll - Changed GET order to work with errors in header file
      s/Module - Disallow instantiation. Manually issue Service_ModulePostFinal during finalisation, to give clients slightly more warning than the kernel does.
    Admin:
      Tested in OMAP3 ROM
    
    
    Version 0.03. Tagged as 'VFPSupport-0_03'
    b881f3cf
  • Jeffrey Lee's avatar
    Add initial VFPv1/VFPv2 support · 28c505b0
    Jeffrey Lee authored
    Detail:
      s/Module:
      - CheckHardware can now correctly determine that the ARM1176JZF-S is ARMv6, not ARMv7
      - Added initial support for VFPv1/v2; currently only supports implementations that use FSTMX/FLDMX standard format 1, and for which we know we can read the MVFR0/MVFR1 registers. I.e. only VFP11 supported at present.
      - Fixed null pointer dereference in ExamineContext when examining the active context
    Admin:
      Tested on Raspberry Pi with high processor vectors
      Note there is no support code present, so using the coprocessor outside of RunFast mode will result in aborts.
    
    
    Version 0.04. Tagged as 'VFPSupport-0_04'
    28c505b0
  • Jeffrey Lee's avatar
    Fix save/restore of contexts which have pending exceptions · 48d821ca
    Jeffrey Lee authored
    Detail:
      s/Module - Fixed context save & restore code to ensure FPEXC EX & FP2V bits are clear when accessing FPSCR and the main VFP registers. Without doing this, attempting to save or restore a context which has a pending exception will trigger an exception itself.
      Test/test2,ffb - Simple test to make sure save/restore of contexts with pending exceptions works properly
      Test/test1,ffb - Added brief description, changed file from plain text to tokenised BASIC to prevent it accidentally happening later on
    Admin:
      Tested on Raspberry Pi
      Programs which need support code to run or trigger math exceptions no longer trigger an undefined instruction abort from within VFPSupport
    
    
    Version 0.05. Tagged as 'VFPSupport-0_05'
    48d821ca
  • Jeffrey Lee's avatar
    Move VFPSupport to 'mixed' folder · 04c27221
    Jeffrey Lee authored
    Detail:
      This is a copy of VFPSupport-0_05 from bsd/RiscOS/Sources/HWSupport
      It's being moved to the 'mixed' folder as the next version will contain sources using several different licences
    Admin:
      Untested
    
    
    Version 0.05. Retagged as 'VFPSupport-0_05'
    04c27221
  • Jeffrey Lee's avatar
    Add VFPv2 support code · a5596610
    Jeffrey Lee authored
    Detail:
      This update adds the support code necessary to allow the VFPv2 coprocessor in the Raspberry Pi to be used in its full IEEE-compliant mode, and to add support for the generation of errors on VFP match exceptions (division by zero, etc.)
      SoftFloat Release 2b (http://www.jhauser.us/arithmetic/SoftFloat.html) is used to perform the floating point calculations in software, ensuring their accuracy.
      As with FPEmulator, the support code will only be included on machines which require it; at the moment this decision is handled by the makefile, based around the target machine type.
      Note that the current version of the support code does not implement default NaN or flush-to-zero mode, so it is not a fully accurate emulation of the hardware.
      Also added a new SWI, VFPSupport_ExceptionDump, for creating and reading a VFP context exception dump, and a new reason code to VFPSupport_Features to query which exception enable bits are supported
      File changes:
      - Makefile - Rewritten to use the CModule fragment, and to add the necessary rules for (optionally) building the support code.
      - Licences - File summarising the different licences used by different portions of the code
      - Test/test2c,ffb, Test/test3,ffb, Test/test4,ffb, Test/test5,ffb, Test/test6src,ffb - Several test programs for validating behaviour of the support code, mainly focused around unusual causes of exceptions and validating instruction decoding and short vector support
      - actions/ARMv7_VFP, arctions/common, c/head, cache/classify - decgen files for building the instruction decoder. This decoder is only used for synchronous exceptions, to determine whether the instruction is or isn't a valid VFP instruction. Asynchronous exceptions utilise a simpler, hand-crafted decoder in the assembler sources.
      - h/classify - Header for the decgen decoder
      - hdr/shared - Header with some definitions shared between the C and assembler sources (will be Hdr2H'd to generate the C header)
      - hdr/VFPSupport - Updated with new error numbers, SWI definitions
      - s/CSupport - Math support functions from the C library sources, required by SoftFloat
      - s/Errors - Added new error definitions
      - s/GetAll - Include support code if necessary. Add debug switch, plus optimisation switch for machines with 16 D registers
      - s/Instructions - Core data processing instruction emulation code. This file is included twice, once for single precision and once for double precision. The code calls through to the SoftFloat routines to perform the calculations.
      - s/Module - Adjust handling of undefined instruction vector to allow the support code to be installed instead of OldHandler if necessary. Initialise the support code as necessary. Add new SWIs & reason codes.
      - s/SupportCode - Undefined instruction handler which controls the rest of the support code. Also raises RISC OS errors as necessary (division by zero, etc.)
      - softfloat/* - The SoftFloat library sources. It's been tweaked in a few places for integration with the assembler support code, but otherwise no changes to the core logic were necessary.
      - Resources/UK/Messages - Updated with new error text
    Admin:
      Tested on Raspberry Pi & BB-xM
      Support code tested using the supplied test routines and the TestFloat tool (http://www.jhauser.us/arithmetic/TestFloat.html)
    
    
    Version 0.06. Tagged as 'VFPSupport-0_06'
    a5596610
hdr/** gitlab-language=armasm linguist-language=armasm linguist-detectable=true
s/** gitlab-language=armasm linguist-language=armasm linguist-detectable=true
*,ffb gitlab-language=bbcbasic linguist-language=bbcbasic linguist-detectable=true
c/** gitlab-language=c linguist-language=c linguist-detectable=true
**/c/** gitlab-language=c linguist-language=c linguist-detectable=true
h/** gitlab-language=c linguist-language=c linguist-detectable=true
**/h/** gitlab-language=c linguist-language=c linguist-detectable=true
Copyright (c) 2010, RISC OS Open Ltd
Some source code is distributed under the New BSD License:
Copyright (c) 2010-2015, RISC OS Open Ltd
All rights reserved.
Redistribution and use in source and binary forms, with or without
......@@ -23,3 +26,235 @@ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
Some source code is distributed under the SoftFloat License:
SoftFloat was written by me, John R. Hauser. This work was made possible in
part by the International Computer Science Institute, located at Suite 600,
1947 Center Street, Berkeley, California 94704. Funding was partially
provided by the National Science Foundation under grant MIP-9311980. The
original version of this code was written as part of a project to build
a fixed-point vector processor in collaboration with the University of
California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek.
THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL
LOSSES, COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO
FURTHERMORE EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER
SCIENCE INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES,
COSTS, OR OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE
SOFTWARE.
Derivative works are acceptable, even for commercial purposes, provided
that the minimal documentation requirements stated in the source code are
satisfied.
Some source code is distributed under the Apache License:
Apache License
Version 2.0, January 2004
http://www.apache.org/licenses/
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s/CSupport - Apache licence
softfloat/* - SoftFloat licence (see softfloat/ReadMe)
Everything else - ROOL BSD licence
Note that the CSupport and SoftFloat sources are only included in the build if SUPPORTCODE is enabled in the makefile.
......@@ -28,11 +28,70 @@
# Makefile for VFPSupport
#
# Use machine type to determine whether support code is needed
# Can also be overridden on command line by specifying SUPPORTCODE
DEFSUPPORTCODE = FALSE
ifneq (,$(findstring ${MACHINE},All All32 ARM11ZF))
DEFSUPPORTCODE = TRUE
endif
SUPPORTCODE ?= ${DEFSUPPORTCODE}
COMPONENT = VFPSupport
HEADER1 = VFPSupport
ROM_SOURCE = GetAll.s
ASMHDRS = VFPSupport
OBJS = GetAll
HDRS =
CMHGFILE =
ASMDEFINES += -PD "SupportCode SETL {${SUPPORTCODE}}"
RAMASMDEFINES += -PD "standalone SETL {TRUE}" -PD "MergedMsgs SETS \"${MERGEDMSGS}\""
ifeq (${SUPPORTCODE},TRUE)
OBJS += softfloat classify
VPATH = softfloat
endif
include CModule
# We don't want to link to CLib
CLIB =
ROMCSTUBS =
ABSSYM =
CFLAGS += -apcs /nofp
# Force -cpu 5 when building for 'all' to reduce assembler support code
# requirements. This shouldn't pose a problem since the C code will only get hit
# once we've verified VFP hardware is present (i.e. ARMv5+ CPU)
ifneq (,$(findstring ${MACHINE},All All32))
CFLAGS += -cpu 5
endif
# decgen rules
ACTIONS = actions/common \
actions/ARMv7_VFP
ENCODINGS = Build:decgen.encodings.ARMv7 \
Build:decgen.encodings.ARMv7_nASIMD \
Build:decgen.encodings.ARMv7_VFP
DECGEN = <Tools$Dir>.Misc.decgen.decgen
classify.c: $(ACTIONS) head.c $(ENCODINGS)
$(DECGEN) -bits=32 -e -DCDP= -DLDC_STC= -DMRC_MCR= -DVFP1=(cond:4) "-DVFP2={ne(cond,15)}" -DAS1(X)=1111001[X] -DAS2=11110100 $(ENCODINGS) -valid -a $(ACTIONS) -pre head.c -o classify.c -prefix=classify_ -name=classify -default=UNDEFINED -updatecache cache/classify -maxmaskbits=3
classify.o: classify.c shared.h
${CC} ${CFLAGS} -o $@ classify.c
classify.oz: classify.c shared.h
${CC} ${CFLAGS} ${C_MODULE} -o $@ classify.c
shared.h: hdr.shared
${PERL} Build:Hdr2H hdr.shared $@
softfloat.o: shared.h
include StdTools
include AAsmModule
clean::
${RM} c.classify
${RM} h.shared
# Dynamic dependencies:
#{DictTokens}
NoVFP:No VFP/NEON hardware present
BadVFP:Unsupported VFP/NEON version
FeatureUnavailable:A requested feature is unavailable
BadContext:Bad context
BadFeature:Bad VFPSupport_Features reason code
# Regular errors
E00:No VFP/NEON hardware present
E01:Unsupported VFP/NEON version
E02:A requested VFP/NEON feature is unavailable
E03:Bad VFP context
E04:Bad VFPSupport_Features reason code
E06:Only one instance of VFPSupport can be active at a time
E07:Invalid flags passed to VFPSupport SWI
# Serious errors from support code
S00:No VFP context active
S01:VFP coprocessor not enabled
S02:VFP coprocessor enable state mismatch
S03:Unexpected VFP instruction
S04:Divide by zero in VFP suppport code
S05:Unknown VFP exception requested
# Actual floating point exception errors
IO:Vector floating point exception: invalid operation
DZ:Vector floating point exception: division by zero
OF:Vector floating point exception: overflow
UF:Vector floating point exception: underflow
IX:Vector floating point exception: inexact operation
ID:Vector floating point exception: input subnormal
No preview for this file type
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......@@ -11,13 +11,13 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "0.02"
Module_Version SETA 2
Module_MajorVersion SETS "0.06"
Module_Version SETA 6
Module_MinorVersion SETS ""
Module_Date SETS "01 Feb 2011"
Module_ApplicationDate SETS "01-Feb-11"
Module_Date SETS "08 Feb 2014"
Module_ApplicationDate SETS "08-Feb-14"
Module_ComponentName SETS "VFPSupport"
Module_ComponentPath SETS "bsd/RiscOS/Sources/HWSupport/VFPSupport"
Module_FullVersion SETS "0.02"
Module_HelpVersion SETS "0.02 (01 Feb 2011)"
Module_ComponentPath SETS "mixed/RiscOS/Sources/HWSupport/VFPSupport"
Module_FullVersion SETS "0.06"
Module_HelpVersion SETS "0.06 (08 Feb 2014)"
END
/* (0.02)
/* (0.06)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.02
#define Module_MajorVersion_CMHG 0.06
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 01 Feb 2011
#define Module_Date_CMHG 08 Feb 2014
#define Module_MajorVersion "0.02"
#define Module_Version 2
#define Module_MajorVersion "0.06"
#define Module_Version 6
#define Module_MinorVersion ""
#define Module_Date "01 Feb 2011"
#define Module_Date "08 Feb 2014"
#define Module_ApplicationDate "01-Feb-11"
#define Module_ApplicationDate "08-Feb-14"
#define Module_ComponentName "VFPSupport"
#define Module_ComponentPath "bsd/RiscOS/Sources/HWSupport/VFPSupport"
#define Module_ComponentPath "mixed/RiscOS/Sources/HWSupport/VFPSupport"
#define Module_FullVersion "0.02"
#define Module_HelpVersion "0.02 (01 Feb 2011)"
#define Module_LibraryVersionInfo "0:2"
#define Module_FullVersion "0.06"
#define Module_HelpVersion "0.06 (08 Feb 2014)"
#define Module_LibraryVersionInfo "0:6"
#
# Copyright(c)2014, RISC OS Open Ltd
# Allrightsreserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# * Neither the name of RISC OS Open Ltd nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
# These actions will fully classify VFP instructions, up to and including VFPv4
# Any unpredictable instructions will also be flagged (as CLASS_NOT_VFP), as we
# can't guarantee that attempting to re-execute them won't result in further
# synchronous exceptions (plus they might completely trash the system!)
VABS_A2(D,sz,M,nonstandard)
{
COMMON_sz_nonstandard(0)
D32_CHECK(sz,D)
D32_CHECK(sz,M)
return class;
}
VADD_fp_A2(D,sz,N,M,nonstandard)
{
COMMON_sz_nonstandard(0)
D32_CHECK(sz,D)
D32_CHECK(sz,N)
D32_CHECK(sz,M)
return class;
}
VCMP_VCMPE_A1(D,sz,M,nonstandard)
{
COMMON_sz_nonstandard(0)
D32_CHECK(sz,D)
D32_CHECK(sz,M)
return class;
}
VCMP_VCMPE_A2(D,sz,nonstandard)
{
COMMON_sz_nonstandard(0)
D32_CHECK(sz,D)
return class;
}
VCVT_VCVTR_fp_int_VFP_A1(D,opc2,sz,M,nonstandard)
{
COMMON_sz_nonstandard(0)
if(!(opc2 & 4))
{
/* Int to float */
D32_CHECK(sz,D);
}
else
{
/* Float to int */
D32_CHECK(sz,M);
}
return class;
}
VCVT_fp_fx_VFP_A1(D,sf,nonstandard)
{
COMMON_nonstandard(CLASS_VFP3)
if(sf)
class |= CLASS_D;
else
class |= CLASS_S;
D32_CHECK(sf,D)
return class;
}
VCVT_dp_sp_A1(D,sz,M,nonstandard)
{
COMMON_nonstandard(CLASS_S | CLASS_D);
D32_CHECK(sz,M)
D32_CHECK(!sz,D)
return class;
}
VCVTB_VCVTT_hp_sp_VFP_A1(nonstandard)
{
int class = CLASS_VFP3 | CLASS_HP;
if(nonstandard)
return CLASS_NOT_VFP;
return class;
}
VDIV_A1(D,sz,N,M,nonstandard)
{
COMMON_sz_nonstandard(CLASS_DIV)
D32_CHECK(sz,D)
D32_CHECK(sz,N)
D32_CHECK(sz,M)
return class;
}
VFMA_VFMS_A2(D,sz,N,M,nonstandard)
{
COMMON_sz_nonstandard(CLASS_VFP4)
D32_CHECK(sz,D)
D32_CHECK(sz,N)
D32_CHECK(sz,M)
return class;
}
VFNMA_VFNMS_A1(D,sz,N,M,nonstandard)
{
COMMON_sz_nonstandard(CLASS_VFP4)
D32_CHECK(sz,D)
D32_CHECK(sz,N)
D32_CHECK(sz,M)
return class;
}
VLDM_A1(D:Vd,W,Rn,imm8,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
uint32_t regs = imm8>>1;
_UNPREDICTABLE((Rn==15) && W);
_UNPREDICTABLE(!regs || (regs > 16) || ((D_Vd+regs) > 32));
if(imm8 & 1)
{
_UNPREDICTABLE(D_Vd+regs > 16);
}
if(D_Vd+regs > 16)
class |= CLASS_D32;
return class;
}
VLDM_A2(Vd:D,W,Rn,imm8,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
uint32_t regs = imm8;
_UNPREDICTABLE((Rn==15) && W);
_UNPREDICTABLE(!regs || ((Vd_D+regs) > 32));
return class;
}
VLDR_A1(D,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
if(D)
class |= CLASS_D32;
return class;
}
VLDR_A2(nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
return class;
}
VMLA_VMLS_fp_A2(D,sz,N,M,nonstandard)
{
COMMON_sz_nonstandard(0)
D32_CHECK(sz,D)
D32_CHECK(sz,N)
D32_CHECK(sz,M)
return class;
}
VMOV_imm_A2(D,sz,nonstandard)
{
COMMON_sz_nonstandard(CLASS_VFP3)
D32_CHECK(sz,D)
return class;
}
VMOV_reg_A2(D,sz,M,nonstandard)
{
COMMON_sz_nonstandard(0)
D32_CHECK(sz,D)
D32_CHECK(sz,M)
return class;
}
VMOV_arm_A1(opc1,D,Rt,opc2,nonstandard)
{
int class = CLASS_NOT_CDP;
if(nonstandard || (opc1 & 2) || (opc2 & 3))
return CLASS_NOT_VFP;
if(D)
class |= CLASS_D32;
_UNPREDICTABLE(Rt==15);
return class;
}
VMOV_scalar_A1(U,opc1,N,Rt,opc2,nonstandard)
{
int class = CLASS_NOT_CDP;
if(nonstandard || U || (opc1 & 2) || (opc2 & 3))
return CLASS_NOT_VFP;
if(N)
class |= CLASS_D32;
_UNPREDICTABLE(Rt==15);
return class;
}
VMOV_1fp_A1(Rt,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
_UNPREDICTABLE(Rt==15);
return class;
}
VMOV_2fp_A1(op,Rt2,Rt,Vm:M,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
_UNPREDICTABLE((Rt==15) || (Rt2==15) || (Vm_M==31));
if(op)
{
_UNPREDICTABLE(Rt==Rt2);
}
return class;
}
VMOV_dbl_A1(op,Rt2,Rt,M,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
_UNPREDICTABLE((Rt==15) || (Rt2==15));
if(op)
{
_UNPREDICTABLE(Rt==Rt2);
}
if(M)
class |= CLASS_D32;
return class;
}
VMUL_fp_A2(D,sz,N,M,nonstandard)
{
COMMON_sz_nonstandard(0)
D32_CHECK(sz,D)
D32_CHECK(sz,N)
D32_CHECK(sz,M)
return class;
}
VNEG_A2(D,sz,M,nonstandard)
{
COMMON_sz_nonstandard(0)
D32_CHECK(sz,D)
D32_CHECK(sz,M)
return class;
}
VNMLA_VNMLS_VNMUL_A1(D,sz,N,M,nonstandard)
{
COMMON_sz_nonstandard(0)
D32_CHECK(sz,D)
D32_CHECK(sz,N)
D32_CHECK(sz,M)
return class;
}
VNMLA_VNMLS_VNMUL_A2(D,sz,N,M,nonstandard)
{
COMMON_sz_nonstandard(0)
D32_CHECK(sz,D)
D32_CHECK(sz,N)
D32_CHECK(sz,M)
return class;
}
VPOP_A1(D:Vd,imm8,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
uint32_t regs = imm8>>1;
_UNPREDICTABLE(!regs || (regs > 16) || ((D_Vd+regs) > 32));
if(imm8 & 1)
{
_UNPREDICTABLE(D_Vd+regs > 16);
}
if(D_Vd+regs > 16)
class |= CLASS_D32;
return class;
}
VPOP_A2(Vd:D,imm8,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
uint32_t regs = imm8;
_UNPREDICTABLE(!regs || ((Vd_D+regs) > 32));
return class;
}
VPUSH_A1(D:Vd,imm8,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
uint32_t regs = imm8>>1;
_UNPREDICTABLE(!regs || (regs > 16) || ((D_Vd+regs) > 32));
if(imm8 & 1)
{
_UNPREDICTABLE(D_Vd+regs > 16);
}
if(D_Vd+regs > 16)
class |= CLASS_D32;
return class;
}
VPUSH_A2(Vd:D,imm8,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
uint32_t regs = imm8;
_UNPREDICTABLE(!regs || ((Vd_D+regs) > 32));
return class;
}
VSQRT_A1(D,sz,M,nonstandard)
{
COMMON_sz_nonstandard(CLASS_SQRT)
D32_CHECK(sz,D)
D32_CHECK(sz,M)
return class;
}
VSTM_A1(D:Vd,W,Rn,imm8,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
uint32_t regs = imm8>>1;
_UNPREDICTABLE((Rn==15) && W);
_UNPREDICTABLE(!regs || (regs > 16) || ((D_Vd+regs) > 32));
if(imm8 & 1)
{
_UNPREDICTABLE(D_Vd+regs > 16);
}
if(D_Vd+regs > 16)
class |= CLASS_D32;
return class;
}
VSTM_A2(Vd:D,W,Rn,imm8,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
uint32_t regs = imm8;
_UNPREDICTABLE((Rn==15) && W);
_UNPREDICTABLE(!regs || ((Vd_D+regs) > 32));
return class;
}
VSTR_A1(D,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
if(D)
class |= CLASS_D32;
return class;
}
VSTR_A2(nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
return class;
}
VSUB_fp_A2(D,sz,N,M,nonstandard)
{
COMMON_sz_nonstandard(0)
D32_CHECK(sz,D)
D32_CHECK(sz,N)
D32_CHECK(sz,M)
return class;
}
VMRS_A1(reg,Rt,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
_UNPREDICTABLE((Rt==15) && (reg != REG_FPSCR));
if(!(VMRS_MASK & (1<<reg)))
return CLASS_NOT_VFP;
/* Follow ARMv7 rules and limit user mode to only the FPSCR register */
if((reg != REG_FPSCR) && !privileged_mode())
return CLASS_NOT_VFP;
return class;
}
VMSR_A1(reg,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
if(!(VMSR_MASK & (1<<reg)))
return CLASS_NOT_VFP;
/* Follow ARMv7 rules and limit user mode to only the FPSCR register */
if((reg != REG_FPSCR) && !privileged_mode())
return CLASS_NOT_VFP;
return class;
}
#
# Copyright (c) 2014, RISC OS Open Ltd
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# * Neither the name of RISC OS Open Ltd nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
# Common actions for ARM disassembly
UNDEFINED()
{
(void) OPCODE;
return CLASS_NOT_VFP;
}
UNPREDICTABLE()
{
(void) OPCODE;
return CLASS_NOT_VFP;
}
UNALLOCATED_HINT()
{
(void) OPCODE;
return CLASS_NOT_VFP;
}
PERMA_UNDEFINED()
{
(void) OPCODE;
return CLASS_NOT_VFP;
}
UNALLOCATED_MEM_HINT()
{
(void) OPCODE;
return CLASS_NOT_VFP;
}
/*
* Copyright (c) 2014, RISC OS Open Ltd
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of RISC OS Open Ltd nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include "classify.h"
/* This file has the generated disassembler source appended to it */
File added
/*
* Copyright (c) 2014, RISC OS Open Ltd
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of RISC OS Open Ltd nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef CLASSIFY_H
#define CLASSIFY_H
#include <stdint.h>
#include <stdbool.h>
#include "shared.h"
/* decgen bits */
#define RETURNTYPE int
#define PARAMDECL uint32_t opcode
#define PARAMS opcode
#define PARAMSCOMMA ,
#define OPCODE opcode
extern RETURNTYPE classify(PARAMDECL);
/* Helper macros */
#define COMMON_sz_nonstandard(base) \
(void) OPCODE; \
int class = base; \
if(nonstandard) \
return CLASS_NOT_VFP; \
if(sz) \
class |= CLASS_D; \
else \
class |= CLASS_S;
#define COMMON_nonstandard(base) \
(void) OPCODE; \
int class = base; \
if(nonstandard) \
return CLASS_NOT_VFP; \
#define D32_CHECK(sz,high) if((sz) && (high)) class |= CLASS_D32;
#define _UNPREDICTABLE(cond) if(cond) return CLASS_NOT_VFP;
/* Which registers are valid for reading/writing (in privileged modes) */
#define VMRS_MASK ((1<<REG_FPSID)+(1<<REG_FPSCR)+(1<<REG_MVFR1)+(1<<REG_MVFR0)+(1<<REG_FPEXC)+(1<<REG_FPINST)+(1<<REG_FPINST2))
#define VMSR_MASK ((1<<REG_FPSCR)+(1<<REG_FPEXC)+(1<<REG_FPINST)+(1<<REG_FPINST2))
static inline bool privileged_mode(void)
{
int value;
__asm
{
LDR value,[sl,#UserPSR]
}
return (value & 0xf);
}
#endif
......@@ -43,6 +43,7 @@ SWIClass SETS VFPSupportSWI_Name
AddSWI ActiveContext
AddSWI Version
AddSWI Features
AddSWI ExceptionDump
VFPSupportSWICheckValue * @
......@@ -83,6 +84,14 @@ VFPSupport_Field_RegDump * 5
; Reason codes for Features
VFPSupport_Features_SystemRegs * 0
VFPSupport_Features_VFPExceptions * 1
; Flags for ExceptionDump
VFPSupport_ExceptionDump_GetDump * 1 :SHL: 0
VFPSupport_ExceptionDump_GetContext * 1 :SHL: 1
VFPSupport_ExceptionDump_Clear * 1 :SHL: 2
VFPSupport_ExceptionDump_Create * 1 :SHL: 3
; VFP status register fields, as per ARMv7 ARM
......@@ -107,12 +116,14 @@ FPSCR_OFC * 1 :SHL: 2
FPSCR_UFC * 1 :SHL: 3
FPSCR_IXC * 1 :SHL: 4
FPSCR_IDC * 1 :SHL: 7
FPSCR_CUMULATIVE_FLAGS * FPSCR_IOC+FPSCR_DZC+FPSCR_OFC+FPSCR_UFC+FPSCR_IXC+FPSCR_IDC
FPSCR_IOE * 1 :SHL: 8
FPSCR_DZE * 1 :SHL: 9
FPSCR_OFE * 1 :SHL: 10
FPSCR_UFE * 1 :SHL: 11
FPSCR_IXE * 1 :SHL: 12
FPSCR_IDE * 1 :SHL: 15
FPSCR_ENABLE_FLAGS * FPSCR_IOE+FPSCR_DZE+FPSCR_OFE+FPSCR_UFE+FPSCR_IXE+FPSCR_IDE
FPSCR_LEN_SHIFT * 16
FPSCR_LEN_MASK * 7 :SHL: 16
FPSCR_STRIDE_SHIFT * 20
......@@ -133,5 +144,36 @@ FPSCR_Z * 1 :SHL: 30
FPSCR_N * 1 :SHL: 31
; Errors
^ ErrorBase_VFPSupport
AddError VFPSupport_NoHW, "No VFP/NEON hardware present"
AddError VFPSupport_BadHW, "Unsupported VFP/NEON version"
AddError VFPSupport_FeatureUnavailable, "A requested VFP/NEON feature is unavailable"
AddError VFPSupport_BadContext, "Bad VFP context"
AddError VFPSupport_BadFeature, "Bad VFPSupport_Features reason code"
AddError VFPSupport_NoHW2, "VFPSupport module or VFP/NEON coprocessor not found" ; Generic error for VFP/NEON dependent programs to use. Where possible programs should use custom error text to specify the exact hardware required - VFPv1, NEON, etc.
AddError VFPSupport_Instanced, "Only one instance of VFPSupport can be active at a time"
AddError VFPSupport_BadFlags, "Invalid flags passed to VFPSupport SWI"
^ ErrorBase_VectorFloatingPoint
; Floating point exception errors
AddError VFPSupport_IO, "Vector floating point exception: invalid operation"
AddError VFPSupport_DZ, "Vector floating point exception: division by zero"
AddError VFPSupport_OF, "Vector floating point exception: overflow"
AddError VFPSupport_UF, "Vector floating point exception: underflow"
AddError VFPSupport_IX, "Vector floating point exception: inexact operation"
AddError VFPSupport_ID, "Vector floating point exception: input subnormal"
; Errors generated by the support code - numbered from top end of block down, to keep separate from the errors programmers should expect to see
AddError VFPSupport_SupCode_NoContext, "No VFP context active", ErrorBase_VectorFloatingPoint+&FF
AddError VFPSupport_SupCode_NotEN, "VFP coprocessor not enabled", ErrorBase_VectorFloatingPoint+&FE
AddError VFPSupport_SupCode_ENMismatch, "VFP coprocessor enable state mismatch", ErrorBase_VectorFloatingPoint+&FD
AddError VFPSupport_SupCode_Unexpected, "Unexpected VFP instruction", ErrorBase_VectorFloatingPoint+&FC
AddError VFPSupport_SupCode_SupDiv0, "Divide by zero in VFP support code", ErrorBase_VectorFloatingPoint+&FB
AddError VFPSupport_SupCode_UnkExcep, "Unknown VFP exception requested", ErrorBase_VectorFloatingPoint+&FA
OPT OldOpt
END