Commits (1)
  • Jeffrey Lee's avatar
    Add VFPv2 support code · a5596610
    Jeffrey Lee authored
    Detail:
      This update adds the support code necessary to allow the VFPv2 coprocessor in the Raspberry Pi to be used in its full IEEE-compliant mode, and to add support for the generation of errors on VFP match exceptions (division by zero, etc.)
      SoftFloat Release 2b (http://www.jhauser.us/arithmetic/SoftFloat.html) is used to perform the floating point calculations in software, ensuring their accuracy.
      As with FPEmulator, the support code will only be included on machines which require it; at the moment this decision is handled by the makefile, based around the target machine type.
      Note that the current version of the support code does not implement default NaN or flush-to-zero mode, so it is not a fully accurate emulation of the hardware.
      Also added a new SWI, VFPSupport_ExceptionDump, for creating and reading a VFP context exception dump, and a new reason code to VFPSupport_Features to query which exception enable bits are supported
      File changes:
      - Makefile - Rewritten to use the CModule fragment, and to add the necessary rules for (optionally) building the support code.
      - Licences - File summarising the different licences used by different portions of the code
      - Test/test2c,ffb, Test/test3,ffb, Test/test4,ffb, Test/test5,ffb, Test/test6src,ffb - Several test programs for validating behaviour of the support code, mainly focused around unusual causes of exceptions and validating instruction decoding and short vector support
      - actions/ARMv7_VFP, arctions/common, c/head, cache/classify - decgen files for building the instruction decoder. This decoder is only used for synchronous exceptions, to determine whether the instruction is or isn't a valid VFP instruction. Asynchronous exceptions utilise a simpler, hand-crafted decoder in the assembler sources.
      - h/classify - Header for the decgen decoder
      - hdr/shared - Header with some definitions shared between the C and assembler sources (will be Hdr2H'd to generate the C header)
      - hdr/VFPSupport - Updated with new error numbers, SWI definitions
      - s/CSupport - Math support functions from the C library sources, required by SoftFloat
      - s/Errors - Added new error definitions
      - s/GetAll - Include support code if necessary. Add debug switch, plus optimisation switch for machines with 16 D registers
      - s/Instructions - Core data processing instruction emulation code. This file is included twice, once for single precision and once for double precision. The code calls through to the SoftFloat routines to perform the calculations.
      - s/Module - Adjust handling of undefined instruction vector to allow the support code to be installed instead of OldHandler if necessary. Initialise the support code as necessary. Add new SWIs & reason codes.
      - s/SupportCode - Undefined instruction handler which controls the rest of the support code. Also raises RISC OS errors as necessary (division by zero, etc.)
      - softfloat/* - The SoftFloat library sources. It's been tweaked in a few places for integration with the assembler support code, but otherwise no changes to the core logic were necessary.
      - Resources/UK/Messages - Updated with new error text
    Admin:
      Tested on Raspberry Pi & BB-xM
      Support code tested using the supplied test routines and the TestFloat tool (http://www.jhauser.us/arithmetic/TestFloat.html)
    
    
    Version 0.06. Tagged as 'VFPSupport-0_06'
    a5596610
hdr/** gitlab-language=armasm linguist-language=armasm linguist-detectable=true
s/** gitlab-language=armasm linguist-language=armasm linguist-detectable=true
*,ffb gitlab-language=bbcbasic linguist-language=bbcbasic linguist-detectable=true
c/** gitlab-language=c linguist-language=c linguist-detectable=true
**/c/** gitlab-language=c linguist-language=c linguist-detectable=true
h/** gitlab-language=c linguist-language=c linguist-detectable=true
**/h/** gitlab-language=c linguist-language=c linguist-detectable=true
s/CSupport - Apache licence
softfloat/* - SoftFloat licence (see softfloat/ReadMe)
Everything else - ROOL BSD licence
Note that the CSupport and SoftFloat sources are only included in the build if SUPPORTCODE is enabled in the makefile.
......@@ -28,11 +28,70 @@
# Makefile for VFPSupport
#
# Use machine type to determine whether support code is needed
# Can also be overridden on command line by specifying SUPPORTCODE
DEFSUPPORTCODE = FALSE
ifneq (,$(findstring ${MACHINE},All All32 ARM11ZF))
DEFSUPPORTCODE = TRUE
endif
SUPPORTCODE ?= ${DEFSUPPORTCODE}
COMPONENT = VFPSupport
HEADER1 = VFPSupport
ROM_SOURCE = GetAll.s
ASMHDRS = VFPSupport
OBJS = GetAll
HDRS =
CMHGFILE =
ASMDEFINES += -PD "SupportCode SETL {${SUPPORTCODE}}"
RAMASMDEFINES += -PD "standalone SETL {TRUE}" -PD "MergedMsgs SETS \"${MERGEDMSGS}\""
ifeq (${SUPPORTCODE},TRUE)
OBJS += softfloat classify
VPATH = softfloat
endif
include CModule
# We don't want to link to CLib
CLIB =
ROMCSTUBS =
ABSSYM =
CFLAGS += -apcs /nofp
# Force -cpu 5 when building for 'all' to reduce assembler support code
# requirements. This shouldn't pose a problem since the C code will only get hit
# once we've verified VFP hardware is present (i.e. ARMv5+ CPU)
ifneq (,$(findstring ${MACHINE},All All32))
CFLAGS += -cpu 5
endif
# decgen rules
ACTIONS = actions/common \
actions/ARMv7_VFP
ENCODINGS = Build:decgen.encodings.ARMv7 \
Build:decgen.encodings.ARMv7_nASIMD \
Build:decgen.encodings.ARMv7_VFP
DECGEN = <Tools$Dir>.Misc.decgen.decgen
classify.c: $(ACTIONS) head.c $(ENCODINGS)
$(DECGEN) -bits=32 -e -DCDP= -DLDC_STC= -DMRC_MCR= -DVFP1=(cond:4) "-DVFP2={ne(cond,15)}" -DAS1(X)=1111001[X] -DAS2=11110100 $(ENCODINGS) -valid -a $(ACTIONS) -pre head.c -o classify.c -prefix=classify_ -name=classify -default=UNDEFINED -updatecache cache/classify -maxmaskbits=3
classify.o: classify.c shared.h
${CC} ${CFLAGS} -o $@ classify.c
classify.oz: classify.c shared.h
${CC} ${CFLAGS} ${C_MODULE} -o $@ classify.c
shared.h: hdr.shared
${PERL} Build:Hdr2H hdr.shared $@
softfloat.o: shared.h
include StdTools
include AAsmModule
clean::
${RM} c.classify
${RM} h.shared
# Dynamic dependencies:
#{DictTokens}
# Regular errors
E00:No VFP/NEON hardware present
E01:Unsupported VFP/NEON version
E02:A requested VFP/NEON feature is unavailable
E03:Bad VFP context
E04:Bad VFPSupport_Features reason code
E06:Only one instance of VFPSupport can be active at a time
E07:Invalid flags passed to VFPSupport SWI
# Serious errors from support code
S00:No VFP context active
S01:VFP coprocessor not enabled
S02:VFP coprocessor enable state mismatch
S03:Unexpected VFP instruction
S04:Divide by zero in VFP suppport code
S05:Unknown VFP exception requested
# Actual floating point exception errors
IO:Vector floating point exception: invalid operation
DZ:Vector floating point exception: division by zero
OF:Vector floating point exception: overflow
UF:Vector floating point exception: underflow
IX:Vector floating point exception: inexact operation
ID:Vector floating point exception: input subnormal
File added
File added
File added
File added
......@@ -11,13 +11,13 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "0.05"
Module_Version SETA 5
Module_MajorVersion SETS "0.06"
Module_Version SETA 6
Module_MinorVersion SETS ""
Module_Date SETS "19 Oct 2012"
Module_ApplicationDate SETS "19-Oct-12"
Module_Date SETS "08 Feb 2014"
Module_ApplicationDate SETS "08-Feb-14"
Module_ComponentName SETS "VFPSupport"
Module_ComponentPath SETS "bsd/RiscOS/Sources/HWSupport/VFPSupport"
Module_FullVersion SETS "0.05"
Module_HelpVersion SETS "0.05 (19 Oct 2012)"
Module_ComponentPath SETS "mixed/RiscOS/Sources/HWSupport/VFPSupport"
Module_FullVersion SETS "0.06"
Module_HelpVersion SETS "0.06 (08 Feb 2014)"
END
/* (0.05)
/* (0.06)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.05
#define Module_MajorVersion_CMHG 0.06
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 19 Oct 2012
#define Module_Date_CMHG 08 Feb 2014
#define Module_MajorVersion "0.05"
#define Module_Version 5
#define Module_MajorVersion "0.06"
#define Module_Version 6
#define Module_MinorVersion ""
#define Module_Date "19 Oct 2012"
#define Module_Date "08 Feb 2014"
#define Module_ApplicationDate "19-Oct-12"
#define Module_ApplicationDate "08-Feb-14"
#define Module_ComponentName "VFPSupport"
#define Module_ComponentPath "bsd/RiscOS/Sources/HWSupport/VFPSupport"
#define Module_ComponentPath "mixed/RiscOS/Sources/HWSupport/VFPSupport"
#define Module_FullVersion "0.05"
#define Module_HelpVersion "0.05 (19 Oct 2012)"
#define Module_LibraryVersionInfo "0:5"
#define Module_FullVersion "0.06"
#define Module_HelpVersion "0.06 (08 Feb 2014)"
#define Module_LibraryVersionInfo "0:6"
#
# Copyright(c)2014, RISC OS Open Ltd
# Allrightsreserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# * Neither the name of RISC OS Open Ltd nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
# These actions will fully classify VFP instructions, up to and including VFPv4
# Any unpredictable instructions will also be flagged (as CLASS_NOT_VFP), as we
# can't guarantee that attempting to re-execute them won't result in further
# synchronous exceptions (plus they might completely trash the system!)
VABS_A2(D,sz,M,nonstandard)
{
COMMON_sz_nonstandard(0)
D32_CHECK(sz,D)
D32_CHECK(sz,M)
return class;
}
VADD_fp_A2(D,sz,N,M,nonstandard)
{
COMMON_sz_nonstandard(0)
D32_CHECK(sz,D)
D32_CHECK(sz,N)
D32_CHECK(sz,M)
return class;
}
VCMP_VCMPE_A1(D,sz,M,nonstandard)
{
COMMON_sz_nonstandard(0)
D32_CHECK(sz,D)
D32_CHECK(sz,M)
return class;
}
VCMP_VCMPE_A2(D,sz,nonstandard)
{
COMMON_sz_nonstandard(0)
D32_CHECK(sz,D)
return class;
}
VCVT_VCVTR_fp_int_VFP_A1(D,opc2,sz,M,nonstandard)
{
COMMON_sz_nonstandard(0)
if(!(opc2 & 4))
{
/* Int to float */
D32_CHECK(sz,D);
}
else
{
/* Float to int */
D32_CHECK(sz,M);
}
return class;
}
VCVT_fp_fx_VFP_A1(D,sf,nonstandard)
{
COMMON_nonstandard(CLASS_VFP3)
if(sf)
class |= CLASS_D;
else
class |= CLASS_S;
D32_CHECK(sf,D)
return class;
}
VCVT_dp_sp_A1(D,sz,M,nonstandard)
{
COMMON_nonstandard(CLASS_S | CLASS_D);
D32_CHECK(sz,M)
D32_CHECK(!sz,D)
return class;
}
VCVTB_VCVTT_hp_sp_VFP_A1(nonstandard)
{
int class = CLASS_VFP3 | CLASS_HP;
if(nonstandard)
return CLASS_NOT_VFP;
return class;
}
VDIV_A1(D,sz,N,M,nonstandard)
{
COMMON_sz_nonstandard(CLASS_DIV)
D32_CHECK(sz,D)
D32_CHECK(sz,N)
D32_CHECK(sz,M)
return class;
}
VFMA_VFMS_A2(D,sz,N,M,nonstandard)
{
COMMON_sz_nonstandard(CLASS_VFP4)
D32_CHECK(sz,D)
D32_CHECK(sz,N)
D32_CHECK(sz,M)
return class;
}
VFNMA_VFNMS_A1(D,sz,N,M,nonstandard)
{
COMMON_sz_nonstandard(CLASS_VFP4)
D32_CHECK(sz,D)
D32_CHECK(sz,N)
D32_CHECK(sz,M)
return class;
}
VLDM_A1(D:Vd,W,Rn,imm8,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
uint32_t regs = imm8>>1;
_UNPREDICTABLE((Rn==15) && W);
_UNPREDICTABLE(!regs || (regs > 16) || ((D_Vd+regs) > 32));
if(imm8 & 1)
{
_UNPREDICTABLE(D_Vd+regs > 16);
}
if(D_Vd+regs > 16)
class |= CLASS_D32;
return class;
}
VLDM_A2(Vd:D,W,Rn,imm8,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
uint32_t regs = imm8;
_UNPREDICTABLE((Rn==15) && W);
_UNPREDICTABLE(!regs || ((Vd_D+regs) > 32));
return class;
}
VLDR_A1(D,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
if(D)
class |= CLASS_D32;
return class;
}
VLDR_A2(nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
return class;
}
VMLA_VMLS_fp_A2(D,sz,N,M,nonstandard)
{
COMMON_sz_nonstandard(0)
D32_CHECK(sz,D)
D32_CHECK(sz,N)
D32_CHECK(sz,M)
return class;
}
VMOV_imm_A2(D,sz,nonstandard)
{
COMMON_sz_nonstandard(CLASS_VFP3)
D32_CHECK(sz,D)
return class;
}
VMOV_reg_A2(D,sz,M,nonstandard)
{
COMMON_sz_nonstandard(0)
D32_CHECK(sz,D)
D32_CHECK(sz,M)
return class;
}
VMOV_arm_A1(opc1,D,Rt,opc2,nonstandard)
{
int class = CLASS_NOT_CDP;
if(nonstandard || (opc1 & 2) || (opc2 & 3))
return CLASS_NOT_VFP;
if(D)
class |= CLASS_D32;
_UNPREDICTABLE(Rt==15);
return class;
}
VMOV_scalar_A1(U,opc1,N,Rt,opc2,nonstandard)
{
int class = CLASS_NOT_CDP;
if(nonstandard || U || (opc1 & 2) || (opc2 & 3))
return CLASS_NOT_VFP;
if(N)
class |= CLASS_D32;
_UNPREDICTABLE(Rt==15);
return class;
}
VMOV_1fp_A1(Rt,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
_UNPREDICTABLE(Rt==15);
return class;
}
VMOV_2fp_A1(op,Rt2,Rt,Vm:M,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
_UNPREDICTABLE((Rt==15) || (Rt2==15) || (Vm_M==31));
if(op)
{
_UNPREDICTABLE(Rt==Rt2);
}
return class;
}
VMOV_dbl_A1(op,Rt2,Rt,M,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
_UNPREDICTABLE((Rt==15) || (Rt2==15));
if(op)
{
_UNPREDICTABLE(Rt==Rt2);
}
if(M)
class |= CLASS_D32;
return class;
}
VMUL_fp_A2(D,sz,N,M,nonstandard)
{
COMMON_sz_nonstandard(0)
D32_CHECK(sz,D)
D32_CHECK(sz,N)
D32_CHECK(sz,M)
return class;
}
VNEG_A2(D,sz,M,nonstandard)
{
COMMON_sz_nonstandard(0)
D32_CHECK(sz,D)
D32_CHECK(sz,M)
return class;
}
VNMLA_VNMLS_VNMUL_A1(D,sz,N,M,nonstandard)
{
COMMON_sz_nonstandard(0)
D32_CHECK(sz,D)
D32_CHECK(sz,N)
D32_CHECK(sz,M)
return class;
}
VNMLA_VNMLS_VNMUL_A2(D,sz,N,M,nonstandard)
{
COMMON_sz_nonstandard(0)
D32_CHECK(sz,D)
D32_CHECK(sz,N)
D32_CHECK(sz,M)
return class;
}
VPOP_A1(D:Vd,imm8,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
uint32_t regs = imm8>>1;
_UNPREDICTABLE(!regs || (regs > 16) || ((D_Vd+regs) > 32));
if(imm8 & 1)
{
_UNPREDICTABLE(D_Vd+regs > 16);
}
if(D_Vd+regs > 16)
class |= CLASS_D32;
return class;
}
VPOP_A2(Vd:D,imm8,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
uint32_t regs = imm8;
_UNPREDICTABLE(!regs || ((Vd_D+regs) > 32));
return class;
}
VPUSH_A1(D:Vd,imm8,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
uint32_t regs = imm8>>1;
_UNPREDICTABLE(!regs || (regs > 16) || ((D_Vd+regs) > 32));
if(imm8 & 1)
{
_UNPREDICTABLE(D_Vd+regs > 16);
}
if(D_Vd+regs > 16)
class |= CLASS_D32;
return class;
}
VPUSH_A2(Vd:D,imm8,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
uint32_t regs = imm8;
_UNPREDICTABLE(!regs || ((Vd_D+regs) > 32));
return class;
}
VSQRT_A1(D,sz,M,nonstandard)
{
COMMON_sz_nonstandard(CLASS_SQRT)
D32_CHECK(sz,D)
D32_CHECK(sz,M)
return class;
}
VSTM_A1(D:Vd,W,Rn,imm8,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
uint32_t regs = imm8>>1;
_UNPREDICTABLE((Rn==15) && W);
_UNPREDICTABLE(!regs || (regs > 16) || ((D_Vd+regs) > 32));
if(imm8 & 1)
{
_UNPREDICTABLE(D_Vd+regs > 16);
}
if(D_Vd+regs > 16)
class |= CLASS_D32;
return class;
}
VSTM_A2(Vd:D,W,Rn,imm8,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
uint32_t regs = imm8;
_UNPREDICTABLE((Rn==15) && W);
_UNPREDICTABLE(!regs || ((Vd_D+regs) > 32));
return class;
}
VSTR_A1(D,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
if(D)
class |= CLASS_D32;
return class;
}
VSTR_A2(nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
return class;
}
VSUB_fp_A2(D,sz,N,M,nonstandard)
{
COMMON_sz_nonstandard(0)
D32_CHECK(sz,D)
D32_CHECK(sz,N)
D32_CHECK(sz,M)
return class;
}
VMRS_A1(reg,Rt,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
_UNPREDICTABLE((Rt==15) && (reg != REG_FPSCR));
if(!(VMRS_MASK & (1<<reg)))
return CLASS_NOT_VFP;
/* Follow ARMv7 rules and limit user mode to only the FPSCR register */
if((reg != REG_FPSCR) && !privileged_mode())
return CLASS_NOT_VFP;
return class;
}
VMSR_A1(reg,nonstandard)
{
COMMON_nonstandard(CLASS_NOT_CDP)
if(!(VMSR_MASK & (1<<reg)))
return CLASS_NOT_VFP;
/* Follow ARMv7 rules and limit user mode to only the FPSCR register */
if((reg != REG_FPSCR) && !privileged_mode())
return CLASS_NOT_VFP;
return class;
}
#
# Copyright (c) 2014, RISC OS Open Ltd
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# * Neither the name of RISC OS Open Ltd nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
# Common actions for ARM disassembly
UNDEFINED()
{
(void) OPCODE;
return CLASS_NOT_VFP;
}
UNPREDICTABLE()
{
(void) OPCODE;
return CLASS_NOT_VFP;
}
UNALLOCATED_HINT()
{
(void) OPCODE;
return CLASS_NOT_VFP;
}
PERMA_UNDEFINED()
{
(void) OPCODE;
return CLASS_NOT_VFP;
}
UNALLOCATED_MEM_HINT()
{
(void) OPCODE;
return CLASS_NOT_VFP;
}
/*
* Copyright (c) 2014, RISC OS Open Ltd
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of RISC OS Open Ltd nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include "classify.h"
/* This file has the generated disassembler source appended to it */
File added
/*
* Copyright (c) 2014, RISC OS Open Ltd
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of RISC OS Open Ltd nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef CLASSIFY_H
#define CLASSIFY_H
#include <stdint.h>
#include <stdbool.h>
#include "shared.h"
/* decgen bits */
#define RETURNTYPE int
#define PARAMDECL uint32_t opcode
#define PARAMS opcode
#define PARAMSCOMMA ,
#define OPCODE opcode
extern RETURNTYPE classify(PARAMDECL);
/* Helper macros */
#define COMMON_sz_nonstandard(base) \
(void) OPCODE; \
int class = base; \
if(nonstandard) \
return CLASS_NOT_VFP; \
if(sz) \
class |= CLASS_D; \
else \
class |= CLASS_S;
#define COMMON_nonstandard(base) \
(void) OPCODE; \
int class = base; \
if(nonstandard) \
return CLASS_NOT_VFP; \
#define D32_CHECK(sz,high) if((sz) && (high)) class |= CLASS_D32;
#define _UNPREDICTABLE(cond) if(cond) return CLASS_NOT_VFP;
/* Which registers are valid for reading/writing (in privileged modes) */
#define VMRS_MASK ((1<<REG_FPSID)+(1<<REG_FPSCR)+(1<<REG_MVFR1)+(1<<REG_MVFR0)+(1<<REG_FPEXC)+(1<<REG_FPINST)+(1<<REG_FPINST2))
#define VMSR_MASK ((1<<REG_FPSCR)+(1<<REG_FPEXC)+(1<<REG_FPINST)+(1<<REG_FPINST2))
static inline bool privileged_mode(void)
{
int value;
__asm
{
LDR value,[sl,#UserPSR]
}
return (value & 0xf);
}
#endif
......@@ -43,6 +43,7 @@ SWIClass SETS VFPSupportSWI_Name
AddSWI ActiveContext
AddSWI Version
AddSWI Features
AddSWI ExceptionDump
VFPSupportSWICheckValue * @
......@@ -83,6 +84,14 @@ VFPSupport_Field_RegDump * 5
; Reason codes for Features
VFPSupport_Features_SystemRegs * 0
VFPSupport_Features_VFPExceptions * 1
; Flags for ExceptionDump
VFPSupport_ExceptionDump_GetDump * 1 :SHL: 0
VFPSupport_ExceptionDump_GetContext * 1 :SHL: 1
VFPSupport_ExceptionDump_Clear * 1 :SHL: 2
VFPSupport_ExceptionDump_Create * 1 :SHL: 3
; VFP status register fields, as per ARMv7 ARM
......@@ -107,12 +116,14 @@ FPSCR_OFC * 1 :SHL: 2
FPSCR_UFC * 1 :SHL: 3
FPSCR_IXC * 1 :SHL: 4
FPSCR_IDC * 1 :SHL: 7
FPSCR_CUMULATIVE_FLAGS * FPSCR_IOC+FPSCR_DZC+FPSCR_OFC+FPSCR_UFC+FPSCR_IXC+FPSCR_IDC
FPSCR_IOE * 1 :SHL: 8
FPSCR_DZE * 1 :SHL: 9
FPSCR_OFE * 1 :SHL: 10
FPSCR_UFE * 1 :SHL: 11
FPSCR_IXE * 1 :SHL: 12
FPSCR_IDE * 1 :SHL: 15
FPSCR_ENABLE_FLAGS * FPSCR_IOE+FPSCR_DZE+FPSCR_OFE+FPSCR_UFE+FPSCR_IXE+FPSCR_IDE
FPSCR_LEN_SHIFT * 16
FPSCR_LEN_MASK * 7 :SHL: 16
FPSCR_STRIDE_SHIFT * 20
......@@ -143,6 +154,26 @@ FPSCR_N * 1 :SHL: 31
AddError VFPSupport_BadFeature, "Bad VFPSupport_Features reason code"
AddError VFPSupport_NoHW2, "VFPSupport module or VFP/NEON coprocessor not found" ; Generic error for VFP/NEON dependent programs to use. Where possible programs should use custom error text to specify the exact hardware required - VFPv1, NEON, etc.
AddError VFPSupport_Instanced, "Only one instance of VFPSupport can be active at a time"
AddError VFPSupport_BadFlags, "Invalid flags passed to VFPSupport SWI"
^ ErrorBase_VectorFloatingPoint
; Floating point exception errors
AddError VFPSupport_IO, "Vector floating point exception: invalid operation"
AddError VFPSupport_DZ, "Vector floating point exception: division by zero"
AddError VFPSupport_OF, "Vector floating point exception: overflow"
AddError VFPSupport_UF, "Vector floating point exception: underflow"
AddError VFPSupport_IX, "Vector floating point exception: inexact operation"
AddError VFPSupport_ID, "Vector floating point exception: input subnormal"
; Errors generated by the support code - numbered from top end of block down, to keep separate from the errors programmers should expect to see
AddError VFPSupport_SupCode_NoContext, "No VFP context active", ErrorBase_VectorFloatingPoint+&FF
AddError VFPSupport_SupCode_NotEN, "VFP coprocessor not enabled", ErrorBase_VectorFloatingPoint+&FE
AddError VFPSupport_SupCode_ENMismatch, "VFP coprocessor enable state mismatch", ErrorBase_VectorFloatingPoint+&FD
AddError VFPSupport_SupCode_Unexpected, "Unexpected VFP instruction", ErrorBase_VectorFloatingPoint+&FC
AddError VFPSupport_SupCode_SupDiv0, "Divide by zero in VFP support code", ErrorBase_VectorFloatingPoint+&FB
AddError VFPSupport_SupCode_UnkExcep, "Unknown VFP exception requested", ErrorBase_VectorFloatingPoint+&FA
OPT OldOpt
END
;
; Copyright (c) 2014, RISC OS Open Ltd
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of RISC OS Open Ltd nor the names of its contributors
; may be used to endorse or promote products derived from this software
; without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
OldOpt SETA {OPT}
OPT OptNoList+OptNoP1List
; Private header containing definitions that are shared with C code via Hdr2H
; Layout of the exception processing workspace
^ 0
XCRelocOffset # 4 ; C relocation offset - must be at the start
RoundingMode # 1
XFlags # 1 ; Extra flags about the exception
ExceptionFlags # 1
ExceptionEnable # 1
Reg_D # 4 ; Operand and result register numbers (*2 for D regs)
Reg_N # 4
Reg_M # 4
TheInstruction # 4 ; Instruction word being manipulated. Just use context FPINST?
TheFPEXC # 4 ; FPEXC being manipulated. Just use context FPEXC?
TheContext # 4 ; Pointer to context being manipulated
Workspace # 4 ; Module workspace pointer
UserRegisters # 64 ; R0-R15 for the caller's mode (assuming not FIQ)
UserPSR # 4 ; SPSR on entry
ASSERT ?UserRegisters = 16*4 ; Hdr2H doesn't do maths
; Flags for use by classify() to indicate the class of a given instruction
CLASS_NOT_VFP * 1 ; Not a VFP instruction
CLASS_NOT_CDP * 2 ; Is VFP, but not a VFP CDP instruction (i.e. not
; to be emulated by us)
CLASS_VFP3 * 4 ; VFPv3 required
CLASS_VFP4 * 8 ; VFPv4 required
CLASS_S * 16 ; Single precision support required
CLASS_D * 32 ; Double precision support required
CLASS_D32 * 64 ; D32 support required
CLASS_HP * 128 ; Half precision support required
CLASS_SQRT * 256 ; Square root support required
CLASS_DIV * 512 ; Divide support required
; Special register numbers
REG_FPSID * 0
REG_FPSCR * 1
REG_MVFR1 * 6
REG_MVFR0 * 7
REG_FPEXC * 8
REG_FPINST * 9
REG_FPINST2 * 10
OPT OldOpt
END
; Copyright 2014 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; Math functions taken from SharedCLibrary - just the bare minimum needed by
; softfloat
EXPORT __rt_udiv
EXPORT _ll_mul
EXPORT _ll_udiv
EXPORT _ll_shift_l
EXPORT _ll_ushift_r
EXPORT _ll_cmpu
; Redefine CLib macros to the general ones
MACRO
FunctionEntry $UsesSb, $SaveList, $MakeFrame
ASSERT "$UsesSb"=""
ASSERT "$MakeFrame"=""
LCLS Temps
LCLS TempsC
Temps SETS "$SaveList"
TempsC SETS ""
[ Temps <> ""
TempsC SETS Temps :CC: ","
]
Push "$TempsC.lr"
MEND
MACRO
Return $UsesSb, $ReloadList, $Base, $CC
ASSERT "$UsesSb"=""
LCLS Temps
LCLS TempsC
Temps SETS "$ReloadList"
TempsC SETS ""
[ Temps <> ""
TempsC SETS Temps :CC: ","
]
[ "$Base" = "LinkNotStacked" :LAND: "$ReloadList"=""
MOV$CC pc, lr
|
ASSERT "$Base"=""
Pull "$TempsC.pc", $CC
]
MEND
MACRO
Pop $Regs,$Caret,$CC,$Base
ASSERT "$Caret"=""
ASSERT "$Base"=""
Pull "$Regs", $CC
MEND
|__rt_udiv|
; Unsigned divide of a2 by a1: returns quotient in a1, remainder in a2
; Destroys a3 and ip
MOV a3, #0
RSBS ip, a1, a2, LSR #3
BCC u_sh2
RSBS ip, a1, a2, LSR #8
BCC u_sh7
MOV a1, a1, LSL #8
ORR a3, a3, #&FF000000
RSBS ip, a1, a2, LSR #4
BCC u_sh3
RSBS ip, a1, a2, LSR #8
BCC u_sh7
MOV a1, a1, LSL #8
ORR a3, a3, #&00FF0000
RSBS ip, a1, a2, LSR #8
MOVCS a1, a1, LSL #8
ORRCS a3, a3, #&0000FF00
RSBS ip, a1, a2, LSR #4
BCC u_sh3
RSBS ip, a1, #0
BCS dividebyzero
u_loop MOVCS a1, a1, LSR #8
u_sh7 RSBS ip, a1, a2, LSR #7
SUBCS a2, a2, a1, LSL #7
ADC a3, a3, a3
u_sh6 RSBS ip, a1, a2, LSR #6
SUBCS a2, a2, a1, LSL #6
ADC a3, a3, a3
u_sh5 RSBS ip, a1, a2, LSR #5
SUBCS a2, a2, a1, LSL #5
ADC a3, a3, a3
u_sh4 RSBS ip, a1, a2, LSR #4
SUBCS a2, a2, a1, LSL #4
ADC a3, a3, a3
u_sh3 RSBS ip, a1, a2, LSR #3
SUBCS a2, a2, a1, LSL #3
ADC a3, a3, a3
u_sh2 RSBS ip, a1, a2, LSR #2
SUBCS a2, a2, a1, LSL #2
ADC a3, a3, a3
u_sh1 RSBS ip, a1, a2, LSR #1
SUBCS a2, a2, a1, LSL #1
ADC a3, a3, a3
u_sh0 RSBS ip, a1, a2
SUBCS a2, a2, a1
ADCS a3, a3, a3
BCS u_loop
MOV a1, a3
MOV pc, lr
; Assume ARMv5+, but keep these switches in place so that any updates to the
; SCL code can easily be copied over to here
GBLL HaveCLZ
HaveCLZ SETL {TRUE}
GBLL HaveMULL
HaveMULL SETL {TRUE}
GBLL RuntimeArch
RuntimeArch SETL {FALSE}
; Multiply two 64-bit numbers
; In: (a1,a2),(a3,a4)
; Out: (a1,a2)
_ll_mul ROUT
FunctionEntry
[ RuntimeArch
CPUArch ip, lr
CMP ip, #CPUArch_v4
BCC mul_hardway
]
[ RuntimeArch :LOR: HaveMULL
; Have UMULL instruction
MOV ip, a1
UMULL a1, lr, a3, a1
MLA lr, ip, a4, lr
MLA a2, a3, a2, lr
Return
]
[ RuntimeArch :LOR: :LNOT: HaveMULL
mul_hardway ROUT
; No UMULL instruction
; Break the operation down thus:
; aaaaaaaa bbbb cccc
; * dddddddd eeee ffff
; ------------------
; cccc * ffff
; bbbb * ffff
; cccc * eeee
; bbbb * eeee
; aaaaaaaa * eeeeffff
; + dddddddd * bbbbcccc
MUL a2, a3, a2 ; msw starts as aaaaaaaa * eeeeffff
MLA a2, a4, a1, a2 ; msw += dddddddd * bbbbcccc
MOV lr, a3, LSR #16 ; lr = eeee from now on
MOV ip, a1, LSR #16 ; ip = bbbb from now on
SUB a4, a3, lr, LSL #16 ; a4 = ffff
SUB a3, a1, ip, LSL #16 ; a3 = cccc
MUL a1, a3, a4 ; lsw starts as cccc * ffff
MUL a4, ip, a4
MUL a3, lr, a3
ADDS a3, a4, a3 ; a3 = (bbbb * ffff + cccc * eeee) [0:31]
MOV a4, a3, RRX ; a4 = (bbbb * ffff + cccc * eeee) [1:32]
ADDS a1, a1, a3, LSL #16 ; lsw now complete
ADC a2, a2, a4, LSR #15
MLA a2, ip, lr, a2 ; msw completed by adding bbbb * eeee
Return
]
; Divide a uint64_t by another, returning both quotient and remainder
; In: dividend (a1,a2), divisor (a3,a4)
; Out: quotient (a1,a2), remainder (a3,a4)
_ll_udiv ROUT
FunctionEntry , "a1-v6,sl,fp"
; Register usage:
; v1,v2 = quotient (initially 0)
; v3,v4 = remainder (initially dividend)
; v5,v6 = divisor
; sl = CPU architecture
; fp used as a scratch register
; note none of our callees use sl or fp in their usual sense
Pop "v3-v6"
_ll_udiv_lateentry ROUT
MOV v1, #0
MOV v2, #0
; Calculate a floating point underestimate of the
; reciprocal of the divisor. The representation used is
; mantissa: 16 bits
; exponent: number of binary places below integers of lsb of mantissa
; The way the mantissa and exponent are calculated
; depends upon the number of leading zeros in the divisor.
[ RuntimeArch
CPUArch sl, lr
CMP sl, #CPUArch_v5T
CLZCS a1, v6
MOVCC a1, v6
BLCC soft_clz
|
[ HaveCLZ
CLZ a1, v6
|
MOV a1, v6
BL soft_clz
]
]
MOV fp, a1 ; fp = leading zeros in divisor
CMP fp, #16
BCS %FT10
; Divisor has 0..15 leading zeros.
MOV a2, v6, LSL fp
MOVS a1, v5
MOVEQS a1, a2, LSL #16
MOVNE a1, #1 ; round up to account for loss of accuracy
ADD a1, a1, a2, LSR #16 ; divisor for calculating mantissa
B %FT40
10 CMP v6, #0
BEQ %FT20
; Divisor has 16..31 leading zeros.
SUB a2, fp, #16
RSB a3, fp, #48
MOVS a1, v5, LSL a2
MOVNE a1, #1 ; round up to account for loss of accuracy
ADD a1, a1, v6, LSL a2
ADD a1, a1, v5, LSR a3 ; divisor for calculating mantissa
B %FT40
20
[ RuntimeArch
CMP sl, #CPUArch_v5T
CLZCS a1, v5
MOVCC a1, v5
BLCC soft_clz
|
[ HaveCLZ
CLZ a1, v5
|
MOV a1, v5
BL soft_clz
]
]
ADD fp, a1, #32 ; fp = leading zeros in divisor
CMP fp, #48
BCS %FT30
; Divisor has 32..47 leading zeros.
MOV a2, v5, LSL a1
MOVS a1, a2, LSL #16
MOVNE a1, #1 ; round up to account for loss of accuracy
ADD a1, a1, a2, LSR #16 ; divisor for calculating mantissa
B %FT40
30 CMP v5, #0
BEQ %FT99
; Divisor has 48..63 leading zeros.
SUB a2, a1, #16
MOV a1, v5, LSL a2 ; divisor for calculating mantissa
; drop through
40 MOV a2, #&80000000 ; dividend for calculating mantissa
BL __rt_udiv ; a1 = mantissa &8000..&10000
RSB a2, fp, #15+64 ; a2 = exponent
TST a1, #&10000
MOVNE a1, #&8000 ; force any &10000 mantissas into 16 bits
SUBNE a2, a2, #1
50 ; Main iteration loop:
; each time round loop, calculate a close underestimate of
; the quotient by multiplying through the "remainder" by the
; approximate reciprocal of the divisor.
; a1 = mantissa
; a2 = exponent
; Perform 16 (a1) * 64 (v3,v4) -> 80 (a3,a4,lr) multiply
[ RuntimeArch
CMP sl, #CPUArch_v4
BCC %FT51
]
[ RuntimeArch :LOR: HaveMULL
; Have UMULL instruction
UMULL a3, ip, v3, a1
UMULL a4, lr, v4, a1
ADDS a4, ip, a4
ADC lr, lr, #0
]
[ RuntimeArch
B %FT60
51
]
[ RuntimeArch :LOR: :LNOT: HaveMULL
; No UMULL instruction
; aaaa bbbb cccc dddd
; * eeee
; -------------------
; dddd * eeee
; cccc * eeee
; bbbb * eeee
; aaaa * eeee
MOV ip, v4, LSR #16
MOV fp, v3, LSR #16
SUB a4, v4, ip, LSL #16
SUB a3, v3, fp, LSL #16
MUL ip, a1, ip
MUL fp, a1, fp
MUL a4, a1, a4
MUL a3, a1, a3
MOV lr, ip, LSR #16
MOV ip, ip, LSL #16
ORR ip, ip, fp, LSR #16
MOV fp, fp, LSL #16
ADDS a3, a3, fp
ADCS a4, a4, ip
ADC lr, lr, #0
]
60 ; Shift down by exponent
; First a word at a time, if necessary:
SUBS ip, a2, #32
BCC %FT62
61 MOV a3, a4
MOV a4, lr
MOV lr, #0
SUBS ip, ip, #32
BCS %BT61
62 ; Then by bits, if necessary:
ADDS ip, ip, #32
BEQ %FT70
RSB fp, ip, #32
MOV a3, a3, LSR ip
ORR a3, a3, a4, LSL fp
MOV a4, a4, LSR ip
ORR a4, a4, lr, LSL fp
70 ; Now (a3,a4) contains an underestimate of the quotient.
; Add it to the running total for the quotient, then
; multiply through by divisor and subtract from the remainder.
; Sometimes (a3,a4) = 0, in which case this step can be skipped.
ORRS lr, a3, a4
BEQ %FT80
ADDS v1, v1, a3
ADC v2, v2, a4
[ RuntimeArch
CMP sl, #CPUArch_v4
MOVCS lr, a3
UMULLCS a3, ip, v5, lr
MLACS a4, v5, a4, ip
MLACS a4, v6, lr, a4
BCS %FT75
]
[ :LNOT: RuntimeArch :LAND: HaveMULL
MOV lr, a3
UMULL a3, ip, v5, lr
MLA a4, v5, a4, ip
MLA a4, v6, lr, a4
]
[ RuntimeArch :LOR: :LNOT: HaveMULL
; No UMULL instruction
; Proceeed as for mul_hardway
MUL a4, v5, a4
MLA a4, v6, a3, a4
MOV ip, a3, LSR #16
MOV lr, v5, LSR #16
SUB fp, a3, ip, LSL #16
SUB lr, v5, lr, LSL #16
MUL a3, fp, lr
Push "ip"
MUL ip, lr, ip
MOV lr, v5, LSR #16
MUL fp, lr, fp
ADDS fp, ip, fp
MOV ip, fp, RRX
ADDS a3, a3, fp, LSL #16
ADC a4, a4, ip, LSR #15
Pop "ip"
MLA a4, ip, lr, a4
]
75 SUBS v3, v3, a3
SBC v4, v4, a4
80 ; Termination condition for iteration loop is
; remainder < divisor
; OR
; quotient increment == 0
CMP v3, v5
SBCS lr, v4, v6
TEQCC lr, lr ; set Z if r < d (and preserve C)
ORRCSS lr, a3, a4 ; else Z = a3 and a4 both 0
BNE %BT50
; The final multiple of the divisor can get lost in rounding
; so subtract one more divisor if necessary
CMP v3, v5
SBCS lr, v4, v6
BCC %FT85
ADDS v1, v1, #1
ADC v2, v2, #0
SUBS v3, v3, v5
SBC v4, v4, v6
85
Push "v1-v4"
Return , "a1-v6,sl,fp"
99 ; Division by zero
Pop "v1-v6,sl,fp,lr"
B __rt_div0
; Shift a 64-bit number left
; In: (a1,a2),a3
; Out: (a1,a2)
_ll_shift_l ROUT
RSBS ip, a3, #32
MOVHI a2, a2, LSL a3
ORRHI a2, a2, a1, LSR ip
MOVHI a1, a1, LSL a3
Return ,, LinkNotStacked, HI
SUB ip, a3, #32
MOV a2, a1, LSL ip
MOV a1, #0
Return ,, LinkNotStacked
; Logical-shift a 64-bit number right
; In: (a1,a2),a3
; Out: (a1,a2)
_ll_ushift_r ROUT
RSBS ip, a3, #32
MOVHI a1, a1, LSR a3
ORRHI a1, a1, a2, LSL ip
MOVHI a2, a2, LSR a3
Return ,, LinkNotStacked, HI
SUB ip, a3, #32
MOV a1, a2, LSR ip
MOV a2, #0
Return ,, LinkNotStacked
; Compare two uint64_t numbers, or test two int64_t numbers for equality
; In: (a1,a2),(a3,a4)
; Out: Z set if equal, Z clear if different
; C set if unsigned higher or same, C clear if unsigned lower
; all registers preserved
_ll_cmpu ROUT
CMP a2, a4
CMPEQ a1, a3
MOV pc, lr ; irrespective of calling standard
END
......@@ -35,6 +35,7 @@
MakeInternatErrorBlock VFPSupport_BadFeature,,E04
; MakeInternatErrorBlock VFPSupport_NoHW2,,E05 - not used internally
MakeInternatErrorBlock VFPSupport_Instanced,,E06
MakeInternatErrorBlock VFPSupport_BadFlags,,E07
; Other errors
......