Commit 28c505b0 authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Add initial VFPv1/VFPv2 support

Detail:
  s/Module:
  - CheckHardware can now correctly determine that the ARM1176JZF-S is ARMv6, not ARMv7
  - Added initial support for VFPv1/v2; currently only supports implementations that use FSTMX/FLDMX standard format 1, and for which we know we can read the MVFR0/MVFR1 registers. I.e. only VFP11 supported at present.
  - Fixed null pointer dereference in ExamineContext when examining the active context
Admin:
  Tested on Raspberry Pi with high processor vectors
  Note there is no support code present, so using the coprocessor outside of RunFast mode will result in aborts.


Version 0.04. Tagged as 'VFPSupport-0_04'
parent b881f3cf
......@@ -11,13 +11,13 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "0.03"
Module_Version SETA 3
Module_MajorVersion SETS "0.04"
Module_Version SETA 4
Module_MinorVersion SETS ""
Module_Date SETS "20 Mar 2012"
Module_ApplicationDate SETS "20-Mar-12"
Module_Date SETS "21 Jul 2012"
Module_ApplicationDate SETS "21-Jul-12"
Module_ComponentName SETS "VFPSupport"
Module_ComponentPath SETS "bsd/RiscOS/Sources/HWSupport/VFPSupport"
Module_FullVersion SETS "0.03"
Module_HelpVersion SETS "0.03 (20 Mar 2012)"
Module_FullVersion SETS "0.04"
Module_HelpVersion SETS "0.04 (21 Jul 2012)"
END
/* (0.03)
/* (0.04)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.03
#define Module_MajorVersion_CMHG 0.04
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 20 Mar 2012
#define Module_Date_CMHG 21 Jul 2012
#define Module_MajorVersion "0.03"
#define Module_Version 3
#define Module_MajorVersion "0.04"
#define Module_Version 4
#define Module_MinorVersion ""
#define Module_Date "20 Mar 2012"
#define Module_Date "21 Jul 2012"
#define Module_ApplicationDate "20-Mar-12"
#define Module_ApplicationDate "21-Jul-12"
#define Module_ComponentName "VFPSupport"
#define Module_ComponentPath "bsd/RiscOS/Sources/HWSupport/VFPSupport"
#define Module_FullVersion "0.03"
#define Module_HelpVersion "0.03 (20 Mar 2012)"
#define Module_LibraryVersionInfo "0:3"
#define Module_FullVersion "0.04"
#define Module_HelpVersion "0.04 (21 Jul 2012)"
#define Module_LibraryVersionInfo "0:4"
......@@ -182,6 +182,14 @@ CheckHardware
CMP r4, #&F<<20
MCRNE p15,0,r2,c1,c0,2 ; restore original CPACR
BNE NoVFP_v6v7
CMP r0, #&F
BNE %FT10
; Both ARMv6 and ARMv7 identify themselves with &F in the main ID register
; To work out which is which, it looks like the only (or easiest) way is to check the cache type register
MRC p15, 0, r4, c0, c0, 1
TST r4, #&80000000
MOVEQ r0, #&7
10
; VFP coprocessors exist and are now enabled, read FPSID
myISB ,r4 ; ISB to ensure that the coprocessors really are enabled
myVMRS ,r4, FPSID
......@@ -237,9 +245,21 @@ GotFPSID
CMP r3, #&30000
BNE BadVFP
B GoodVFP
CheckFPSIDv5 ; TODO
CheckFPSIDv6 ; TODO
CheckFPSIDv5
CheckFPSIDv6
; v5/v6 version. Should be VFPv1 or VFPv2.
AND r3, r4, #&F0000
CMP r3, #&20000
CMPNE r3, #&10000
BNE BadVFP
; Currently only support implementations that use FSTMX/FLDMX standard format 1 (i.e. we can just use VLDM/VSTM)
TST r4, #3:SHL:21
BNE BadVFP
B GoodVFP
BadVFP
NoMVFR ; Currently we don't cope with situations where the MVFR registers are absent
; Restore CPACR if ARMv6+
CMP r0, #&7
MCRGE p15,0,r2,c1,c0,2
......@@ -248,6 +268,13 @@ BadVFP
MSR CPSR_c, R1
ADRL r0, ErrorBlock_VFPSupport_BadHW
B ReturnError_Stacked
HasMVFRTable
DCW &FFF0 ; FPSID mask (part & variant fields)
DCW &20B0 ; VFP11
DCW 0
ALIGN
GoodVFP
; r0 = ARM version
; r1 = old PSR
......@@ -256,10 +283,24 @@ GoodVFP
; r4 = FPSID
; Read MVFR0/1 if they're available
CMP r3, #&2<<16
BLT %FT10
BGE HasMVFR ; Subarchitecture 2+ is required to have them
; In subarchitecture 1 and below, the registers are optional.
; E.g. VFP9-S doesn't have them but VFP11 does, even though they're both subarchitecture 1/VFPv2.
; Search through a list of VFP variants which are known to contain the registers
ADR r7, HasMVFRTable
LDRH r8, [r7], #2
AND r8, r8, r4
10
LDRH r9, [r7], #2
CMP r9, #0
BEQ NoMVFR
CMP r9, r8
BEQ HasMVFR
B %BT10
HasMVFR
myVMRS ,r5,MVFR0
myVMRS ,r6,MVFR1
10
; Done for now, make sure VFP access is disabled
; For the moment we just disable access via the FPEXC.EN bit. This will disable everything except VMSR & VMRS from privileged modes
MOV r7, #0
......@@ -267,7 +308,7 @@ GoodVFP
; Restore interrupts
MSR CPSR_c, R1
; Store our results
; TODO - Calculate fake MVFR0/MVFR1 values for pre-VFPv3
; TODO - Calculate fake MVFR0/MVFR1 values where necessary
MOV r3, r3, LSR #16
STRB r3, VFPVersion
STR r4, SoftFPSID
......@@ -581,6 +622,7 @@ SWI_ExamineContext
BL SWI_ChangeContext ; Deactivate it
BLVC SWI_ChangeContext ; Reactivate it
MOVVS pc, r3
MOV r0, r2
MOV lr, r3
10
; Check the FPEXC value in the dump as a method of determining which format of descriptor block we should use
......
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