Commit 3a3d343d authored by Robert Sprowson's avatar Robert Sprowson

Fix for the wrong TRB being flushed to RAM when building TD rings

For an N entry ring, the 0th TRB (which is written last, to avoid some controller quirks) is written to RAM but the N+1th is what gets synced - should sync the 0th.
From NetBSD revision 1.47, ref http://gnats.netbsd.org/cgi-bin/query-pr-single.pl?number=51199

Version 0.14. Tagged as 'XHCIDriver-0_14'
parent 55734f42
/* (0.13)
/* (0.14)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.13
#define Module_MajorVersion_CMHG 0.14
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 03 Jun 2016
#define Module_MajorVersion "0.13"
#define Module_Version 13
#define Module_MajorVersion "0.14"
#define Module_Version 14
#define Module_MinorVersion ""
#define Module_Date "03 Jun 2016"
......@@ -18,6 +18,6 @@
#define Module_ComponentName "XHCIDriver"
#define Module_ComponentPath "mixed/RiscOS/Sources/HWSupport/USB/Controllers/XHCIDriver"
#define Module_FullVersion "0.13"
#define Module_HelpVersion "0.13 (03 Jun 2016)"
#define Module_LibraryVersionInfo "0:13"
#define Module_FullVersion "0.14"
#define Module_HelpVersion "0.14 (03 Jun 2016)"
#define Module_LibraryVersionInfo "0:14"
......@@ -2221,7 +2221,7 @@ xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr,
xhci_trb_put(&xr->xr_trb[xr->xr_ep], htole64(parameter),
htole32(status), htole32(control));
usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1,
usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * xr->xr_ep, XHCI_TRB_SIZE * 1,
BUS_DMASYNC_PREWRITE);
xr->xr_cookies[xr->xr_ep] = cookie;
}
......
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