Fix for the wrong TRB being flushed to RAM when building TD rings
For an N entry ring, the 0th TRB (which is written last, to avoid some controller quirks) is written to RAM but the N+1th is what gets synced - should sync the 0th. From NetBSD revision 1.47, ref http://gnats.netbsd.org/cgi-bin/query-pr-single.pl?number=51199 Version 0.14. Tagged as 'XHCIDriver-0_14'
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