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Commit 66844ced authored by Jeffrey Lee's avatar Jeffrey Lee

Issue CLREX on return from the FIQ handler

Detail:
  s/regaccess - Issue CLREX on return from the FIQ handler, just in case we start using exclusive access instructions from within the handler. Update PSR manipulation code to use CPS in preference to MSR.
Admin:
  Tested on Raspberry Pi


Version 0.28. Tagged as 'DWCDriver-0_28'
parent 1a000a96
/* (0.27)
/* (0.28)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.27
#define Module_MajorVersion_CMHG 0.28
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 02 May 2016
#define Module_Date_CMHG 15 Jun 2016
#define Module_MajorVersion "0.27"
#define Module_Version 27
#define Module_MajorVersion "0.28"
#define Module_Version 28
#define Module_MinorVersion ""
#define Module_Date "02 May 2016"
#define Module_Date "15 Jun 2016"
#define Module_ApplicationDate "02-May-16"
#define Module_ApplicationDate "15-Jun-16"
#define Module_ComponentName "DWCDriver"
#define Module_ComponentPath "mixed/RiscOS/Sources/HWSupport/USB/Controllers/DWCDriver"
#define Module_FullVersion "0.27"
#define Module_HelpVersion "0.27 (02 May 2016)"
#define Module_LibraryVersionInfo "0:27"
#define Module_FullVersion "0.28"
#define Module_HelpVersion "0.28 (15 Jun 2016)"
#define Module_LibraryVersionInfo "0:28"
......@@ -91,8 +91,7 @@ DWC_WRITE_REG64
; void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask)
DWC_MODIFY_REG32
MRS ip, CPSR
ORR a4, ip, #I32_bit+F32_bit
MSR CPSR_c, a4
CPSID if
LDR a4, [a1]
myDSB
BIC a4, a4, a2
......@@ -108,23 +107,18 @@ mb
; void local_fiq_disable(void)
local_fiq_disable
MRS a1, CPSR
ORR a1, a1, #F32_bit
MSR CPSR_c, a1
CPSID f
MOV pc, lr
; void local_fiq_enable(void)
local_fiq_enable
MRS a1, CPSR
BIC a1, a1, #F32_bit
MSR CPSR_c, a1
CPSIE f
MOV pc, lr
; int _local_irq_save(void)
|_local_irq_save|
MRS a1, CPSR
ORR a2, a1, #I32_bit
MSR CPSR_c, a2
CPSID i
MOV pc, lr
; void local_irq_restore(int)
......@@ -162,16 +156,14 @@ install_fiq ROUT
LDMIA a3, {a3-a4}
STMIA a1, {a3-a4}
; Set up the FIQ mode registers
MRS a3, CPSR
EOR a4, a3, #FIQ32_mode :EOR: SVC32_mode
MSR CPSR_c, a4
CPS #FIQ32_mode
ADD sp, a1, a2
ADD sl, a1, #540
MOV fp, #0
MOV v5, v3 ; i.e. r8
MOV v6, v1
MOV ip, v2
MSR CPSR_c, a3
CPS #SVC32_mode
LDMFD sp!, {a1-a2,v1-v3,pc}
FIQcode
......@@ -181,6 +173,7 @@ FIQcode
MOV a2, ip
myDSB
BLX v5
CLREX
LDMFD sp!, {a1-a4,ip,pc}^
FIQcode_end
......
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